Unit-I digital electronics .

10211CS201-DIGITAL ELECTRONICS
Slot :S2/S3
Category : Program Core
UNIT-I
School of Computing
Department of Computer Science & Engineering
Course Handling Faculty :
Dr. S. Yazhinian
Assistant Professor

Program Core
2
Preamble
 The primary aim of this course is to understand the fundamentals
behind the digital logic design. From that students can gain the
experience, to design any digital circuits and systems.
 The course includes fundamentals of Boolean algebra, combinational,
sequential circuits and applications of digital electronics.
 Students can learn the basic programming concepts to implement digital
circuits using hardware description language.

CO
Nos.
Course Outcomes
Knowledge Level
(Based on revised
Bloom’s
taxonomy)
CO1
Apply the simplification of Boolean expressions
using K – Map method and designing
Combinational circuits.
K3
4/10/2024 Dr. S. Yazhinian, AP/ CSE Digital Electronics
Program Core
3

Correlation of COs with POs
Program Core
4
COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO 2 PSO 3
CO1 H M M L H L
CO2 M M M L L
CO3 H M H L M
CO4 M M M
CO5 M M M L L L

Course Outcome – NBA-EAC-CAC
Program Core
5
Course Outcomes
Correlates to
Program
Outcomes:
NBA
Correlate
s to
Student
Outcomes
: EAC
Correlates
to Student
Outcomes:
CAC
CO1: Apply the simplification of Boolean
expressions using K – Map method and
designing Combinational circuits.
a, b, c, d, g, j 1,2,3,4,5,6 1,2,6
CO2: Outline the combinational building
blocks & memory elements.
a, b, d, j 1,2,3,6 1,2,6
CO3: Design the combinational and
sequential circuits using hardware
description language.
a, b, c, d, g 1,2,3,4,5,6 1,2,6
CO4: Solve the asynchronous sequential
circuits for given applications
a, b, g 1,2,6,7 1,2,6
CO5: Explain the applications of digital
electronics
a, b, g, j 1,2,4,5,6,7 1,2,6

Syllabus
Program Core
6
UNIT–I: DIGITAL FUNDAMENTALS AND COMBINATIONAL CIRCUITS 10
Introduction to Boolean algebra and Switching Functions; Boolean Minimization using K Map and Tabulation
method; combinational circuits: Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor –
Parallel binary adder, parallel binary Subtractor – Fast Adder - Carry Look Ahead adder – Serial Adder/Subtractor
- BCD adder – Binary Multiplier – Binary Divider - Multiplexer/ Demultiplexer – decoder - encoder – parity
checker – parity generators – code converters - Magnitude Comparator.
UNIT -II: SEQUENTIAL CIRCUITS 10
Flip Flops and Memory devices: RAM – Static and Dynamic, ROM, PROM, EPROM, EEPROM; Counters and Shift
registers: Binary, BCD and programmable modulo counters, Shift register counters; Sequential circuit design:
using Mealy and Moore model.
UNIT III: INTRODUCTION TO HARDWARE DESCRIPTION LANGUAGE 10
Introduction to Verilog / VHDL- Structural, Dataflow and Behavioral modeling. Structural, Dataflow and
Behavioral modeling of combinational logic circuits (Multiplexer, Demultiplexer, decoder and encoder). Structural,
Dataflow and Behavioral modeling of sequential logic circuits (counters and shift registers).
UNIT IV: ASYNCHRONOUS SEQUENTIAL CIRCUITS 10
Analysis Procedure, Circuits with latches; Design Procedure, Reduction of state and flow table; Race free state
assignment; Hazards; ASM chart; Design examples.
UNIT V: APPLICATIONS OF DIGITAL ELECTRONICS 5
Multiplexing displays - Frequency counters - Time measurements - using the ADC0804 - Slope alone operation,
span adjust, zero shift, testing - microprocessor compatible A/D converters.

4/10/20
24
Dr. S. Yazhinian, AP/ CSE - Digital Electronics
Recommended Textbooks
7
T1. M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India
Pvt. Ltd., Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.
T2. Donald .P.Leach, Digital principles and applications, 7th Edition,
McGraw-Hill, 2012.
Recommended References
R1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006.
R2. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education
Inc, New Delhi, 2003 Donald D.Givone, Digital Principles and Design,
TMH.
R3. William H. Gothmann, Digital Electronics, 2nd Edition, PHI, 1982.

4/10/20
24
ONLINE RESOURCES
8
1. http://www.wiley.com/legacy/wileychi/mblin/supp/student/LN08Co
mbinationalLogicModules.pdf
2. http://www.learnabout-electronics.org
3. www.nptel.com/digitalelectronics/iitkanpur/
4. www.mooc.org

Applications of Digital Electronics
Program Core
9
• Digital circuits are a part of all the important electronic
devices.
• It can be used for designing the display of watch or a
countdown timer.
• We use digital circuits in complex processes like Rocket
Science and Quantum Computing.
• Digital circuits are also used in traffic lights and
automatic glass doors in offices and restaurants.

Opportunities
Program Core
10
• Electronics Hardware Engineer
• Hardware Circuit Design Engineer

4/10/20
24
Unit I - Syllabus
11
UNIT–I: DIGITAL FUNDAMENTALS AND COMBINATIONAL
CIRCUITS 10
Introduction to Boolean algebra and Switching Functions; Boolean
Minimization using K Map and Tabulation method; combinational circuits:
Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor
– Parallel binary adder, parallel binary Subtractor – Fast Adder - Carry Look
Ahead adder – Serial Adder/Subtractor - BCD adder – Binary Multiplier –
Binary Divider - Multiplexer/ Demultiplexer – decoder - encoder – parity
checker – parity generators – code converters - Magnitude Comparator.
Dr. S. Yazhinian, AP/ CSE Digital Electronics

4/10/2024
Recommended Textbooks
12
T1. M. Morris Mano, Digital Design, 3rd Edition, Prentice Hall of India
Pvt. Ltd., Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.
T2. Donald .P.Leach, Digital principles and applications, 7th Edition,
McGraw-Hill, 2012.
Recommended References
R1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006.
R2. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education
Inc, New Delhi, 2003 Donald D.Givone, Digital Principles and Design,
TMH.
R3. William H. Gothmann, Digital Electronics, 2nd Edition, PHI, 1982.

4/10/2024
Unit 1 - Syllabus
13
UNIT I - The Wireless Channel 9
 Introduction to Boolean algebra and Switching Functions
 Boolean Minimization using K Map and Tabulation method
 Combinational circuits:
• Half adder and Full Adder
• Half subtractor and Full subtractor
• Parallel binary Adder, Subtractor
• Fast Adder - Carry Look Ahead adder
• Serial Adder/Subtractor
• BCD adder

4/10/2024
Unit 1 - Syllabus
14
• Binary Multiplier and Divider
• Multiplexer and Demultiplexer
• Decoder and Encoder
• Parity checker and Parity generators
• Code converters
• Magnitude Comparator.

4/10/2024
Unit 1
15
Introduction to Boolean Algebra
Introduction to Boolean
algebra and Switching
Functions

4/10/2024
Introduction to Boolean algebra and Switching
Functions
16
• As well as the logic symbols “0” and “1” being
used to represent a digital input or output, we can
also use them as constants for a permanently
“Open” or “Closed” circuit or contact respectively.
• A set of rules or Laws of Boolean Algebra
expressions have been invented to help reduce the
number of logic gates needed to perform a
particular logic operation resulting in a list of
functions or theorems known commonly as
the Laws of Boolean Algebra.

4/10/2024
Functions
17
• Boolean Algebra is the mathematics we use to analyse
digital gates and circuits. We can use these “Laws of
Boolean” to both reduce and simplify a complex Boolean
expression in an attempt to reduce the number of logic
gates required.
• The variables used in Boolean Algebra only have one of
two possible values, a logic “0” and a logic “1” but an
expression can have an infinite number of variables all
labelled individually to represent inputs to the expression,
For example, variables A, B, C etc, giving us a logical
expression of A + B = C, but each variable can ONLY be a
0 or a 1.

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Functions
18
Examples of these individual laws of Boolean, rules and
theorems for Boolean Algebra are given in the following
table.

4/10/2024
Functions
19
Truth Tables for the Laws of Boolean
Dr. S. Yazhinian, AP/ CSE-Digital Electronics

4/10/2024
Functions
20
Truth Tables for the Laws of Boolean

Logic Gates
• Logic gates are abstractions of electronic circuit
components that operate on one or more input signals
to produce an output signal.
2-Input AND 2-Input OR NOT (Inverter)
A A
A
B B
F G H
F = A•B G = A+B H = A’
10-04-2024 21

Boolean
Algebra
Properties
Let X: boolean variable, 0,1: constants
1. X + 0 = X -- Zero Axiom
2. X • 1 = X -- Unit Axiom
3. X + 1 = 1 -- Unit Property
4. X • 0 = 0 -- Zero Property
5. X + X = X -- Idepotence
6. X • X = X -- Idepotence
7. X + X’ = 1 -- Complement
8. X • X’ = 0 -- Complement
9. (X’)’ = X -- Involution
10-04-2024 22

Duality
With respect to duality, Identities 1 – 8 have
the following relationship:
1. X + 0 = X 2. X • 1 = X (dual of 1)
3. X + 1 = 1 4. X • 0 = 0 (dual of 3)
5. X + X = X 6. X • X = X (dual of 5)
7. X + X’ = 1 8. X • X’ = 0 (dual of 8)
10-04-2024 23

Basic
Properties
(Laws)
• Commutative Law
X + Y = Y + X
X · Y = Y · X
• Associative Law
X+(Y+Z)=(X+Y)+Z
X(YZ) = (XY)Z
• Distributive Law
X(Y+Z) =XY+XZ
X+YZ=(X+Y)(X+Z)
• DeMorgan’s Theorem
(X + Y)’ = X’ · Y’
(XY)’ = X’ + Y’
10-04-2024 24

Minterm
Denoted by mj, where j is the decimal equivalent of the
minterm’s corresponding binary combination (bj).
A variable in mj is complemented if its value in bj is 0,
otherwise is uncomplemented.
Example: Assume 3 variables (A,B,C), and j=3. Then, bj = 011
and its corresponding minterm is denoted by mj = A’BC
a product term in which all the variables appear exactly
once, either complemented or uncomplemented
10-04-2024 25

Maxterm
Denoted by Mj, where j is the decimal equivalent of the
maxterm’s corresponding binary combination (bj).
A variable in Mj is complemented if its value in bj is 1,
otherwise is uncomplemented.
Example: Assume 3 variables (A,B,C), and j=3. Then, bj = 011
and its corresponding maxterm is denoted by Mj = A+B’+C’
a sum term in which all the variables appear exactly once,
either complemented or uncomplemented
10-04-2024 26

Truth Table
notation for
Minterms
and
Maxterms
x
4
y
2
z
1
Minterm Maxterm
0 0 0 x’y’z’ = m0 x+y+z = M0
0 0 1 x’y’z = m1 x+y+z’ = M1
0 1 0 x’yz’ = m2 x+y’+z = M2
0 1 1 x’yz = m3 x+y’+z’= M3
1 0 0 xy’z’ = m4 x’+y+z = M4
1 0 1 xy’z = m5 x’+y+z’ = M5
1 1 0 xyz’ = m6 x’+y’+z = M6
1 1 1 xyz = m7 x’+y’+z’ = M7
10-04-2024 27

Canonical
Forms
• Any Boolean function F( ) can be
expressed as a unique sum of
minterms and a unique product of
maxterms (under a fixed variable
ordering).
• In other words, every function F() has
two canonical forms:
• Canonical Sum-Of-Products (sum of
minterms)-∑ Eg: F(a,b,c) = ∑ m(1,2,4,6)
• Canonical Product-Of-Sums (product of
maxterms)-∏ Eg: f1(a,b,c) = ∏ M(0,3,5,7)
10-04-2024 28

Conversion
Between
Canonical
Forms
• Replace ∑ with ∏ (or vice versa) and
replace those j’s that appeared in the
original form with those that do not.
• Example:
f1(a,b,c) = a’b’c + a’bc’ + ab’c’ + abc’
= m1 + m2 + m4 + m6
= ∑(1,2,4,6)
= ∏(0,3,5,7)
= (a+b+c)•(a+b’+c’)•(a’+b+c’)•(a’+b’+c’)
10-04-2024 29

Conversion of
SOP from
standard to
canonical
form
• Expand non-canonical terms by
inserting equivalent of 1 in each missing
variable x:
(x + x’) = 1
• Remove duplicate minterms
• f1(a,b,c) = a’b’c + bc’ + ac’
= a’b’c + (a+a’)bc’ + a(b+b’)c’
= a’b’c + abc’ + a’bc’ + abc’ + ab’c’
= a’b’c + abc’ + a’bc’ + ab’c’
= m1,m6,m2,m4
f1(a,b,c)= ∑ (1,2,4,6)
10-04-2024 30

Conversion
of POS from
standard to
canonical
form
• Expand noncanonical terms by adding 0 in
terms of missing variables (e.g., xx’ = 0)
and using the distributive law
• Remove duplicate maxterms
• f1(a,b,c) = (a+b+c)•(b’+c’)•(a’+c’)
= (a+b+c)•(aa’+b’+c’)•(a’+bb’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•
(a’+b+c’)•(a’+b’+c’)
= (a+b+c)•(a+b’+c’)•(a’+b’+c’)•(a’+b+c’)
= M0,M3,M7,M5
F1(a,b,c)= ∏(0,3,5,7)
10-04-2024 31

Boolean Minimization using
K Map and Tabulation method
10-04-2024 32

Karnaugh Maps (K
Map)
 Karnaugh maps (K-maps)
are graphical
representations of
boolean functions.
 One map cell
corresponds to a row in
the truth table.
 Also, one map cell
corresponds to a minterm
or a maxterm in the
boolean expression
10-04-2024 33

K Map Types
Two-Variable K Map
Three-Variable K Map
Four-Variable K Map
Don't Care Conditions for all variable
10-04-2024 34

Two-Variable K
Map
m3
m2
1
m1
m0
0
1
0
x
y
0 1
2 3
NOTE: ordering of variables is IMPORTANT for
f(x,y), x is the row, y is the column.
Cell 0 represents x’y’; Cell 1 represents x’y;
etc. If a minterm is present in the function,
then a 1 is placed in the corresponding cell.
Cell = 2n ,where n is a number of variables
10-04-2024 35

Two-Variable K Map
For the case of 2 variables, we form a map consisting of 22=4 cells
as shown in Figure
B
A
Y
X
0 1
0
1
Y
X
0 1
0
1
Y
X
0 1
0
1
Y
X
Y
X
XY
Y
X 
Y
X 
Y
X 
Y
X 
Maxterm Minterm
0 1
2 3
00
Y
X
01
10 11
y
y
x
x
10-04-2024 36

Example 1 on
Two-Variable K Map
2-variable Karnaugh maps are trivial but can be used to introduce
the methods you need to learn.
Simplify the following Boolean function F(x,y)=∑(1,2,3)
y
x
0 1
0
1
1
1
1
x
y
F(x,y)=x+y
0
y
y
x
x
0 1
2 3
10-04-2024 37

Example 2 on
Two-Variable K Map
Simplify the following Boolean function F(x,y)=∑(0,1)
y
x
0 1
0
1
1
0
0
1
y
y
x
x
0 1
2 3
x
x
y
x
F 
)
,
(
10-04-2024 38

y
x
0 1
0
1
1
0
1
0
y
y
x
x
0 1
2 3
y
x
y
x
y
x
y
x
F 

)
,
(
y
x
10-04-2024 Dr. S. Yazhinian, AP/ CSE - Digital Electronics 39

y
x
0 1
0
1
0
1
0
1
y
y
x
x
0 1
2 3
y
x
xy
y
x
y
x
F 

)
,
(
xy

10
01 11
00
1
0
x
yz
NOTE: ordering of variables is IMPORTANT for
f(x,y,z), x is the row, y&z is the column.
Cell 0 represents x’y’z’; Cell 1 represents
x’y’z; etc. If a minterm is present in the
function, then a 1 is placed in the
corresponding cell.
4 5 6
7
m0 m1 m3
m2
m4 m5 m7 m6
z
y z
y yz z
y
x
x
2
3
1
0

10
01 11
00
1
0
A
BC
4 5 6
7
0 0 1 1
1 1 0 0
C
B C
B BC C
B
A
A
2
3
1
0
Example 1 on
Simplify the following Boolean function F(A,B,C)=∑(2,3,4,5)
B
A
B
A
B
A
B
A
C
B
A
F 

)
,
,
(

10
01 11
00
1
0
A
BC
4 5 6
7
0 0 1 0
1 0 1 1
C
B C
B BC C
B
A
A
2
3
1
0
Example 2 on
AB
C
A
C
A
BC
C
B
A
F 

)
,
,
(
BC
C
B
A

10
01 11
00
1
0
A
BC
4 5 6
7
1 0 0 1
1 1 0 1
C
B C
B BC C
B
A
A
2
3
1
0
Example 3 on
Simplify the following Boolean function F(A,B,C)=∑(0,2,4,5,6)
B
A
B
A
C
C
B
A
F 

)
,
,
(
C

10
01 11
00
1
0
A
BC
4 5 6
7
1 0 1 1
1 0 0 1
C
B C
B BC C
B
A
A
2
3
1
0
Example 4 on
B
A
B
A
C
C
B
A
F 

)
,
,
(
C

10
01 11
00
1
0
A
BC
4 5 6
7
1 1 0 0
0 1 1 0
C
B C
B BC C
B
A
A
2
3
1
0
Example 5 on
B
A
AC
B
A
C
B
A
F 

)
,
,
(
AC

10
01 11
00
1
0
A
BC
4 5 6
7
0 1 1 1
0 0 1 1
C
B C
B BC C
B
A
A
2
3
1
0
Example 6 on
B
B
C
A
C
B
A
F 

)
,
,
(
C
A

10
01 11
00
1
0
A
BC
4 5 6
7
0 0 1 0
0 1 1 1
C
B C
B BC C
B
A
A
2
3
1
0
Example 7 on
BC
AC
AB
BC
AC
C
B
A
F 


)
,
,
(
AB

10
01 11
00
1
0
A
BC
4 5 6
7
0 1 1 1
0 1 1 0
C
B C
B BC C
B
A
A
2
3
1
0
Example 8 on
C
C
B
A
C
B
A
F 

)
,
,
(
B
A

10
01 11
00
1
0
A
BC
4 5 6
7
1 0 0 1
1 1 1 1
C
B C
B BC C
B
A
A
2
3
1
0
Example 9 on
Simplify the following Boolean function F(A,B,C)=∑(0,2,4,5,6,7)
A
C
A
C
B
A
F 

)
,
,
(
C

10
01 11
00
01
00
wx
yz
4 5 6
7
m0 m1 m3
m2
m4 m5 m7 m6
z
y z
y yz z
y
x
w
x
w
2
3
1
0
Four-Variable K Map
8 9 10
11
m12 m13 m15 m14
m8 m9 m11 m10
14
15
13
12
11
10
wx
x
w
• Top cells are adjacent to bottom cells. Left-edge cells
are adjacent to right-edge cells.
• Note variable ordering (wxyz) or (ABCD) or (PQRS).

10
01 11
00
01
00
AB
CD
4 5 6
7
D
C D
C CD D
C
B
A
B
A
Example 1 on
Four-Variable K Map
8 9 10
11
1 1 0 0
1 1 0 1
14
15
13
12
11
10
AB
B
A
Simplify the following Boolean function F(A,B,C,D)=∑(0,1,2,4,5,7,8,9,10,12,13)
BD
A
D
B
C
D
C
B
A
F 


)
,
,
,
(
1 1 0 1
1 1 1 0
2
3
1
0
C
BD
A
D
B

10
01 11
00
01
00
AB
CD
4 5 6
7
D
C D
C CD D
C
B
A
B
A
Example 2 on
Four-Variable K Map
8 9 10
11
0 0 1 0
0 0 0 0
14
15
13
12
11
10
AB
B
A
Simplify the following Boolean function F(A,B,C,D)=∑(4,6,7,15)
D
B
A
BCD
D
C
B
A
F 

)
,
,
,
(
0 0 0 0
1 0 1 1
2
3
1
0
BCD
D
B
A

10
01 11
00
01
00
AB
CD
4 5 6
7
D
C D
C CD D
C
B
A
B
A
Example 3 on
Four-Variable K Map
8 9 10
11
1 1 1 1
0 0 0 0
14
15
13
12
11
10
AB
B
A
Simplify the following Boolean function F(A,B,C,D)=∑2,3,12,13,14,15)
C
B
A
AB
D
C
B
A
F 

)
,
,
,
(
0 0 1 1
0 0 0 0
2
3
1
0
AB
C
B
A

10
01 11
00
01
00
AB
CD
4 5 6
7
D
C D
C CD D
C
B
A
B
A
Example 4 on
Four-Variable K Map
8 9 10
11
1 1 0 1
1 1 0 0
14
15
13
12
11
10
AB
B
A
Simplify the following Boolean function F(A,B,C,D)=∑(0,1,2,4,5,6,8,9,12,13,14)
D
A
D
B
C
D
C
B
A
F 


)
,
,
,
(
1 1 0 1
1 1 0 1
2
3
1
0
C
D
A
D
B

10
01 11
00
01
00
AB
CD
4 5 6
7
D
C D
C CD D
C
B
A
B
A
Example 5 on
Four-Variable K Map
8 9 10
11
0 1 1 0
1 0 0 1
14
15
13
12
11
10
AB
B
A
Simplify the following Boolean function F(A,B,C,D)=∑(0,2,4,5,6,7,8,10,13,15)
D
B
BD
D
A
D
C
B
A
F 


)
,
,
,
(
1 0 0 1
1 1 1 1
2
3
1
0
BD
D
A
D
B
D
B
D
A
D
C
B
A
F 


)
,
,
,
(

10
01 11
00
01
00
AB
CD
4 5 6
7
D
C D
C CD D
C
B
A
B
A
Example 6 on
Four-Variable K Map
8 9 10
11
0 1 0 1
0 1 0 1
14
15
13
12
11
10
AB
B
A
Simplify the following Boolean function F(A,B,C,D)=∑(1,2,5,6,9,10,13,14)
D
C
D
C
D
C
B
A
F 

)
,
,
,
(
0 1 0 1
0 1 0 1
2
3
1
0
D
C
D
C
D
C
D
C
B
A
F 

)
,
,
,
(

Example 6 on
Four-Variable K Map
Simplify the following Boolean function F=A’B’C’+B’CD’+A’BCD’+AB’C’

Simplify the following Boolean function F(x,y)=∏ (0,3)
y
x
0 1
0
1
0
1
0
1
y y
x
x 0 1
2 3
y
x 
)
)(
(
)
,
( y
x
y
x
y
x
F 


y
x 

10
01 11
00
1
0
A
B+C
4 5 6
7
0 1 1 0
0 1 1 1
C
B  C
B  C
B  C
B 
A
A
2
3
1
0
Example 10 on
Simplify the following Boolean function F(A,B,C)= ∏(1,3,5,6,7)
C
B 
)
).(
(
)
,
,
( C
A
C
B
C
B
A
F 


C
A

10
01 11
00
01
00
A+B
C+D
4 5 6
7
D
C  D
C  D
C  D
C 
B
A
B
A
Example 8 on
Four-Variable K Map
8 9 10
11
0 0 1 1
0 0 1 1
14
15
13
12
11
10
B
A
B
A
Simplify the following Boolean function F(A,B,C,D)= ∏(0,1,4,5,10,11,14,15)
)
).(
(
)
,
,
,
( C
A
C
A
D
C
B
A
F 


1 1 0 0
1 1 0 0
2
3
1
0
C
A
C
A
10-04-2024 Dr. S. Yazhinian, AP/ CSE - Digital Electronics
61

10
01 11
00
1
0
A
BC
4 5 6
7
1 0 0 1
1 X 0 X
C
B C
B BC C
B
A
A
2
3
1
0
Example 11 on
Simplify the following Boolean function F(A,B,C)=∑m(0,2,4)+ ∑d(5,6)
A
C
C
B
A
F 
)
,
,
(
C

10
01 11
00
1
0
A
BC
4 5 6
7
1 1 X 1
1 1 X X
C
B C
B BC C
B
A
A
2
3
1
0
Example 12 on
Simplify the following Boolean function F(A,B,C)=∑m(0,1,2,4,5)+ ∑d(3,6,7)
A
1
)
,
,
( 
C
B
A
F

10
01 11
00
01
00
AB
CD
4 5 6
7
D
C D
C CD D
C
B
A
B
A
Example 9 on
Four-Variable K Map
8 9 10
11
0 1 0 1
1 0 0 X
14
15
13
12
11
10
AB
B
A
Simplify the following Boolean function F(A,B,C,D)= ∑m(0,6,8,13,14)+ ∑d(2,4,10)
D
C
AB
D
B
D
C
D
C
B
A
F 


)
,
,
,
(
1 0 0 X
X 0 0 1
2
3
1
0
D
C
AB
D
C
D
B

10
01 11
00
01
00
AB
CD
4 5 6
7
D
C D
C CD D
C
B
A
B
A
Example 10 on
Four-Variable K Map
8 9 10
11
X X 1 0
0 1 0 0
14
15
13
12
11
10
AB
B
A
Simplify the following Boolean function F(A,B,C,D)= ∑m(1,3,5,7,9,15)+ ∑d(4,6,12,13)
BD
D
C
D
A
D
C
B
A
F 


)
,
,
,
(
0 1 1 0
X 1 1 X
2
3
1
0
BD
D
A
D
C

10
01 11
00
01
00
WX
YZ
4 5 6
7
Z
Y Z
Y YZ Z
Y
X
W
X
W
Example 11 on
Four-Variable K Map
8 9 10
11
0 0 X 0
1 0 X 1
14
15
13
12
11
10
WX
X
W
Simplify the following Boolean function F(W,X,Y,Z)= ∑m(0,1,2,3,7,8,10)+ ∑d(5,6,11,15)
Z
X
Z
W
Z
Y
X
W
F 

)
,
,
,
(
1 1 1 1
0 X 1 X
2
3
1
0
Z
X
Z
W

Quine-McCluskey Method
1. Write minterms using binary values.
2. Group minterms by the number of 1’s
3. Apply adjacency (a b´ + a b = a) to each pair of terms, forming a second
list.
4. Check those terms in the first list that are covered by the new terms. Note
that only terms in adjacent groups (that differ by one 1) need be paired.
5. Repeat process with second list (and again if multiple terms are formed
on a third list).

Simplify the following Boolean function F(A,B,C,D)=∑(0,1,2,8,10,11,14,15)
using Tabulation Method
Group 1
10-04-2024 68
8421
0000
0
1
2
8
10
11
14
15
0001
0010
1000
1010
1011
1110
1111
Group 2
Group 3
Group 4
Group 5
Group 1
ABCD
000_
(0,1)
(0,2)
(0,8)
(2,10)
(8,10)
(10,11)
(10,14)
(11,15)
00_0
_000
_010
10_0
101_
1_10
1_11
Group 2
Group 3
Group 4
(14,15)111_
Group 1
ABCD
_0_0
(0,2,8,10)
(0,8,2,10)
(10,11,14,15)
(10,14,11,15)
_0_0
1_1_
1_1_
Group 2
Prime Implicants
000_
(0,1)
_0_0
(0,2,8,10)
(10,11,14,15) 1_1_
ABCD Term
A’B’C’
B’D’
AC

PRIME
IMPLICANT
NUMERIC 0 1 2 8 10 11 14 15
A’B’C’
B’D’
AC
000_
_0_0
1_1_
(0,1)
(0,2,8,10)
(10,11,14,15)
X X
X X X X
X X X X
AC
D
B
C
B
A
D
C
B
A
F 


)
,
,
,
(

Simplify the following Boolean function F(A,B,C,D)=∑(0,1,2,5,6,7,8,9,10,14) using
Tabulation Method
Group 1
8421
0000
0
1
2
8
5
6
9
7
0001
0010
1000
0101
0110
1001
0111
Group 2
Group 3
Group 4
Group 1
ABCD
000_
(0,1)
(0,2)
(0,8)
(1,5)
(1,9)
(5,7)
(6,7)
(6,14)
00_0
_000
0_01
_001
01_1
011_
_110
Group 2
Group 3
(10,14) 1_10
Group 1
ABCD
_00_
(0,1,8,9)
(0,8,2,10)
(2,6,10,14)
(2,10,6,14)
_0_0
_ _10
_ _10
Group 2
8421
0000
0
1
2
5
6
7
9
10
0001
0010
0101
0110
0111
1001
1010
14
8 1000
1110
10 1010
14 1110
(2,6)
(8,9)
0_10
100_
(2,10)
(8,10)
_010
10_0
_0_0
(0,2,8,10)
_00_
(0,8,1,9)

Prime Implicants
(1,5)
(5,7)
(2,6,10,14)
ABCD Term
A’C’D
A’BD
CD’
(6,7)
(0,1,8,9)
(0,2,8,10)
A’BC
B’C’
B’D’
0_01
01_1
011_
_0_0
_ _10
_00_

PRIME
IMPLICANT
NUMERIC 0 1 2 5 6 7 8 9 10 14
X X
X X
X X
X X X X
D
C
C
B
BD
A
D
C
B
A
F 


)
,
,
,
(
A’C’D
A’BD
CD’
A’BC
B’C’
B’D’
0_01
01_1
011_
_0_0
_ _10
_00_
(1,5)
(5,7)
(2,6,10,14)
(6,7)
(0,1,8,9)
(0,2,8,10) X X X
X
X X X X

Combinational Circuit

• Logic circuits for digital systems may be combinational or
sequential.
• A combinational circuit consists of input variables, logic
gates, and output variables.
74

Half Adder
• A combinational circuit that performs the addition of two bits is
called a half adder.
• The truth table for the half adder is
S = x’y + xy’
C = xy
75
S: Sum
C: Carry
10-04-2024
0 0
0 1
1 0
1 1
0 0
0 1
0 1
1 0
x y C S
1
0
1
0
x
y
2 3
0 0
0 1
y y
x
x
1
0
1
0
1
0
x
y
2 3
0 1
1 0
y y
x
x
1
0
xy
C: Carry
S: Sum
y
x
y
x

Implementation of Half-Adder
76
S = x’y + xy’  x⊕ y
C = xy
xy = c
x’y + xy’ = s

Full Adder
• A combinational circuit that performs the addition of three bits is
called a full adder.
• The truth table for the full adder is
77
S: Sum
C: Carry
x y S C
10
01 11
00
1
0
x
yz
4 5 6
7
m0 m1 m3
m2
m4 m5 m7 m6
z
y z
y yz z
y
x
x
2
3
1
0
10
01 11
00
1
0
x
yz
4 5 6
7
m0 m1 m3
m2
m4 m5 m7 m6
z
y z
y yz z
y
x
x
2
3
1
0

Full-Adder
• One that performs the addition of three bits(two
significant bits and a previous carry) is a full adder.
78

Simplified Expressions
S = x’y’z + x’yz’ + xy’z’ + xyz
C = xy + xz + yz
79

Full Adder implementation
• Full-adder can also implemented with two half adders and
one OR gate (Carry Look-Ahead adder).
S = z ⊕ (x ⊕ y)
= z’(xy’ + x’y) + z(xy’ + x’y)’
= xy’z’ + x’yz’ + xyz + x’y’z
C = z(xy’ + x’y) + xy = xy’z + x’yz + xy
80

Binary adder
• This is also called
Ripple Carry
Adder ,because of the
construction with full
adders are connected
in cascade.
81

Binary subtractor
M = 1subtractor ; M = 0adder
82

Overflow
• It is worth noting that binary numbers in the signed-complement
system are added and subtracted by the same basic addition and
subtraction rules as unsigned numbers.
• Overflow is a problem in digital computers because the number of
bits that hold the number is finite and a result that contains n+1
bits cannot be accommodated.
83

Overflow on signed and unsigned
• When two unsigned numbers are added, an overflow is detected
from the end carry out of the MSB position.
• When two signed numbers are added, the sign bit is treated as
part of the number and the end carry does not indicate an
overflow.
• An overflow can’t occur after an addition if one number is positive
and the other is negative.
• An overflow may occur if the two numbers added are both positive
or both negative.
84

BCD adder
BCD adder can’t exceed 9 on each input digit. K is the carry.
85

Rules of BCD adder
• When the binary sum is greater than 1001, we obtain a non-valid
BCD representation.
• The addition of binary 6(0110) to the binary sum converts it to the
correct BCD representation and also produces an output carry as
required.
• To distinguish them from binary 1000 and 1001, which also have a
1 in position Z8, we specify further that either Z4 or Z2 must have a
1.
C = K + Z8Z4 + Z8Z2
86

Implementation of BCD adder
• A decimal parallel
adder that adds n
decimal digits needs n
BCD adder stages.
• The output carry from
one stage must be
connected to the input
carry of the next
higher-order stage.
87
If =1
0110

Binary multiplier
• Usually there are more bits in the partial products and it is necessary to use full
adders to produce the sum of the partial products.
88
And

Magnitude comparator
• The equality relation of each pair
of bits can be expressed logically
with an exclusive-NOR function as:
A = A3A2A1A0 ; B = B3B2B1B0
xi=AiBi+Ai’Bi’ for i = 0, 1, 2, 3
(A = B) = x3x2x1x0
89

Magnitude comparator
• We inspect the relative magnitudes
of pairs of MSB. If equal, we
compare the next lower significant
pair of digits until a pair of unequal
digits is reached.
• If the corresponding digit of A is 1
and that of B is 0, we conclude that
A>B.
(A>B)=
A3B’3+x3A2B’2+x3x2A1B’1+x3x2x1A0B’0
(A<B)=
A’3B3+x3A’2B2+x3x2A’1B1+x3x2x1A’0B0
90

Decoders
• The decoder is called n-to-m-line decoder, where m≤2n
.
• the decoder is also used in conjunction with other code converters
such as a BCD-to-seven_segment decoder.
• 3-to-8 line decoder: For each possible input combination, there are
seven outputs that are equal to 0 and only one that is equal to 1.
91

Implementation and truth table
92

Decoder with enable input
• Some decoders are constructed with NAND gates, it becomes more
economical to generate the decoder minterms in their
complemented form.
• As indicated by the truth table , only one output can be equal to 0
at any given time, all other outputs are equal to 1.
93

Demultiplexer
• A decoder with an enable input is referred to as a
decoder/demultiplexer.
• The truth table of demultiplexer is the same with decoder.
94
Demultiplexer
D0
D1
D2
D3
E
A B

Encoders
• An encoder is the inverse operation of a decoder.
• We can derive the Boolean functions by table
z = D1 + D3 + D5 + D7
y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7
95

Priority encoder
• If two inputs are active simultaneously, the output produces an undefined
combination. We can establish an input priority to ensure that only one input is
encoded.
• Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is
generated when all the inputs are 0; the output is the same as when D0 is equal
to 1.
• The discrepancy tables can resolve aforesaid condition by providing one more
output to indicate that at least one input is equal to 1.
96

Priority encoder
V=0no valid inputs
V=1valid inputs
X’s in output columns represent
don’t-care conditions
X’s in the input columns are
useful for representing a truth
table in condensed form.
Instead of listing all 16
minterms of four variables.
97

4-input priority encoder
• Implementation of
table
x = D2 + D3
y = D3 + D1D’2
V = D0 + D1 + D2 + D3
98
0
0
0
0

Multiplexers
S = 0, Y = I0 Truth Table S Y Y = S’I0 + SI1
S = 1, Y = I1 0 I0
1 I1
99

4-to-1 Line Multiplexer
100

Boolean function implementation
• A more efficient method for implementing a Boolean function of n
variables with a multiplexer that has n-1 selection inputs.
F(x, y, z) = (1,2,6,7)
101

4-input function with a multiplexer
F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)
102

Code Conversion
Code-Conversion example, first, we can list the relation of
the BCD and Excess-3 codes in the truth table.
103

Karnaugh map
For each symbol of the Excess-3 code, we use 1’s to draw
the map for simplifying Boolean function.
104

Circuit implementation
z = D’; y = CD + C’D’ = CD + (C + D)’
x = B’C + B’D + BC’D’ = B’(C + D) + B(C + D)’
w = A + BC + BD = A + B(C + D)
105

Thank You

Unit-I digital electronics .

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