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High Channel Count DAQ Presesentation
- 2. High Channel Count to a Single Channel,a Scalable PXI Based Dynamic Signal Acquisition System 2009 NI Week – August 4th Doug Wilson Stephen Masullo PVI Systems, Inc.
- 3. System Overview Single or Multiple Chassis w/Controller GPS Synchronization Transducers Excitation Devices Host Computer GigE Switch
- 4. Development Overview Scalable Data Acquisition System Designed for a Government Lab Advanced DAQmx Help from NI S&V Support Group Design Goals Flexible Data Acquisition Engine Scalable Reconfigurable to Support Multiple Test Programs Geographically distributed
- 5. Functional Capabilities Channel Configuration Management Hardware Setup and Control Data Quality Checking Data Monitoring Data Streaming Frequency Processing Data File Management Automated Acquisition
- 6. NI Hardware – PXI or PXIe Chassis with Controller Embedded Or External Timing Card(s) Data Acquisition Modules
- 7. Timing Synchronization Options Master/Slave Configuration All Master Configuration Slave #2 External Clock GPS GPS Master Slave #1
- 8. High Channel Count Expansion Options Master/Slave Expansion Master Slave #3 Slave #2 Slave #1 Chassis #1 Chassis#2 Chassis #3 Chassis #4 Slave #6 Slave #7 Slave #4 Slave #5 Slave #8 Slave #9 All Master Expansion GPS GPS GPS GPS GPS Chassis #N
- 9. Software Flow Diagram Host Side Server Side Channel Config Utility TCP Messaging Host Main Data Plotting Data Export Data File Download Acquisition Control Server Main Source Control Acquisition Hardware Data Streaming Data Monitoring
- 10. Acquisition Control Initialization NI-Sync Timing DAQmx Init Trigger Init Sync Pulse Init (on Master Chassis only) Connect Start Trigger
- 11. Acquisition Control - Acquisition Acquisition Loop DAQmx Read Write to Circular Buffer Write to TDMS (if logging) AI Start Data Monitor Loop Init Circ Buffer Start DAQmx Tasks Issue Start Pulse Circular Buffer -> RMS -> Peak ->Host -> Waveform
- 12. Data Formats Time Data – TDMS File on Each Server Configuration for All Servers Scaling Coefficients Raw Data Recorded Errors Frequency Data – TDMS File on Host Configuration for All Servers Selected Frequency Data (PS, PSD, FRF) Recorded Errors
- 15. Source Control
- 17. Signal Monitor
- 18. File Functions
- 19. Data Plotting and Freq Processing
- 20. Download / Merge Data Files
- 21. File Export
- 22. File Configuration and Error Display
- 24. View Time of Master Chassis
- 26. Source Control Output Waveform Output Amplitude Master Per Channel Sine Output Frequency Coordinated Digital Triggering with Analog Output
- 27. Acquisition Control Data File Path Acquisition Mode Continuous Finite Frequency
- 28. Signal Monitoring Bar Graph Indicator Max RMS Instantaneous Peak Range Setting Per Channel Auto Range All Chan Per Channel Time or Frequency Display Multi-Plot Error Indicators
- 31. Frequency Data Display and Processing Playback with Frequency Processing Selectable Parameters
- 32. Automated Acquisition Control Programmatic Control - Active-X Update Front Panel Controls Generate Events Control entire experiment multiple acquisition & source setups
- 33. Future Development Expanded Range of Validated NI Hardware Enhanced User Interface Integrated Post Processing Tools Interface to Third Party Post Processing Tools
- 34. System Demonstration Demonstrates Multiple PXI Chassis Configuration Live Linear Acoustic Array Data Streaming Live Processing See the live demo at PVI Systems Booth # 433
Editor's Notes
- This example is for free run triggering and internal master clock source. Most of this was written by Jack Arnold. After TCP communication is established between host and server(s), the host sends the server the channel/acquisition information, and then issues a command to initialize. The initialization process involves creating an NISync session, on the master the internal oscillator is routed to Clk10 which is routed to Clkout (for connection to server(s)), Trig0 is pull high and connected to Trig1, PFI1, PFI2, and Trig5 for sending the sync and trigger pulses. Next, the DAQmx tasks are created, voltage channels are created, channel parameters are established (range, coupling, IEPE, etc), and the sample clock source is defined.Current time is read from the master chassis and sent back to the host, the host determines a future time to issue a sync pulse and sends that time to the master chassis which issues the pulse at that time. (Trig5 to Sync Source, Clk10 to Ref Clock ?) Init and connect start trigger by connecting Trig1 to Trig4 (start trigger) and pulling Trig0 low. On the slave, PFI0 is connect to Trig4 (Start trigger). This ends initialization. At this point the server sits in an idle state waiting for the next command.