SPICE MODEL of TC74ACT540F in SPICE PARK
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SPICE MODEL of TC74ACT540F in SPICE PARK. English Version is http://www.spicepark.net. Japanese Version is http://www.spicepark.com by Bee Technologies.
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SPICE MODEL of TC74ACT540F in SPICE PARK
- 1. Device Modeling Report COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT PART NUMBER : TC74ACT540F MANUFACTURER : TOSHIBA Bee Technologies Inc. All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 2. Truth Table Circuit simulation result U1:G1BAR U1:G2BAR U1:A1 U1:A2 U1:A3 U1:A4 U1:A5 U1:A6 U1:A7 U1:A8 U1:Y1 U1:Y2 U1:Y3 U1:Y4 U1:Y5 U1:Y6 U1:Y7 U1:Y8 0s 0.5us 1.0us Time Evaluation circuit _ U1 HI G1 VCC _ CLK A1 G2 CLK _ DSTM1 A2 Y1 DSTM2 Y1 ONTIME = .2uS _ ONTIME = .2uS OFFTIME = .2uS A3 Y2 OFFTIME = .2uS Y2 _ A4 Y3 Y3 _ A5 Y4 Y4 V1 _ R4 A6 Y5 5 Y5 1MEG _ A7 Y6 Y6 _ A8 Y7 Y7 _ GND Y8 Y8 74ACT540 0 Comparison table Input Output %Error G1 G2 An Yn (Measurement) Yn (Simulation) H X X Z Z 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 3. Truth Table Circuit simulation result U1:G1BAR U1:G2BAR U1:A1 U1:A2 U1:A3 U1:A4 U1:A5 U1:A6 U1:A7 U1:A8 U1:Y1 U1:Y2 U1:Y3 U1:Y4 U1:Y5 U1:Y6 U1:Y7 U1:Y8 0s 0.5us 1.0us Time Evaluation circuit _ U1 CLK G1 VCC _ DSTM1 A1 G2 HI ONTIME = .2uS _ OFFTIME = .2uS A2 Y1 Y1 _ A3 Y2 Y2 _ A4 Y3 Y3 _ A5 Y4 Y4 V1 _ R4 A6 Y5 5 Y5 1MEG _ A7 Y6 Y6 _ A8 Y7 Y7 _ GND Y8 Y8 74ACT540 0 Comparison table Input Output %Error G1 G2 An Yn (Measurement) Yn (Simulation) X H X Z Z 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 4. Truth Table Circuit simulation result U1:G1BAR 0 U1:G2BAR 0 U1:A1 1 U1:A2 1 U1:A3 1 U1:A4 1 U1:A5 1 U1:A6 1 U1:A7 1 U1:A8 1 U1:Y1 0 U1:Y2 0 U1:Y3 0 U1:Y4 0 U1:Y5 0 U1:Y6 0 U1:Y7 0 U1:Y8 0 0s 0.5us 1.0us Time Evaluation circuit _ U1 LO G1 VCC _ HI A1 G2 LO _ HI A2 Y1 Y1 _ HI A3 Y2 Y2 _ HI A4 Y3 Y3 _ HI A5 Y4 Y4 V1 _ HI A6 Y5 R4 5 Y5 _ A7 Y6 1MEG HI Y6 _ HI A8 Y7 Y7 _ GND Y8 Y8 74ACT540 0 Comparison table Input Output %Error G1 G2 An Yn (Measurement) Yn (Simulation) L L H L L 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 5. Truth Table Circuit simulation result U1:G1BAR 0 U1:G2BAR 0 U1:A1 0 U1:A2 0 U1:A3 0 U1:A4 0 U1:A5 0 U1:A6 0 U1:A7 0 U1:A8 0 U1:Y1 1 U1:Y2 1 U1:Y3 1 U1:Y4 1 U1:Y5 1 U1:Y6 1 U1:Y7 1 U1:Y8 1 0s 0.5us 1.0us Time Evaluation circuit _ U1 LO G1 VCC _ A1 G2 LO LO _ A2 Y1 LO Y1 _ A3 Y2 LO Y2 _ A4 Y3 LO Y3 _ A5 Y4 LO Y4 V2 _ A6 Y5 R4 5 LO Y5 _ A7 Y6 1MEG LO Y6 _ A8 Y7 LO Y7 _ GND Y8 Y8 74ACT540 0 Comparison table Input Output %Error G1 G2 An Yn (Measurement) Yn (Simulation) L L L H H 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 6. High Level and Low Level Input Voltage Circuit simulation result 5.0V Output 2.5V (540.004u,2.0002) Input (515.984u,799.190m) 0V 0s 0.5ms 1.0ms 1.5ms 2.0ms V(Y1) V(V1:+) Time Evaluation circuit _ U1 LO G1 VCC _ A1 G2 LO _ A2 Y1 Y1 _ A3 Y2 _ A4 Y3 V2 V1 = 0 _ V2 = 5 V1 A5 Y4 TD = 0.5m _ R2 TR = 0.1m A6 Y5 5 TF = 0.1m 1G _ PW = 1m A7 Y6 PER = 2m _ A8 Y7 _ GND Y8 74ACT540 0 Comparison table VCC = 5V Measurement Simulation %Error VIH (V) 2 2.0002 0.010 VIL (V) 0.8 0.79919 -0.101 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 7. High Level and Low Level Output Voltage Circuit simulation result 5.0V 2.5V SEL>> Output 0V V(Y1) Input 5.0V 2.5V 0V 0s 5ms 10ms V(V1:+) Time Evaluation circuit _ U1 LO G1 VCC _ A1 G2 LO _ A2 Y1 Y1 _ A3 Y2 _ A4 Y3 V2 V1 = 0 _ V2 = 4.5 V1 A5 Y4 TD = 0.5m _ R1 TR = 3n A6 Y5 4.5 TF = 3n 0.09MEG _ PW = 1m A7 Y6 PER = 2m _ A8 Y7 _ GND Y8 74ACT540 0 Comparison table VCC = 4.5V Measurement Simulation %Error VOH (V) 4.5 4.4988 -0.027 VOL (V) 0 0 0 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 8. Propagation Delay Time Circuit simulation result 5.0V 3.0V 1 2 2.0V Output 2.5V Input 1.0V >> 0V 0V 0s 0.5us 1.0us 1 V(TPLH_TPHL) 2 V(U1:A1) Time Evaluation circuit _ U1 LO G1 VCC _ A1 G2 LO _ TPLH_TPHL A2 Y1 _ A3 Y2 _ A4 Y3 _ A5 Y4 V1 = 0 _ V2 V2 = 3 A6 Y5 R1 TD = 0.2u V1 _ C1 TR = 3.8n A7 Y6 50p 500 5 TF = 3.8n _ PW = 0.5u A8 Y7 PER = 1u _ GND Y8 74ACT540 0 Comparison table CL = 50 pF, RL = 500 tr = tf = 3 ns Measurement Simulation %Error tpLH (ns) 5 5.0210 0.420 tpHL (ns) 5 5.03 0.600 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 9. Output enable time, high impedance (off) to high output (tPZH) Output disable time, high to high impedance (off) output (tPHZ) Circuit simulation result 5.0V 3.0V 1 2 Output Input 2.0V 2.5V 1.0V >> 0V 0V 0s 0.5us 1.0us 1 V(TPHZ_TPZH) 2 V(V1:+) Time Evaluation circuit _ U1 G1 VCC _ A1 G2 LO _ tphz_tpzh A2 Y1 _ A3 Y2 _ A4 Y3 _ A5 Y4 _ V2 V1 = 0 V1 A6 Y5 C1 R1 R2 V2 = 3 _ 50p TD = 0.2u A7 Y6 500 500 TR = 3.8n _ 5 TF = 3.8n A8 Y7 PW = 0.5u _ PER = 1u GND Y8 74ACT540 0 Comparison table CL = 50 pF, RL = 500 tr = tf = 3 ns Measurement Simulation %Error tPHZ (ns) 5.9 5.9843 1.429 tpZH (ns) 7.3 7.3133 0.182 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005
- 10. Output enable time, high impedance (off) to low output (tPZL) Output disable time, low to high impedance (off) output (tPLZ) Circuit simulation result 5.0V 3.0V 1 2 Output Input 2.0V 2.5V 1.0V >> 0V 0V 0s 0.5us 1.0us 1 V(TPLZ_TPZL) 2 V(V1:+) Time Evaluation circuit _ U1 G1 VCC _ HI A1 G2 _ tplz_tpzl R2 A2 Y1 _ 500 A3 Y2 _ A4 Y3 _ A5 Y4 V3 V1 = 0 V1 _ V2 V2 = 3 A6 Y5 C1 R1 TD = 0.2u _ TR = 3.8n A7 Y6 50p 500 TF = 3.8n _ 10 5 PW = 0.5u A8 Y7 PER = 1u _ GND Y8 74ACT540 0 Comparison table CL = 50 pF, RL = 500 tr = tf = 3 ns Measurement Simulation %Error tPLZ (ns) 5.9 5.9705 1.195 tpZL (ns) 7.3 7.3961 1.316 All Rights Reserved Copyright (c) Bee Technologies Inc. 2005