The document is a device modeling report for the CMOS digital integrated circuit TC74LCX541FW, manufactured by Toshiba Bee Technologies Inc. It includes truth tables, circuit simulation results, and performance comparisons related to input/output characteristics, propagation delay, and output enable/disable times. The report provides detailed measurements and simulations, highlighting errors in output and timing under various conditions.

1. Device Modeling Report
COMPONENTS : CMOS DIGITAL INTEGRATED CIRCUIT
PART NUMBER : TC74LCX541FW
MANUFACTURER : TOSHIBA
Bee Technologies Inc.
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

2. Truth Table
Circuit simulation result
1:OE1BAR 1
1:OE2BAR 0
U1:A1 0
U1:A2 0
U1:A3 0
U1:A4 0
U1:A5 0
U1:A6 0
U1:A7 0
U1:A8 0
Y1 Z
Y2 Z
Y3 Z
Y4 Z
Y5 Z
Y6 Z
Y7 Z
Y8 Z
0s 0.5us 1.0us
Time
Evaluation circuit
___ U1
HI OE1 VCC
___
CLK A1 OE2 CLK
DSTM1 A2 Y1 DSTM2
Y1
ONTIME = .2uS ONTIME = .2uS
OFFTIME = .2uS A3 Y2 OFFTIME = .2uS
Y2
A4 Y3
Y3
A5 Y4
Y4 V1
R4
A6 Y5
Y5 1MEG
A7 Y6 3
Y6
A8 Y7
Y7
GND Y8
Y8
74LCX541
0
Comparison table
Input Output
%Error
OE1 OE2 An Yn (Measurement) Yn (Simulation)
H X X Z Z 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

3. Truth Table
Circuit simulation result
1:OE1BAR 0
1:OE2BAR 1
U1:A1 0
U1:A2 0
U1:A3 0
U1:A4 0
U1:A5 0
U1:A6 0
U1:A7 0
U1:A8 0
Y1 Z
Y2 Z
Y3 Z
Y4 Z
Y5 Z
Y6 Z
Y7 Z
Y8 Z
0s 0.5us 1.0us
Time
Evaluation circuit
___ U1
CLK OE1 VCC
___
DSTM1 A1 OE2 HI
ONTIME = .2uS
OFFTIME = .2uS A2 Y1
Y1
A3 Y2
Y2
A4 Y3
Y3
A5 Y4
Y4 V1
R4
A6 Y5 3
Y5 1MEG
A7 Y6
Y6
A8 Y7
Y7
GND Y8
Y8
74LCX541
0
Comparison table
Input Output
%Error
OE1 OE2 An Yn (Measurement) Yn (Simulation)
X H X Z Z 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

4. Truth Table
Circuit simulation result
1:OE1BAR 0
1:OE2BAR 0
U1:A1 1
U1:A2 1
U1:A3 1
U1:A4 1
U1:A5 1
U1:A6 1
U1:A7 1
U1:A8 1
Y1 1
Y2 1
Y3 1
Y4 1
Y5 1
Y6 1
Y7 1
Y8 1
0s 0.5us 1.0us
Time
Evaluation circuit
___ U1
LO
OE1 VCC
___
HI
A1 OE2 LO
HI A2 Y1
Y1
HI A3 Y2
Y2
HI A4 Y3
Y3
HI A5 Y4
Y4 V1
HI A6 Y5 R4 3
Y5
A7 Y6 1MEG
HI Y6
HI A8 Y7
Y7
GND Y8
Y8
74LCX541
0
Comparison table
Input Output
%Error
OE1 OE2 An Yn (Measurement) Yn (Simulation)
L L H H H 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

5. Truth Table
Circuit simulation result
1:OE1BAR 0
1:OE2BAR 0
U1:A1 0
U1:A2 0
U1:A3 0
U1:A4 0
U1:A5 0
U1:A6 0
U1:A7 0
U1:A8 0
U1:Y1 0
U1:Y2 0
U1:Y3 0
U1:Y4 0
U1:Y5 0
U1:Y6 0
U1:Y7 0
U1:Y8 0
0s 0.5us 1.0us
Time
Evaluation circuit
___ U1
LO
OE1 VCC
___
A1 OE2
LO LO
A2 Y1
LO Y1
A3 Y2
LO Y2
A4 Y3
LO Y3
A5 Y4
LO Y4 V2
A6 Y5 R4 3
LO Y5
A7 Y6 1MEG
LO Y6
A8 Y7
LO Y7
GND Y8
Y8
74LCX541
0
Comparison table
Input Output
%Error
OE1 OE2 An Yn (Measurement) Yn (Simulation)
L L L L L 0
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

6. High Level and Low Level Input Voltage
Circuit simulation result
3.0V
2.0V
Output
Input
1.0V
0V
0s 0.5ms 1.0ms 1.5ms 2.0ms
V(Y1) V(V1:+)
Time
Evaluation circuit
___ U1
LO
OE1 VCC
___
A1 OE2 LO
A2 Y1
Y1
A3 Y2
A4 Y3 V2
V1 = 0
V2 = 3 V1 A5 Y4
TD = 0.5m R2
TR = 0.1m A6 Y5 3
TF = 0.1m 1G
PW = 1m A7 Y6
PER = 2m
A8 Y7
GND Y8
74LCX541
0
Comparison table
VCC = 3V Measurement Simulation %Error
VIH (V) 2 2 0
VIL (V) 0.8 0.799173 -0.103
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

7. High Level Output Voltage
Circuit simulation result
3.0V
2.0V
Output
1.0V
0V
0s 2ms 4ms 6ms 8ms 10ms
V(Y1)
Time
Evaluation circuit
___ U1
LO
OE1 VCC
___
A1 OE2 LO
A2 Y1
Y1
A3 Y2
A4 Y3 V2
V1
A5 Y4
2.1 I1
A6 Y5 3
-100u
A7 Y6
A8 Y7
GND Y8
74LCX541
0
Comparison table
VIN = VIH, VCC = 3 V Measurement Simulation %Error
Min VOH = (VCC - 0.2) V 2.8 2.8340 1.214
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

8. Low Level Output Voltage
Circuit simulation result
3.0V
2.0V
Output
1.0V
0V
0s 2ms 4ms 6ms 8ms 10ms
V(Y1)
Time
Evaluation circuit
___ U1
LO
OE1 VCC
___
A1 OE2 LO
A2 Y1
Y1
A3 Y2
A4 Y3 V2
V1
A5 Y4
0.7 I1
A6 Y5 3
100u
A7 Y6
A8 Y7
GND Y8
74LCX541
0
Comparison table
VIN = VIL, VCC = 3 V Measurement Simulation %Error
VOL (V) 0.2 0.191208 -4.396
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

9. Propagation Delay Time
Circuit simulation result
3.0V
2.0V
Output
Input
1.0V
0V
0s 0.5us 1.0us
V(TPLH_TPHL) V(U1:A1)
Time
Evaluation circuit
___ U1
LO
OE1 VCC
___
A1 OE2 LO
TPLH_TPHL
A2 Y1
A3 Y2
A4 Y3
A5 Y4
V1 = 0 V2
V2 = 2.7 A6 Y5 R1
TD = 0.2u V1 C1
TR = 3.15n A7 Y6 50p 500 2.7
TF = 3.15n
PW = 0.5u A8 Y7
PER = 1u
GND Y8
74LCX541
0
Comparison table CL = 50 pF, RL = 500 
VCC = 2.7 V, tr=tf= 2.5 ns Measurement Simulation %Error
tpLH (ns) 7.5 7.4215 -1.047
tpHL (ns) 7.5 7.4696 -0.405
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

10. Output enable time, high impedance (off) to high output (tPZH)
Output disable time, high to high impedance (off) output (tPHZ)
Circuit simulation result
3.0V
Output
Input
2.0V
1.0V
0V
0s 0.5us 1.0us
V(TPHZ_TPZH) V(V1:+)
Time
Evaluation circuit
___ U1
OE1 VCC
___
HI
A1 OE2
tphz_tpzh
A2 Y1
A3 Y2
A4 Y3
A5 Y4
V2
V1 = 0 V1 A6 Y5 C1 R1 R2
V2 = 2.7 50p
TD = 0.2u A7 Y6 500 500
TR = 3.15n 2.7
TF = 3.15n A8 Y7
PW = 0.5u
PER = 1u GND Y8
74LCX541
0
Comparison table CL = 50 pF, RL = 500 
VCC = 2.7 V, tr=tf= 2.5 ns Measurement Simulation %Error
tPHZ (ns) 8.5 8.3687 -1.545
tpZH (ns) 9.5 9.4711 -0.304
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005

11. Output enable time, high impedance (off) to low output (tPZL)
Output disable time, low to high impedance (off) output (tPLZ)
Circuit simulation result
3.0V
Output
Input
2.0V
1.0V
0V
0s 0.5us 1.0us
V(TPLZ_TPZL) V(V1:+)
Time
Evaluation circuit
___ U1
OE1 VCC
___
A1 OE2
LO
tplz_tpzl R2
A2 Y1
500
A3 Y2
A4 Y3
A5 Y4 V3
V1 = 0 V1 V2
V2 = 2.7 A6 Y5 C1 R1
TD = 0.2u
TR = 3.15n A7 Y6 50p 500
TF = 3.15n 6 2.7
PW = 0.5u A8 Y7
PER = 1u
GND Y8
74LCX541
0
Comparison table CL = 50 pF, RL = 500 
VCC = 2.7 V, tr=tf= 2.5 ns Measurement Simulation %Error
tPLZ (ns) 8.5 8.4395 -0.712
tpZL (ns) 9.5 9.583 0.874
All Rights Reserved Copyright (c) Bee Technologies Inc. 2005