The document describes two job positions at an engineering company.
Position 1 is for a Design Verification Engineer requiring a degree in computer, electrical, or electronic engineering plus 5+ years of industry experience verifying ASIC designs using SystemVerilog and OVM/UVM methodologies. Strong skills in testbench development, debugging, and understanding of bus protocols are needed.
Position 2 is for a Physical Design Engineer requiring a similar degree and experience implementing physical designs including floorplanning, placement, routing, and verification for cores like graphics and video processors. Experience with STA tools, timing closure, power analysis, and formal verification is required.
1. Position 1---Job Title Design Verification Engineer
Department/Job Area: Engineering-Hardware
Experience Level: >5 Years
Work Location: San Diego, CA and Bay Area, CA
Job description
Bachelor/Master’s in Computer Engineering and/or Electrical / Electronic Engineering with 5+
years of industry experience in ASIC design and verification
Experience in verifying designs at system level and block level using constrained random
verification. - Expert in System Verilog and OVM/UVM based verification. - Strong experience
in ASIC design verification flows and DV methodologies.
Expert in coding SV Test bench, drivers, monitors, scoreboards, checkers - Strong and
independent design debugging capability.
Understanding of AHB, AXI and other bus protocols, digital design and system architecture
Highly motivated and be able to work both independently and as a member of team.
Strong verbal and written communication skills
Position 2: ---Job Details: Job Title Physical Design Engineer
Department/Job Area: Engineering-Hardware
Experience Level: >5 Years
Work Location: San Diego, CA and Bay Area, CA
Job description:
Bachelor/Master’s in Computer Engineering and/or Electrical / Electronic Engineering with 5+
years of industry experience in the following technical areas:
Complete Physical Implementation of cores i.e. graphics, video, multimedia, processor, DDR. •
Core and Top level Floor planning, Placement, Clock Tree Synthesis, Place & Route, Physical
Verification, and Signal Integrity Analysis.
Low-power implementation methods and develop high speed customized logic cells -
Physical design implementation (Floor planning, CTS, STA) for CPUs and GPUs in advanced
technologies.
STA tool and timing closure methodologies - Power grid, clock tree, and low-power
reduction implementation methods
Signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing
Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification
Programming and scripting skills (Tcl, perl and/or C)
Strong verbal and written communication skills