Sparc64 vii+ on the m4000 to m9000

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SPARC64 VII+ on the M4000 to M9000
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The following is intended to outline our general
product direction. It is intended for information
purposes only, and may not be incorporated into
any contract. It is not a commitment to deliver
any material, code, or functionality, and should
not be relied upon in making purchasing
decisions.
The development, release, and timing of any
features or functionality described for Oracle’s
products remains at the sole discretion of
Oracle.

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Product Overview
• Oracle is announcing enhancements to the SPARC
Enterprise M-Series family of servers
• A new processor upgrade, the SPARC64 VII+, will be
available starting in December and rolling out in 2011
– Offers customers another system upgrade, preserving
investment protection in existing M-Series frames
– Improves performance over prior generation CPUs
while continuing commitment to mission-critical
reliability

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Sun Systems for Oracle
Over 20 Years of Joint Mission Critical Deployments
Enterprise class platforms
• Reliability, availability, serviceability,
and security
• Highly scalable (Vertical, Horizontal)
• Flash optimized for business critical
database performance acceleration
M3000
M4000
M5000
M8000
M9000

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SPARC Solaris Industry Leadership
SPARC M-Series Upgrade delivers:
• Processor upgrade for the M4000 to M9000
• 5th
processor upgrade for the M-Series
­ Clear ROI advantage over IBM and HP
• 10-30% performance improvement
• 2X L2 Cache for improved memory access
• Database optimized for performance and reliability
• Leading investment protection
– Seamless upgrade path from prior generations
– Built-in application and binary compatibility

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Mixed Processor Generations
A Key ROI Advantage
• Only the M-Series is able to mix up to 5 different CPU
speeds from 3 different generations
• Mix up to 3 different L2 cache sizes
• No change required for applications. Solaris handles
everything.
M4000/M5000 M8000/M9000
Generation 1:
SPARC64 VI at 2.15 GHz with 5 MB of L2$
Generation 1:
SPARC64 VI at 2.28 GHz with 5 MB of L2$
SPARC64 VI at 2.4 GHz with 6 MB of L2$
Generation 2:
SPARC64 VII at 2.4 GHz with 5 MB of L2$
SPARC64 VII at 2.53 GHz with 5.5 MB of L2$
Generation 2:
SPARC64 VII at 2.52 GHz with 6 MB of L2$
SPARC64 VII at 2.88 GHz with 6 MB of L2$
Generation 3:
SPARC64 VII+ at 2.66 GHz with 11 MB of L2$
Generation 3:
SPARC64 VII+ at 3.0 GHz with 12 MB of L2$

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C1 C2
Arbiter / Switch
System
Interface
System Interconnect
128KB
D$
128KB I$
FPU
128KB
D$
128KB I$
FPU
5-6MB L2$
5B @ 530Mhz
1st Generation: SPARC64 VI
• Available on M4000-M9000
• Two SPARC V9 cores @ 2.15 – 2.4 GHz
> Exports sun4u architecture to Solaris
> Two vertical threads per core
> 128KB I$ and 128KB D$ per core
> 5-6MB on-chip shared L2$
• Switch strands on events: Vertical Multi Threading
• Implements combination of CMP and VMT
• New system chipset/interconnect (Jupiter bus)
> Scalable to 64 sockets
• Technology: Fujitsu 90nm
• Power: 110W @ 1.1v & 2.15 - 2.4 GHz
• Can be mixed with other SPARC64 CPUs

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64KB D$
64KB I$
FPU
C1
FPU
C2
Arbiter / Switch
System Interconnect
5-6MB L2$
5B @ 530Mhz
FPU
C3
FPU
C4
System
Interface
64KB D$
64KB I$
64KB D$
64KB I$
64KB D$
64KB I$
2nd Generation: SPARC64 VII (i.e. Jupiter)
• Available on M3000-M9000
• Four SPARC V9 cores @ 2.4-2.52GHz
> Exports sun4u architecture to Solaris
> Improved threading model, 2 SMT threads per
core
> 64KB I$ and 64KB D$ per core
> Large on-chip shared 5-6MB L2$
• Same system chipset/interconnect
• SPARC v9 compliant design; Binary
compatible to S10 applications
> S10U4 minimum OS level required
> XCP1070 or greater on XSCF
• Technology: Fujitsu 65nm
• Power: ~120W @1.1v & 2.52GHz
• Can be mixed with other SPARC64 CPUs

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64KB D$
64KB I$
FPU
C1
FPU
C2
Arbiter / Switch
System Interconnect
5.5/6MB L2$
5B @ 530Mhz
FPU
C3
FPU
C4
System
Interface
64KB D$
64KB I$
64KB D$
64KB I$
64KB D$
64KB I$
2nd Generation: SPARC64 VII (i.e. Jupiter+)
• Available on M3000-M9000
• Four SPARC V9 cores @ 2.53-2.88GHz
> Same thread model as Jupiter
> Large on-chip shared 5.5MB or 6MB L2$
• Same system chipset/interconnect
• S10U4 + MU8 minimum OS level required
> XCP1090 or greater on XSCF
• Power: ~135W @1.1v & 2.88GHz
• Can be mixed with existing SPARC64
processors
> Can mix SPARC64 VI, VII in the same
system and same domain
> two VI and two VII (2.53GHz)
> two VI and two VII (2.88GHz)
> two VII (2.53GHz) and two VII (2.88GHz)

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3rd Generation: SPARC64 VII+ (i.e. Jupiter++)
• Available on M4000-M9000
• Four SPARC V9 cores @ 2.66 and 3.0GHz
> Same thread model as Jupiter
> Large on-chip shared 11MB or 12MB L2$
• Same system chipset/interconnect
• S10U4 + MU8 minimum OS level required
> XCP1100 or greater on XSCF
• Power: ~160W @1.1v & 3.0GHz
• Can be mixed with existing SPARC64
processors
> Can mix SPARC64 VI, VII in the same
system and same domain
> two VI and two VII (2.53GHz)
> two VI and two VII (2.88GHz)
> two VI and two VII+ (2.66/3.0GHz)
> two VII (2.53/2.88GHz) and two VII+
(2.66/3.0GHz)
64KB D$
64KB I$
FPU
C1
FPU
C2
Arbiter / Switch
System Interconnect
11/12MB L2$
5B @ 530Mhz
FPU
C3
FPU
C4
System
Interface
64KB D$
64KB I$
64KB D$
64KB I$
64KB D$
64KB I$

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Details: SPARC64 VII+ (2.66GHz)
• Only for M4000/M5000
– New CPUM: 2 x SPARC64 VII+ cpus
• 2.66 GHz and 11MB of L2$
• New MOBO_B to support new SC+
• SC ASICs on original MOBO can only address up to
6MB of L2$
• Mixing SPARC64 VI, VII/VII+ in the same domain is
supported

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Details: SPARC64 VII+ (3.0GHz)
• Only for M8000 and M9000
– 3.0 GHz and 12MB of L2$
– Can be placed on new CMU_C board
– Can be placed on existing CMU boards in the field
• New CMU_C board
– 2 or 4 processors
– Has new SC+ chip, as well as earlier released MAC+
– SC ASICs on original CMU or CMU_B can only address up to
6MB of L2$
– Will support all SPARC64 versions
• Mixing SPARC64 VI, VII/VII+ in the same domain is supported
• All processors run at rated speed and are not clocked down

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SPARC64 VII/VII+ Support
• The SPARC64 VI processor and the SPARC64
VII/VII+ processor can be mounted in a mixed
configuration.
– Upgrade Solaris and XCP before using SPARC64 VII/VII+
• Use the XCP command “setdomainmode”
– cpumode
– 2 modes for this function:
• auto - Automatically determines the operational mode of
CPU at domain startup (default)
• compatible - Regardless of the CPUs mounted, sets the
operational mode of CPU to the SPARC64 VI compatible
mode.

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Modes and Mixed Configuration of CPUs
Domain 0
CMU#0 CMU#1 CMU#2 CMU#3
CMU mounted with
VII/VII+ only
CMU mounted with
VI only
CMU of mixed CPU
configuration
CMU of mixed CPU
configuration
: SPARC64 VII/VII+ processor : SPARC64 VI processor
Domain 2
Domain 1

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Implications of CPU Mode and Dynamic Reconfiguration
• To verify domain mode
> on XSCF: showdomainmode
> on domain: prtdiag
• Set mode to compatible if there is a possibly of adding SPARC64 VI cpus to a
domain that only has SPARC64 VII/VII+
Domain CPU
Configuration
Value of
cpumode
Current CPU
Operational
Mode
CPU Configuration that
can be added by DR
Operation
SPARC64 VII auto SPARC64 VII
enhanced mode
SPARC64 VII or VII+
SPARC64 VII/VII+ compatible SPARC64 VI
compatibility mode
Any CPU
SPARC64
VI/VII/VII+
auto or
compatible
SPARC64 VI
compatibility mode
Any CPU
SPARC64 VI Auto or
compatible
SPARC64 VI
compatibility mode
Any CPU

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Mixing VII+ Processors With VI or VII Processors
• To achieve the 11MB or 12MB L2$ capacity, two
conditions must be met:
– All four processors on the system board must be SPARC64
VII+. None of the four can be either SPARC64 VI or
SPARC64 VII.
– The motherboard on the M4000/M5000 must be at least
version MOBO_B, and the CMU on the M8000/M9000 must
be at least version CMU_C
• The new MOBO_B and CMU_C have the new SC+
chip, which will provide L2$ addressing up to 12MB.
• When SPARC64 VII+ is set to half of its L2$, a
message notifying this event, will be displayed and
logged.

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Mixed Configuration of CPUs on M4000/M5000
MOBO MOBO MOBO_B MOBO_B
All L2$ is 5.5MB VII+ L2$ is 5.5MB All L2$ is 11MB All L2$ is 5.5MB
: SPARC64 VII : SPARC64 VI: SPARC64 VII+
CPU Board
CPU Board
CPU Board
CPU Board
CPU Board
CPU Board
CPU Board
CPU Board

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Mixed Configuration of CPUs on M8000/M9000
CMU_B CMU or CMU_B CMU_C CMU_C
All L2$ is 6MB All L2$ is 5MB or
6MB
All L2$ is 12MB All L2$ is 6MB
: SPARC64 VII : SPARC64 VI: SPARC64 VII+

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Performance
• Performance peak (best performance) is at small
warehouses/JVM
– +27%(M4000)/+23%(M8000) gains at large warehouse/JVM
compared with Jupiter+
• Cache hit rate reaches almost 100% up to 4 threads per
chip. This may be the reason of the peak
• For reference, test measured
performance under “SMT=off”
(means 4 out of 8 threads
enabled in a chip)
• +79% compared to Jupiter+ on M4000
• +57% compared to Jupiter+ on M8000
Preliminary !

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SPARC64 VII+ SW Plan
• Support Solaris 10 12/07 (Update 4) with
Maintenance Update Bundle 8 (MU8) at minimum

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XCP1100
• XCP1100 New Feature/Enhancements
– SPARC64 VII+ (2.66/3.0GHz)
– New SC+ on CMU_C board
– Many bug fixes

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XCP1100 is a Requirement For SPARC64 VII+ !
• If you attempt to poweron a SPARC64 VII+ CPU module with firmware
lower than XCP1100, the poweron command will fail, and the CPUs will
be marked with a "Faulted" status, making them unusable in this
system:
– XSCF> showstatus
– MBU_B Status:Deconfigured;
– * CPUM#0-CHIP#0 Status:Faulted;
– * CPUM#0-CHIP#1 Status:Faulted;
– * CPUM#1-CHIP#0 Status:Faulted;
– * CPUM#1-CHIP#1 Status:Faulted;
– * CPUM#2-CHIP#0 Status:Faulted;
– * CPUM#2-CHIP#1 Status:Faulted;
– * CPUM#3-CHIP#0 Status:Faulted;
– * CPUM#3-CHIP#1 Status:Faulted;
– ...
• To fix this problem, customers would have to make a service call so that
they could run a special clearfault command.
• Upgrade the XCP firmware BEFORE inserting the new CPUs !

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XCP Changes Since Introduction
XCP
Version
New Features
XCP1050 • Full Featured BUI
• XSCF Failover
• COD CLI
• “admin” account added for Remote
Installation Support
XCP1060 • COD BUI Support
XCP1061 • Bug fixes only
XCP1070 • Support for SPARC64 VII at 2.4 and
2.52GHz
XCP1071 • Combine SPARC64 VI and VII in same
system
XCP1080 • Support for M3000
• Ability to dump and restore XSCF
configuration
• ping and traceroute commands added
XCP1081 • Ability to set login lockout
• Support of 8GB DIMMS
• Support of 2-core SPARC64 VII on M3000
• Power consumption monitoring on M3000
XCP1082 • SNMP trap enhancements
• Air flow measurements on M4000/M5000
• SSH over DSCP
XCP Version New Features
XCP1090 • Support 2.53GHz/2.88GHz SPARC64 VII
• Support MAC+ on M8000/M9000
• Airflow and Power monitoring on M3000
• Airflow indicator on M8000/M9000
• SNMP alert on loss of PSU
• New commands: setdateoffset
XCP1091 • Active Directory support
• LDAP over SSL support
• Support 2.75GHz SPARC64 VII
XCP1092 • New commands: setpacketfilters,
showpacketfilters
XCP1093 • Support of F20 Flash Accelerator on
M4000-M9000
• COD terminology changes
XCP1100 • Support new SPARC64 VII+ in M4000-
M9000
• iSCSI boot support
• Airflow indicator on M4000/M5000
• Enhanced Mail utility

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•SPARC Enterprise Server Sales Essentials
– http://ilearning.oracle.com/ilearn/en/learner/jsp/rco_details_find.jsp?srchfor=null&rcoid=784330681
– http://ilearning.oracle.com/ilearn/en/learner/jsp/rco_details_find.jsp?srchfor=null&rcoid=784429534
•High-End SPARC Server Solution Selling
– http://ilearning.oracle.com/ilearn/en/learner/jsp/rco_details_find.jsp?srchfor=null&rcoid=784331157
•Sun Hardware Resource Center on Retriever
– http://retriever.us.oracle.com/apex/f?p=121:3:944168630568435:::3:P3_PAGE_ID:651
•SPARC Enterprise Technical Sales Essentials
– http://ilearning.oracle.com/ilearn/en/learner/jsp/rco_details_find.jsp?srchfor=null&rcoid=784330692
•External SPARC page on Oracle.com
‒ http://www.oracle.com/us/products/servers-storage/servers/sparc-enterprise/index.html
SPARC Enterprise Resources

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Resources
• Main Product Page:
– http://www.oracle.com/us/products/servers-storage/servers/sparc-enterprise/m-
series/index.html
• White Papers
– M-Series Architecture: http://www.oracle.com/technetwork/articles/systems-hardware-
architecture/m-seriesarchitecture-163844.pdf
– HA for the M-Series: http://www.oracle.com/technetwork/articles/systems-hardware-
architecture/m-seriesha-163810.pdf
– Performance Considerations on the M-Series:
http://www.oracle.com/technetwork/articles/systems-hardware-
architecture/mseriesperfconsiderations-163845.pdf
• Contacts:
– Product Manager for M3000/M4000/M5000 and I/O Expansion Unit: Chad Bender
(chad.bender@oracle.com)
– Product Manager for M8000/M9000: Chris Scheufele (chris.scheufele@oracle.com)
– Technical Marketing: Gary Combs (gary.combs@oracle.com), Kelly Wilson
(kelly.wilson@oracle.com), Rob Ludeman (rob.ludeman@oracle.com)
• Useful Links
– Gary’s M-Series Resource Page: http://esp.west.sun.com/~grc/opl/
– I/O Wiki: http://wikis.sun.com/display/PlatformIoSupport/Home
– Memory Config Rules Paper: http://panacea.central.sun.com/twiki/pub/Main/StefOPL/OPL-

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Key Takeaways - Follow-on Learning
• Oracle's new SPARC Enterprise M-Series enhancements
provide additional performance and features
– Up to 20% more performance compared to prior generation
– Continued commitment to investment protection and compatibility
– Describe the different SPARC64 CPU offerings
– Which platforms use which speed/cache CPUs
– System requirements for utilizing the SPARC64 VII+

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Appendix