The document describes research into designing reliable universal logic gates for Quantum-dot cellular automata (QCA) that are fault tolerant in the presence of cell deposition defects. Two reliable universal logic gate designs are proposed: r-ULG with a single clock zone provides 75% fault tolerance, while r-ULG-II with multiple clock zones provides 100% fault tolerance against single cell defects. Simulation results show the proposed gates can reliably implement majority, minority and universal logic functions even when cells are missing. The designs improve over existing approaches in terms of fault tolerance, area, and cell count.
IRJET- Design and Characterization of MAEC IP CoreIRJET Journal
This document describes the design and implementation of a Message Authentication Code (MAC) with integrated error correction capability called MAEC. MAEC uses a cellular automata (CA) based error correcting code to provide resilience against random errors during transmission. The key steps are: (1) Data is padded and partitioned into blocks, (2) A random maximal-length CA rule is selected based on a key using Rabin's irreducibility test, (3) Checkbytes are computed by encoding the data blocks using the CA, (4) The checkbytes and a key are mixed using NMix to generate the MAC tag, (5) During verification, received checkbytes are compared to recomputed checkbytes using the CA to detect
Ms. Christy Lilly, an ESOL teacher at Mayfield Intermediate School, was nominated for the 2012-2013 School Board Apple Award. She creates a learning environment where students actively engage in learning and supports students to reach personal goals. She uses various teaching modalities like visual and kinesthetic cues to engage students. Ms. Lilly collaborates with other teachers by researching curriculum goals and sharing ideas and materials. She communicates well with parents, students, and coworkers and builds strong relationships. As an ESOL teacher, she employs technology, research, and creative skills to plan and deliver effective instruction.
Martha Ann Burns is an information developer with over 25 years of experience producing technical documentation for software and hardware products. She has worked at IBM since 1996, where she plans, develops, and maintains documentation individually and as a team leader. Prior to IBM, she held documentation roles at several other companies developing materials for banking, lighting, and accounting systems.
Esto es lo que hacemos con las organizaciones dedicadas al estudio de la innovación social tecnológica. Conoce uno de nuestros casos de negocio en Social Venture Capital, en el cual aplicamos el modelo de la democratización y el acceso para el desarrollo de la empresa social abierta.
The document discusses the design of a new fault-tolerant scheme for quantum-dot cellular automata (QCA) logic circuits. It introduces a 2x2 array of four rotated quantum dot cells, called a complementary tile (CT), that can achieve 100% fault tolerance against single cell defects. A new majority voter logic gate called the reliable majority voter (RMV) is designed using the CT that outperforms existing QCA majority gates in terms of reliability. The document analyzes the polarization and functional characteristics of the RMV under different types of cell defects. It also develops an error probability model to quantify the reliability of the proposed RMV design.
IRJET- Design and Characterization of MAEC IP CoreIRJET Journal
This document describes the design and implementation of a Message Authentication Code (MAC) with integrated error correction capability called MAEC. MAEC uses a cellular automata (CA) based error correcting code to provide resilience against random errors during transmission. The key steps are: (1) Data is padded and partitioned into blocks, (2) A random maximal-length CA rule is selected based on a key using Rabin's irreducibility test, (3) Checkbytes are computed by encoding the data blocks using the CA, (4) The checkbytes and a key are mixed using NMix to generate the MAC tag, (5) During verification, received checkbytes are compared to recomputed checkbytes using the CA to detect
Ms. Christy Lilly, an ESOL teacher at Mayfield Intermediate School, was nominated for the 2012-2013 School Board Apple Award. She creates a learning environment where students actively engage in learning and supports students to reach personal goals. She uses various teaching modalities like visual and kinesthetic cues to engage students. Ms. Lilly collaborates with other teachers by researching curriculum goals and sharing ideas and materials. She communicates well with parents, students, and coworkers and builds strong relationships. As an ESOL teacher, she employs technology, research, and creative skills to plan and deliver effective instruction.
Martha Ann Burns is an information developer with over 25 years of experience producing technical documentation for software and hardware products. She has worked at IBM since 1996, where she plans, develops, and maintains documentation individually and as a team leader. Prior to IBM, she held documentation roles at several other companies developing materials for banking, lighting, and accounting systems.
Esto es lo que hacemos con las organizaciones dedicadas al estudio de la innovación social tecnológica. Conoce uno de nuestros casos de negocio en Social Venture Capital, en el cual aplicamos el modelo de la democratización y el acceso para el desarrollo de la empresa social abierta.
The document discusses the design of a new fault-tolerant scheme for quantum-dot cellular automata (QCA) logic circuits. It introduces a 2x2 array of four rotated quantum dot cells, called a complementary tile (CT), that can achieve 100% fault tolerance against single cell defects. A new majority voter logic gate called the reliable majority voter (RMV) is designed using the CT that outperforms existing QCA majority gates in terms of reliability. The document analyzes the polarization and functional characteristics of the RMV under different types of cell defects. It also develops an error probability model to quantify the reliability of the proposed RMV design.
Design and Development of 4-Bit Adder Programmable QCA Design using ALU Techn...IRJET Journal
This document discusses the design and development of a 4-bit adder using quantum-dot cellular automata (QCA) and an arithmetic logic unit (ALU) technique. QCA is a nano-technology that can be used to build digital circuits with lower power consumption compared to CMOS. The author proposes using ALU techniques with QCA cells to implement a 4-bit adder circuit. This includes using reversible logic and arithmetic units, multiplexers, and cascading 1-bit adders. Simulations show that a 4-bit adder implemented with QCA cells using an ALU technique has advantages like lower area and transistor count with no propagation delay compared to traditional CMOS designs.
Loc, los and loes at speed testing methodologies for automatic test pattern g...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Loc, los and loes at speed testing methodologies for automatic test pattern g...eSAT Journals
Abstract Faults, caused by timing-related defects in very large scale integrated circuits, are important to detect to optimize coverage and test time. Delay faults are only due to timing malfunction. At-speed test is only method to detect these delay faults. This paper describes and compares different at-speed testing techniques on vivid point of views along with them practical implementation. This paper also shows results generated by automatic test pattern generation tool for these techniques. Next, generated test patterns are simulated by using simulator and correctness of these methods are verified. Keywords: LOC (Launch on capture), LOS (Launch on shift), LOES (Launch on extra shift), At-speed testing.
Fault Modeling and Parametric Fault Detection in Analog VLSI Circuits using D...IRJET Journal
This document presents a method for modeling and detecting parametric faults in analog VLSI circuits using discretization. It begins with an abstract that describes detecting faults using discretization. It then provides background on fault modeling challenges in analog circuits. The main body describes modeling a biquadratic filter circuit using state-space equations, then discretizing it. It explains how discretization allows modeling the effects of single parametric faults, like a change in resistor value. The method is demonstrated through simulations in MATLAB/Simulink of detecting faults in biquadratic and leapfrog filters. Results show the method can effectively detect parametric faults in benchmark analog circuits.
DEFECT ANALYSIS OF QUANTUM-DOT CELLULAR AUTOMATA COMBINATIONAL CIRCUIT USING ...IAEME Publication
CMOS technology has achieved the device dimension in the nanometer range. Beyond this CMOS technology is the QCA (Quantum-dot Cellular Automata). Due to nanoscale defects may occur in this technology so in the consequences of it the faults will occur. This paper presents the defect analysis of QCA basic devices like Majority Voter (MV), inverter. The defect analysis and its effects on the output of combinational circuit using Hardware Description Language for QCA (HDLQ) is presented in this paper.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOPVLSICS Design
The power consumption of IC during test mode is higher than its normal mode. This brings the power as one of the major design constraints for today’s low power design technologies. In normal scan based test circuits most of the power consumed due to the switching activity of scanflops during shift and capture cycles. In this paper a novel scanflop is presented which reduces the switching activity of the scanflop for clock and it reduces the power consumption of the circuit and it also reduces area and test time too. The proposed Dual Mode One Latch Double Edge Triggered (DMOL-DET) scanflop which shift the two bits of test vector in a clock cycle, during its test mode and captures the single data in a clock cycle during its data mode. The design and functionality of the proposed scanflop is discussed and compared with the different flipflops which shows that the proposed scan flop reduces the test time and clock switching activity by 50%, area by 30% and static power by 25%.
Analysis and implementation of local modular supervisory control forIAEME Publication
1. The document describes the analysis and implementation of a local modular supervisory control system for a manufacturing cell using programmable logic controllers (PLCs).
2. A local modular approach is used where modular supervisors are obtained for each behavioral specification by considering only locally affected subsystems, avoiding state space explosion.
3. The modular supervisors are implemented on the PLC in a three-level structure that executes the supervisors concurrently and interfaces them to the physical system.
IRJET- Fault Classification using Fuzzy for Grid Connected PV SystemIRJET Journal
This document presents a study on fault classification using fuzzy logic in a grid-connected photovoltaic (PV) power system. The study aims to identify and classify faults that may occur in both the AC and DC sides of the system using a fuzzy logic controller (FLC). A 100 kW PV array is connected to a 25 kV grid via a DC-DC boost converter and a three-level voltage source converter (VSC). Faults are classified as either AC faults like inverter faults or DC faults like faults in the PV array or DC link. The performance of the proposed FLC for fault classification is demonstrated through MATLAB/Simulink simulations of different fault cases.
IRJET- Design of Memristor based MultiplierIRJET Journal
This document describes the design of a 4-bit multiplier circuit using memristors. It begins with an introduction to memristors and their advantages over CMOS technology. It then discusses different window functions that can be used for memristor models and selects the Biolek window function. The document implements a 2-bit and 4-bit array multiplier circuit using memristor-CMOS hybrid logic gates. It analyzes the results in LTSpice and finds improvements in area and component count compared to traditional CMOS and other memristor-based designs. The document concludes memristors can help reduce area for multiplier circuits.
Use of abstraction for generating timing models for hierarchicalIAEME Publication
This document discusses the use of abstraction for generating timing models for hierarchical design closure. It summarizes the process of library-based timing model generation which works by abstracting timing information for critical paths into timing arcs in a modeled timing library. It then outlines some key limitations of this approach, such as how it can fail to capture relationships between generated clocks or properly represent multi-cycle path exceptions. The document argues that addressing these limitations is important for improving the accuracy of timing models for hierarchical timing closure.
IRJET-Power Efficient Implementation of Asynchronous Counter using Intelligen...IRJET Journal
This document discusses an intelligent clock gating technique to reduce power consumption in VLSI sequential circuits. It describes implementing the technique on an asynchronous counter in Xilinx Vivado and comparing the power with and without clock gating. With intelligent clock gating, the asynchronous counter design saw a 21.57% reduction in dynamic power consumption from 3.432W to 2.692W. Intelligent clock gating automatically inserts clock enable signals to turn off unused portions of the design, reducing unnecessary switching without affecting functionality or timing constraints. This allows significant power savings to be achieved with less manual effort compared to traditional clock gating techniques.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
This document discusses application-specific reconfigurable architectures for fault testing and diagnosis in FPGAs. It provides an overview of different types of faults that can occur in FPGAs at runtime, including logical faults, interconnect faults, and delay faults. It then reviews several previous works that proposed various techniques for application-independent and application-dependent fault diagnosis in FPGAs, focusing on methods for detecting and locating logical faults and interconnect faults. The goal is to remove faults at the application level to improve FPGA performance and reliability.
Advancing VLSI Design Reliability: A Comprehensive Examination of Embedded De...IRJET Journal
The document summarizes research on Embedded Deterministic Test (EDT) logic insertion's impact on VLSI designs. Key findings include:
1) EDT insertion enhances test and fault coverage, but also increases the number of test patterns required.
2) There are significant shifts in fault sub-classes like untestable faults and tied cells after EDT insertion, highlighting its nuanced effects.
3) Results provide empirical evidence for designers to optimize testability by strategically integrating EDT logic.
IRJET- Metastability Mitigation & Error Masking of High Speed Flip-FlopIRJET Journal
This document discusses techniques for mitigating metastability and masking timing errors in high-speed flip-flops. It proposes flip-flop designs that take advantage of delayed data or pulse-based methods to detect timing violations. Simulation results show the proposed flip-flops can reduce error masking latency by up to 23% and increase the effective timing error detection window compared to state-of-the-art metastability immune flip-flops. The document also analyzes metastability in flip-flops qualitatively and quantitatively, and evaluates the performance of the proposed designs in reducing metastability errors.
FAULT DETECTION IN FIVE BUS SYSTEM USING MATLAB & SIMULINK (DISCRETE WAVELET ...IRJET Journal
This document describes a study that uses discrete wavelet transform (DWT) to detect and classify faults in a five-bus power transmission system simulated in MATLAB/Simulink. Twelve different fault types with varying durations are introduced at different transmission line locations in the five-bus system. The current signals at the receiving end of lines undergoing faults are analyzed using DWT to extract wavelet coefficients. These coefficients are then used to identify the specific fault type, location, and duration. The results demonstrate that DWT with the db8 mother wavelet can accurately detect and classify faults with mean error of -0.34% under different system conditions.
Design and Implementation of a Dual Stage Operational AmplifierIRJET Journal
This document describes the design and implementation of a dual stage operational amplifier using Miller compensation technique. It begins with an introduction to operational amplifiers and issues with single stage designs. It then provides details on the small signal model and equations for an uncompensated and Miller compensated dual stage opamp. The document outlines the design procedure and calculations to determine the transistor aspect ratios. It presents the schematic of the designed opamp along with simulation results showing improved gain, phase margin and gain bandwidth compared to an uncompensated design. In conclusion, Miller compensation is shown to effectively improve the stability and performance of the dual stage operational amplifier design.
IRJET-Study of Expenditure in Construction of Tram in Enclosed AreaIRJET Journal
This document provides a literature review of a non-isolated single stage three-port converter (NISSTPC) for hybrid microgrid applications. A NISSTPC has three bidirectional ports connected to an AC side, DC side, and storage system, allowing single-stage power conversion. This improves power conversion efficiency and power quality over conventional hybrid microgrids. The document compares NISSTPC to conventional hybrid microgrid topologies in terms of power quality, frequency deviation, and availability of storage during faults. Studies show NISSTPC provides better power quality and uninterrupted storage availability during faults. In conclusion, a hybrid microgrid using NISSTPC improves overall performance.
Neural Network Modeling for Simulation of Error Optimized QCA Adder CircuitIRJET Journal
This document proposes a Hopfield neural network model (PNN) to design an error-optimized quantum-dot cellular automata (QCA) adder circuit. The PNN model analyzes how the polarization at the output of a single-bit full adder can help build larger, more complex QCA adder circuits. It also identifies the most robust and reliable single-bit full adder design. The PNN model measures the efficiency and accuracy of polarization at each output of the adder circuit. It demonstrates the PNN model's ability to design a reliable and robust single-bit full adder circuit with optimized error and cost compared to other simulation techniques.
Design and Development of 4-Bit Adder Programmable QCA Design using ALU Techn...IRJET Journal
This document discusses the design and development of a 4-bit adder using quantum-dot cellular automata (QCA) and an arithmetic logic unit (ALU) technique. QCA is a nano-technology that can be used to build digital circuits with lower power consumption compared to CMOS. The author proposes using ALU techniques with QCA cells to implement a 4-bit adder circuit. This includes using reversible logic and arithmetic units, multiplexers, and cascading 1-bit adders. Simulations show that a 4-bit adder implemented with QCA cells using an ALU technique has advantages like lower area and transistor count with no propagation delay compared to traditional CMOS designs.
Loc, los and loes at speed testing methodologies for automatic test pattern g...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Loc, los and loes at speed testing methodologies for automatic test pattern g...eSAT Journals
Abstract Faults, caused by timing-related defects in very large scale integrated circuits, are important to detect to optimize coverage and test time. Delay faults are only due to timing malfunction. At-speed test is only method to detect these delay faults. This paper describes and compares different at-speed testing techniques on vivid point of views along with them practical implementation. This paper also shows results generated by automatic test pattern generation tool for these techniques. Next, generated test patterns are simulated by using simulator and correctness of these methods are verified. Keywords: LOC (Launch on capture), LOS (Launch on shift), LOES (Launch on extra shift), At-speed testing.
Fault Modeling and Parametric Fault Detection in Analog VLSI Circuits using D...IRJET Journal
This document presents a method for modeling and detecting parametric faults in analog VLSI circuits using discretization. It begins with an abstract that describes detecting faults using discretization. It then provides background on fault modeling challenges in analog circuits. The main body describes modeling a biquadratic filter circuit using state-space equations, then discretizing it. It explains how discretization allows modeling the effects of single parametric faults, like a change in resistor value. The method is demonstrated through simulations in MATLAB/Simulink of detecting faults in biquadratic and leapfrog filters. Results show the method can effectively detect parametric faults in benchmark analog circuits.
DEFECT ANALYSIS OF QUANTUM-DOT CELLULAR AUTOMATA COMBINATIONAL CIRCUIT USING ...IAEME Publication
CMOS technology has achieved the device dimension in the nanometer range. Beyond this CMOS technology is the QCA (Quantum-dot Cellular Automata). Due to nanoscale defects may occur in this technology so in the consequences of it the faults will occur. This paper presents the defect analysis of QCA basic devices like Majority Voter (MV), inverter. The defect analysis and its effects on the output of combinational circuit using Hardware Description Language for QCA (HDLQ) is presented in this paper.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOPVLSICS Design
The power consumption of IC during test mode is higher than its normal mode. This brings the power as one of the major design constraints for today’s low power design technologies. In normal scan based test circuits most of the power consumed due to the switching activity of scanflops during shift and capture cycles. In this paper a novel scanflop is presented which reduces the switching activity of the scanflop for clock and it reduces the power consumption of the circuit and it also reduces area and test time too. The proposed Dual Mode One Latch Double Edge Triggered (DMOL-DET) scanflop which shift the two bits of test vector in a clock cycle, during its test mode and captures the single data in a clock cycle during its data mode. The design and functionality of the proposed scanflop is discussed and compared with the different flipflops which shows that the proposed scan flop reduces the test time and clock switching activity by 50%, area by 30% and static power by 25%.
Analysis and implementation of local modular supervisory control forIAEME Publication
1. The document describes the analysis and implementation of a local modular supervisory control system for a manufacturing cell using programmable logic controllers (PLCs).
2. A local modular approach is used where modular supervisors are obtained for each behavioral specification by considering only locally affected subsystems, avoiding state space explosion.
3. The modular supervisors are implemented on the PLC in a three-level structure that executes the supervisors concurrently and interfaces them to the physical system.
IRJET- Fault Classification using Fuzzy for Grid Connected PV SystemIRJET Journal
This document presents a study on fault classification using fuzzy logic in a grid-connected photovoltaic (PV) power system. The study aims to identify and classify faults that may occur in both the AC and DC sides of the system using a fuzzy logic controller (FLC). A 100 kW PV array is connected to a 25 kV grid via a DC-DC boost converter and a three-level voltage source converter (VSC). Faults are classified as either AC faults like inverter faults or DC faults like faults in the PV array or DC link. The performance of the proposed FLC for fault classification is demonstrated through MATLAB/Simulink simulations of different fault cases.
IRJET- Design of Memristor based MultiplierIRJET Journal
This document describes the design of a 4-bit multiplier circuit using memristors. It begins with an introduction to memristors and their advantages over CMOS technology. It then discusses different window functions that can be used for memristor models and selects the Biolek window function. The document implements a 2-bit and 4-bit array multiplier circuit using memristor-CMOS hybrid logic gates. It analyzes the results in LTSpice and finds improvements in area and component count compared to traditional CMOS and other memristor-based designs. The document concludes memristors can help reduce area for multiplier circuits.
Use of abstraction for generating timing models for hierarchicalIAEME Publication
This document discusses the use of abstraction for generating timing models for hierarchical design closure. It summarizes the process of library-based timing model generation which works by abstracting timing information for critical paths into timing arcs in a modeled timing library. It then outlines some key limitations of this approach, such as how it can fail to capture relationships between generated clocks or properly represent multi-cycle path exceptions. The document argues that addressing these limitations is important for improving the accuracy of timing models for hierarchical timing closure.
IRJET-Power Efficient Implementation of Asynchronous Counter using Intelligen...IRJET Journal
This document discusses an intelligent clock gating technique to reduce power consumption in VLSI sequential circuits. It describes implementing the technique on an asynchronous counter in Xilinx Vivado and comparing the power with and without clock gating. With intelligent clock gating, the asynchronous counter design saw a 21.57% reduction in dynamic power consumption from 3.432W to 2.692W. Intelligent clock gating automatically inserts clock enable signals to turn off unused portions of the design, reducing unnecessary switching without affecting functionality or timing constraints. This allows significant power savings to be achieved with less manual effort compared to traditional clock gating techniques.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
This document discusses application-specific reconfigurable architectures for fault testing and diagnosis in FPGAs. It provides an overview of different types of faults that can occur in FPGAs at runtime, including logical faults, interconnect faults, and delay faults. It then reviews several previous works that proposed various techniques for application-independent and application-dependent fault diagnosis in FPGAs, focusing on methods for detecting and locating logical faults and interconnect faults. The goal is to remove faults at the application level to improve FPGA performance and reliability.
Advancing VLSI Design Reliability: A Comprehensive Examination of Embedded De...IRJET Journal
The document summarizes research on Embedded Deterministic Test (EDT) logic insertion's impact on VLSI designs. Key findings include:
1) EDT insertion enhances test and fault coverage, but also increases the number of test patterns required.
2) There are significant shifts in fault sub-classes like untestable faults and tied cells after EDT insertion, highlighting its nuanced effects.
3) Results provide empirical evidence for designers to optimize testability by strategically integrating EDT logic.
IRJET- Metastability Mitigation & Error Masking of High Speed Flip-FlopIRJET Journal
This document discusses techniques for mitigating metastability and masking timing errors in high-speed flip-flops. It proposes flip-flop designs that take advantage of delayed data or pulse-based methods to detect timing violations. Simulation results show the proposed flip-flops can reduce error masking latency by up to 23% and increase the effective timing error detection window compared to state-of-the-art metastability immune flip-flops. The document also analyzes metastability in flip-flops qualitatively and quantitatively, and evaluates the performance of the proposed designs in reducing metastability errors.
FAULT DETECTION IN FIVE BUS SYSTEM USING MATLAB & SIMULINK (DISCRETE WAVELET ...IRJET Journal
This document describes a study that uses discrete wavelet transform (DWT) to detect and classify faults in a five-bus power transmission system simulated in MATLAB/Simulink. Twelve different fault types with varying durations are introduced at different transmission line locations in the five-bus system. The current signals at the receiving end of lines undergoing faults are analyzed using DWT to extract wavelet coefficients. These coefficients are then used to identify the specific fault type, location, and duration. The results demonstrate that DWT with the db8 mother wavelet can accurately detect and classify faults with mean error of -0.34% under different system conditions.
Design and Implementation of a Dual Stage Operational AmplifierIRJET Journal
This document describes the design and implementation of a dual stage operational amplifier using Miller compensation technique. It begins with an introduction to operational amplifiers and issues with single stage designs. It then provides details on the small signal model and equations for an uncompensated and Miller compensated dual stage opamp. The document outlines the design procedure and calculations to determine the transistor aspect ratios. It presents the schematic of the designed opamp along with simulation results showing improved gain, phase margin and gain bandwidth compared to an uncompensated design. In conclusion, Miller compensation is shown to effectively improve the stability and performance of the dual stage operational amplifier design.
IRJET-Study of Expenditure in Construction of Tram in Enclosed AreaIRJET Journal
This document provides a literature review of a non-isolated single stage three-port converter (NISSTPC) for hybrid microgrid applications. A NISSTPC has three bidirectional ports connected to an AC side, DC side, and storage system, allowing single-stage power conversion. This improves power conversion efficiency and power quality over conventional hybrid microgrids. The document compares NISSTPC to conventional hybrid microgrid topologies in terms of power quality, frequency deviation, and availability of storage during faults. Studies show NISSTPC provides better power quality and uninterrupted storage availability during faults. In conclusion, a hybrid microgrid using NISSTPC improves overall performance.
Neural Network Modeling for Simulation of Error Optimized QCA Adder CircuitIRJET Journal
This document proposes a Hopfield neural network model (PNN) to design an error-optimized quantum-dot cellular automata (QCA) adder circuit. The PNN model analyzes how the polarization at the output of a single-bit full adder can help build larger, more complex QCA adder circuits. It also identifies the most robust and reliable single-bit full adder design. The PNN model measures the efficiency and accuracy of polarization at each output of the adder circuit. It demonstrates the PNN model's ability to design a reliable and robust single-bit full adder circuit with optimized error and cost compared to other simulation techniques.
3. TABLE III. FUNCTIONAL CHARACTERIZATION OF R-ULGS GATE
WITH MULTIPLE MISSING CELL DEFECTS.
Observation r-ULG r-ULG-II
No of defected cell→ 1 2 1 2
Output F1 F2 F1 F2 F1 F2 F1 F2
No of defective pattern 8 8 28 28 8 8 28 28
Occurrence of wire function 2 - 15 - - - 2 1
Wire function percentage 25% - 53.57% - - - 7.14% 3.57%
Occurrence of INV function - 2 - 14 - - 1 2
INV function percentage - 25% - 50% - - 3.57% 7.14%
Occurrence of Maj function 6 - 13 - 8 - 24 -
Maj function percentage 75% - 46.42% - 100% - 85.71% -
Occurrence of Minority function - 6 - 12 - 8 - 24
Minority function percentage - 75% - 42.85% - 100% - 85.71%
Occurrence of Undefined function - - - 2 - - 1 1
Undefined function percentage - - - 7.14% - - 3.57% 3.57%
TABLE IV. ADDITIONAL SINGLE CELL DEPOSITION DEFECT OF
R-ULG
Cell Cell r-ULG Output
Position Type F1 F2
P
× Maj(ABC) ABC
+ Maj(ABC) ABC
Q
× Maj(ABC) ABC
+ Maj(ABC) ABC
R
× Maj(ABC) ABC
+ C C
S
× Maj(ABC) ABC
+ Maj(ABC) ABC
III. DEFECT CHARACTERIZATION OF R-ULG
The different cell deposition defects (miss-
ing/displacement/extra deposition of cells) of the r -
ULG gate are investigated here. The defective function of
the proposed r-ULG under single and double cell deposition
(missing/additional) is reported in Table III. The results of
Table III shows that the proposed universal logic: (i) based
on r-ULG shows 75% fault tolerance and (ii) based on r-
ULG-II shows 100% fault tolerance under single cell missing
deposition. It is evident from Table II that the proposed r-ULG
achieves enviable improvement in fault tolerance (85%), area,
cell count and delay. The defective behaviour at the gate
outputs, due to extra cell deposition, is analysed in tables IV
The following observations can be made from the simu-
lation results: (1) In almost all cases, our proposed r-ULG
with undeposited cells (as defects) behaves in the following
two ways: wire functions or MV/MV-like functions. (2) Unde-
posited cell defects occurring in corner cells (cells 5, 7) change
the logic function of the r-ULG to the wire. In all other cases
of single cell missing defect, have no effect on output and thus
confirming the 75% defect tolerant design. In r-ULG-II, due
to introduction of second clock zone it has no influence on
cell missing defect and thus confirms 100% defect tolerant.
(3) In the simulations using the coherence vector engine, the
polarization level never experiences a significant drop under
cell missing defect. In all simulated occurrences, the magnitude
of the maximum polarization is above 0.9 eV (Fig. III). Note
that by definition, the MV-like function set does not include
the MV function.
It can be observed that under one cell missing defect,
the probability of having the correct majority function at the
outputs is 75% for the r-ULG and 100% for the r-ULG-II
whereas the existing fault tolerant QCA logic gates achieve
only 15% success. Again, in double cell missing defect the
proposed r-ULG logics achieve 42-85% tolerance, whereas
existing universal logic gates show 0% tolerance. Even with
multiple undeposited cells, in most cases the proposed r-ULG
produces a stable logic function: either the wire function, or the
majority-like function which are very useful for logic design.
1
2
3
4
5 6
7 8
A
B
C
F2
F1
P
Q
R S
(a) Layout of r-ULG with cell
deposition location
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1 2 3 4
AveragePolarization
# Cell Deposition
MV
MV-like
Wire
Undefined
Total
(b) Average polarization of r-ULG un-
der cell deposition
IV. SIMULATION SETUP
All the designs have been verified using QCADesigner
version 2.0.3 [9] with all default parameter specifications.
V. CONCLUSION
This paper addresses the reliability issues of
majority/minority-based computational structures synthesizing
a 100% fault tolerant universal logic in QCA (r-ULG-II)
having two complementary outputs (F1=F2). Two fault-
tolerant/reliable universal logic gate r-ULG are explored
which possess enviable 75% fault tolerance using single
clock-zone and 100% fault tolerance using multiple clock-
zone under single missing and additional cell defect. A
detailed simulation-based analysis and a characterization of
QCA defects have affirmed the reliability of the proposed
r-ULG against the manufacturing-process variations.
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