Are you working in Semiconductor, VLSI/FPGA domain? Looking for an automated test generator for your regressions? Here is RTGen! #EDA, #UVM, #SystemVerilog

1. Copyright 2014-2016, www.verifworks.com
VerifWorks
Women led, EDA start-up from India
hFp://www.verifworks.com

2. Copyright 2014-2016, www.verifworks.com
Problem?
Not enough DV
experNse
Tech challenges - Low
Power, Quality of DV
Business challenges -
Small teams, short TTM

3. Copyright 2014-2016, www.verifworks.com
Our Value ProposiNon
BeFer
chips!
Create
Fast
Verify
beFer
CerNfied
DV
process
Debug
apps

4. Copyright 2014-2016, www.verifworks.com
VerifWorks EDA
• ProducNvity tools
– DVCreate SystemVerilog
– DVCreate UVM
– DVCreate Low Power (UPF)
• Quality checks
– DVRules – “Verify your
VerificaNon code”
• Methodology, apps
– Smart Debug apps
– RTGen
Impact
• Shorter Nme-to-
market
• Increased quality
of tesNng à
designs
• OpNmized use of
$$ (ExisNng EDA
tool run Nmes)

5. Copyright 2014-2016, www.verifworks.com
Products at a glance
• SV Interface
• UVM
• Low Power
DVCreate
• UVM
• SVA
• SVTB
DVRules
• SystemVerilog
• UVM
• Formal-to-Sim adapter
RTGen
• Verilog
• SystemVerilog
• UVM
DVEnc
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6. Copyright 2014-2016, www.verifworks.com
RTGen
• Regression Test Generator
• Extracts a testcase from waveform
• Exact opposite of building a testbench and testcase
• Helps in capturing quality traces
– Typical error scenarios
– Past bugs
– SpecificaNon driven
• Formal VerificaNon (FV) to simulaNon
– Extract a test from a FV failure trace
• Executable specificaNon
– Timing Diagrams to testcase
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7. Copyright 2014-2016, www.verifworks.com
RTGen flow
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VCD EVCD
FSDB
VPD
WLF
SHM

8. Copyright 2014-2016, www.verifworks.com
RTGen in Formal flow
• RTGen is a proven technology in FV centric
flow
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FV
DUT
Model (SVA/PSL)
Pass Witness trace
FalsificaNon Counterexample

9. Copyright 2014-2016, www.verifworks.com
RTGen in Formal flow
• Big challenge in FV is debug
– Lack of $display
– No breakpoints
– No Line-stepping etc.
• A bug found is valuable
– Add to regression suite!
– Add scenario coverage
• RTGen converts a FV trace (Waves) to a
SimulaNon Testcase
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10. Copyright 2014-2016, www.verifworks.com
RTGen – in UVM flow
• UVM is great, powerful with Constrained
Random Tests (CRT/CRV)
• Random stability is a big concern in complex
testbenhces
– Add a new constraint, the “test” changes
– May not reproduce the same scenario that caught
a design bug!
• Need an easy way to add “quality tests” to
regressions
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11. Copyright 2014-2016, www.verifworks.com
Life without RTGen in UVM flow
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Found a bug?
• Retain the seed
Add directed test
• Manual effort
• Duplicate work (of
CRV test)
Add a “cover point”
• Manual process
• Error prone
• SNll requires same
“trace”

12. Copyright 2014-2016, www.verifworks.com
RTGen in UVM flow
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Found a bug?
Run RTGen
• Waves-2-Testcase
• Fully automated
process
• Get a directed test/
UVM Seq
Add to regression suite!

13. Copyright 2014-2016, www.verifworks.com
Interested to know more?
• See our product page @
hFp://www.verifworks.com
• See our blog @ hFp://www.verifworks.com
• Contact: support@verifworks.com for pricing,
availability etc.
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