Robert Gage has over 30 years of experience as an ASIC and FPGA designer, with expertise in high-speed logic design, physical design, and architecture. He has led development teams on over 20 ASIC and FPGA projects, with a focus on high-speed digital design and implementation using Cadence Encounter and Synopsys tools. Gage holds a Bachelor's degree from Harvard University and has designed and patented several chips, ASICs, and computer control systems throughout his career.

1. Robert Gage
13475 SW Tapadera St Beaverton 0R97008  503 643 4097  bobgage5@gmail.com
Profile
ASIC & FPGA Designer: Physical Design, Architecture & Logic Design. Mixed Signal & Digital
Experience
 CDI Corp. – July 2015 thru Present - Contract ASIC Design (for Teradyne)
 Lead HS Physical and logical design & debug for 40 nm TSMC Mixed Signal ASIC spin.
 Teradyne Tualatin OR - February 1996 thru May 2015: Hardware Design Engineer level 5
 ASIC designer and architect for High Speed Digital including implementing physical design.
 Expert in logic design, synthesis, timing, verification, CAE tools, and back end physical design
 Recent experience leading HSD team in TSMC and ARM 40nm libraries including 3.2 GHz logic design.
 Cadence Encounter used for last several projects, Synopsys before that. Over a dozen ASIC projects.
 Fully trained by IBM microelectronics in Chipbench, executing half dozen IBM ASICS.
 Architect and logic designer for 10.7 GHz IBM 7HP ASIC for Serial instrument. Experienced in timing and
designing with CML and ECL differential logic as well as getting the most out of single ended CMOS.
 Specialist in clock synthesis, high-speed logic design, and FPGA interfaces. Selected and acquired 40 nm IP for
latest project.
 Led small development groups throughout career. Over a dozen ASIC developments and half a dozen FPGAs.
 Designed and implemented Direct Digital Synthesis Engines underlying most Teradyne Chip Testers
 Designed and implemented High Speed Digital enabling the last two Teradyne and Nextest residue based testers.
 Executed physical designs and led development teams for 20 ASICS and FPGAS
 4 US Patents and 3 Published Papers.
 Sequent Computer Systems Beaverton OR. Nov 1989- Feb 1996 (IBM bought 2000)
 SENOIR STAFF ENGINEER
 Diagnostics design, software hardware design of computer control systems. ASIC verification and design. Computer
control system design. Modified Intel Hobbs System management card for Ethernet and developed object oriented
control library. Developed Verilog model of Intel Pentium, cache displacement diagnostics. 1 US patent and 2
published papers.
 Gould Mini Super computers San Diego CA July 1987 - Nov 1989
 Diagnostics and simulation developer and manager.
 Datagraphics Division of General Dynamics San Diego CA February 1981 – July 1987
 Test Equipment design, test equipment group manager (20 people)
 Design custom microprocessor controlled testers for Disc Drives, Memory, and physical devices such as laser print
engines.
Education
Harvard University Bachelors Degree: Major: Engineering and Applied Physics.

2. 2
UCSD - 4.0 average. . 40 credits thru 1989 all engineering and science (including AMCC ASIC design)
Skills
Expert in High Speed Logic Design Including Physical Design and Verification
Cadence Encounter, RC and Tempus, Synopsys DC and Primetime, Verilog, TCL, PERL and C++