1. NIMISHA LIMAYE
https://in.linkedin.com/in/nimishalimaye
155 Washington Street, Apt 206, Jersey City, New Jersey 07302
nimisha.limaye@nyu.edu • 917-995-7157
EDUCATION
New York University | Tandon School of Engineering, Brooklyn, NY
Master of Science, Computer Engineering (CGPA- 3.65 / 4.00) May 2017
Coursework: Introduction to VLSI System Design, Advanced Hardware Design, Computer Architecture I,
Computer Architecture II, Advanced Project (Hardware acceleration of CNN), Nanoelectronic Devices,
Real Time Embedded System Design, Digital Signal Processing-I, Internet Architecture and Protocols,
Mumbai University | Thadomal Shahani Engineering College, Mumbai, India
Bachelor of Engineering, Electronics and Telecommunication Engineering June 2015
Coursework: Digital Logic Design
EXPERIENCE
Graduate Teaching Assistant September 2016 – December 2016
 Worked as a teaching assistant for the graduate course, Introduction to VLSI System Design, for a class of 90 students.
 Conducted lectures on fabrication techniques, stick diagrams and Cadence Virtuoso and Calibre tool for FreePDK45 library.
 Guided students toward semester long project on 64 Bit SRAM. Made solutions and graded assignments.
Mentor at Womentorship Program September 2016 – December 2016
 Assisted two graduate mentees on studies, internship, and social interaction and provided them with necessary resources.
Volunteer at ECE Department, NYU Tandon School of Engineering June 2016 - August 2016
 Implemented Sigmoid, TanH and ReLU activation functions in hardware, along with max pool layer, on VC707 board using
Verilog.
 Developed a MATLAB algorithm to convert image into .coe file and transferred it to VGA monitor using a VHDL architecture.
 Updated the VHDL architecture to transfer live feed from OV7670 camera to VGA monitor using Nexys4 DDR board.
PROJECTS
Hardware Acceleration of Convolution Neural Network September 2016 – December 2016
Developed hardware accelerator for first layer of AlexNet on VC707 FPGA Board using Xilinx ISE and Vivado. Performed edge
detection on image stored in BRAM using Nexys4 DDR and ZYBO via VGA port and VC707 board via HDMI port.
Fibonacci series on MIPS CPU April 2016
Designed Fibonacci series of 40 numbers on the DE0 Nano FPGA board using In-System Memory Content Editor and Signal
Tap tools on Altera Quartus II Prime Lite 15.1 Software.
Indexed, Auto-Increment and Auto-Decrement modes for MIPS CPU April 2016
Implemented Indexed, Auto-increment and Auto-decrement addressing modes for MIPS CPU using Signal Tap and In-System
Memory Content Editor tools available on Altera Quartus II Prime Lite 15.1 software using DE0 Nano FPGA board.
Radiation Survey Meter April 2016- May 2016
Worked on keypad interface for radiation survey meter comprising of two STM32F4 development boards, to successfully convert
the detected pulses to desired units of Roentgen and Sieverts.
256 Bit SRAM September 2015 - December 2015
Created schematic of 6T SRAM cell and peripherals for 45nm technology using Cadence Virtuoso, and designed 6T SRAM cell
layout in 1.0032 µm2 area with 3 metal layers by running DRC and LVS checks using Calibre.
Router based PageRank September 2015 - December 2015
Devised algorithm for PageRank implementation of 64 websites using concept of network on-chip in Verilog HDL on Modelsim
and found top ten websites using sorting algorithm.
SKILLS
Hardware Description Languages: Verilog (Intermediate), VHDL (Intermediate)
Scripting languages: Perl (Beginner), Python (Beginner)
Programming Languages: C (Intermediate), C++ (Intermediate), MATLAB (Intermediate)
Development Boards: ZYBO, Nexys4 DDR, VC707, STM32F4, DE0 Nano
Operating Systems: Windows, Linux Ubuntu