The document provides an overview of various programmable logic devices (PLDs) including their types such as ROM, PAL, and CPLD, and discusses their capabilities for customization, design turnaround, and application-specific configurations. It further details the architecture and operational features of advanced implementations like the XC9500 CPLD family and Xilinx FPGAs, emphasizing their logic density, programmability, and integration of multiple functionalities. Additionally, it addresses the design complexities and the potential for implementing complete systems on single chips.

2. Programmable Logic Devices
¾ They are available in standard configurations from
a catalogue of parts and are sold in very high
volumes.
¾ They may be configured or programmed to create a
part customized to a specific application.
¾ No customized mask layers or logic cells are used.
¾ Fast design turnaround.
¾ Single large block of programmable inter-connect.
¾ A matrix of logic Marco-cells that usually consists
of programmable array logic followed by FF or latch
is used.

3. Types of PLD’s
¾ ROM.
¾ PAL.
¾ PLA.
¾ SPLD.
¾ CPLD.

4. ROM

5. Types of ROM
1.Mask-Programmable ROM
-Permanent data storage
-economically feasible for large production
2.Erasable Programmable ROM
-Special Charge Storage mechanism
-A PROM Programmer used to provide
voltage pulses.
-can be reprogrammed limited no.of times
3.EEPROM
- can be reprogrammed limited no.of times
4.Flash ROM
- Built-in Programming and erase Facility

6. PLA
Both AND & OR-array are programmable

7. Example of PLA
Realize the Following function using PLA :
F0 = sop m(0, 1, 4, 6) = A’B’ + AC’
F1 = sop m(2, 3, 4, 6, 7) = B + AC’
F2 = sop m(0, 1, 2, 6) = A’B’ + BC’
F3 = sop m(2, 3, 5, 6, 7) = AC + B

8. PLA with 3 input, 5 Product Terms, and
4 Outputs

9. nMOS NOR Gate
Conversion for NOR-NOR to AND-OR

10. AND-OR Array Equivalent
PLA Table

11. Realize following function using a PLA :
F1=sop m(2,3,5,7,8,9,10,11,13,15)
F2=sop m(2,3,5,6,710,11,14,15)
F3=sop m(6,7,8,9,13,14,15)

12. Minimized functions
F1= bd + b’c + ab’
F2= c + a’bd
F3= bc + ab’c’ + abd

13. Multiple output K-maps
Reduced PLA Table

16. Programmable Array Logic
(PALS)
-AND-array programmable while OR-array Fixed
Combinational PAL Segment
- Fusible links are
selectively blown

17. Segment of a Sequential PAL

18. PLDs like 22CEV10 are capable of implementing a
sequential N/W but not a complete system design.
Programmable Gate Arrays and Complex Programmable
Logic Devices are capable of implementing a complete
system design on a single chip.

19. XC9500 CPLD Family
Features:
High performance:
- 5 ns pin-to-pin logic delays on all pins
Large density range:
-36 to 288 macrocells with 800 to 6400 usable
gates
5V In-system programmable:
-Endurance of 10,000 program/erase cycles
-Program/Erase over full commercial voltage
and temp.range
supports parallel programming of multiple XC9500
devices
-24mA high drive outputs

20. ARCHITECTURE DESCRIPTION
- multiple FBs and IOBs fully interconnected by Fast
CONNECT switch matrix.
- IOB provides buffering for device inputs and outputs.
- Each FB has programmable logic capability with 36
inputs and 18 outputs.
- FSM connects all FB o/ps and I/p signal to FB I/ps.
- For each FB, 12-18 o/ps and associated o/p enable
signals drive to the IOBs.

21. XC9500 CPLD ARCHITECTURE

22. XC9500 FUNCTION BLOCKS

23. XC9500 MACROCELL

24. MACROCELL CLOCK & SET-
RESET CAPABILITY

25. PRODUCT TERM ALLOCATOR

26. PRODUCT TERM ALLOCATION
WITH 15 PRODUCT TERMS

27. PRODUCT TERM ALLOCATOR LOGIC

28. FASTCONNECT SWITCH
MATRIX

29. I/O BLOCK AND OUTPUT
ENABLE CAPABILITY

30. EPLD FAMILY
„ Logic density of 300-900 gates
„ Device erasure and reprogramming with nonvolatile
EPROM configuration element
„ Logic delay up to 10ns
„ Low power consumption
„ Can be erased with ultraviolet light allowing design
changes to be implemented quickly.

31. GENERAL DESCRIPTION
„ Uses sum-of-product logic and a programmable register.
„ Sum-of-product: programmable -AND/fixed-OR structure ;
implement logic up to eight product terms.
„ Programmable register: can be programmed for D,T,SR or
JK F/F or can be bypassed for combinational operation.
„ Macrocell register: can be clocked either by global clock or
by any input or feedback path to the AND array.

32. FUNCTIONAL DESCRIPTION
Classic architecture includes following
elements:
„ Macrocells
„ Programmable registers
„ Output enable/clock select
„ Feedback select

33. MACROCELL
„ Can be configured for
combinational or sequential
logic operation.
„ Eight product terms form a
prog.AND-array.
„ Additional product term for
asynchronous clear control
of the internal register.
„ Another product term
generates output enable or
a logic array generated
clock.
„ Eight product terms feed
the 8-I/p OR-array.

34. OUTPUT ENABLE/ CLOCK SELECT

35. - Two operating modes mode0 and mode1
- Controlled by a single programmable bit.
- Can be individually configured for each macrocell.
Mode 0:
- tri-state output buffer controlled by single product term.
- OE=’1’ => output buffer enabled.
- OE=’0’ => output has high impedance value
- macrocell flip-flop clocked by global clock input signal.
Mode 1:
- OE buffer is always enabled.
- macrocell register can be triggered by an array-clock
signal generated by a product term.

36. FEEDBACK SELECT
- Controlled by feedback multiplexor.
- Allows the designer to feed either the macrocell output
or the I/O pin input associated with the macrocell back
into the AND-array.
- macrocell output can be either the q-output of the
programmable register or the combinatorial output of
the macrocell.

37. PEEL- PROGRAMMABLE ELECTRICALLY
ERASABLE LOGIC ARRAY
ƒ large PLAs that include
logic macrocells with
flop-flops and feedback
to the logic planes.
ƒ A programmable AND-
plane that feeds a
programmable OR-
plane.
ƒ Outputs of OR-plane
divided into groups of 4
600 to 2800 equivalent
gates logic capacity.

38. LOGIC CELL IN PEEL ARRAY
„ Includes:
- a flip-flop
configurable as D, T
or JK
- two multiplexors.

39. PEEL Family
- provided by Integrated Circuit Technology.
- Useful for lower pin-count applications.
- Offering 20-44 pins
- Speeds as fast as 5ns
- Additional architectural features(more inputs, product
terms, macrocell functions)allow more logic to be put in
every part.
- PEEL arrays are CPLDs with advanced architectural
features packed into 24,28 and 44-pin packages.

40. XILINX 3000 SERIES FPGAs
- Consists array of 64 CLBs surrounded by a ring of 64 IOBs
- Interconnections between blocks are programmed by
storing data in internal Configuration memory cells

41. LAYOUT OF A ROGRAMMABLE
LOGIC CELL ARRAY(some part of it)

42. CONFIGURATION MEMORY CELL

43. XILINX 3000 SERIES LOGIC CELL

44. COMBINATORIAL LOGIC OPTIONS

45. XILINX 3000 SERIES I/O BLOCK

46. Direct interconnection
between adjacent blocks
General-purpose
interconnects

47. VERTICAL AND HORIZONTAL
LONG LINES

48. XILINX XC4000 SERIES CLB

49. XILINX XC4000 WIRE SEGMENTS

50. ARCHITECTURE OF ALTERA FLEX
8000 FPGA

51. ALTERA FLEX 8000 LOGIC
ELEMENT

52. ALTERA FLEX 8000 LOGIC
ARRAY BLOCK

53. ARCHITECTURE OF FLEX
10K FPGA

54. ALTERA APEX 20K
„ 256–3,456 LABs, each of which contains 10 Logic
Elements (LEs), so a chip contains 2,560–51,840 Les,
162,000–2,391,552 usable gates
„ 16–216 Embedded System Blocks (EABs), each of which
can provide 32,768–442,368 bits of memory
„ Can implement CAM, RAM, dual-port RAM, ROM, and
FIFO.

55. APEX LABS AND INTERCONNECT
Logic Array Blocks
- 10 Les
- each LE connects to 2 local interconnect,each local
interconnect connects to 10 LEs.
- Each LE can connect to 29 other LEs through local
interconnect.
Logic element
- 4-input LUT,carry chain, cascade chain, same as FLEX devices
Interconnect
- MegaLAB interconnect between 16 LABs, etc. inside each
MegaLAB
- FastTrack row and column interconnect between MegaLABs0

56. APEX EMBEDDED SYSTEM
BLOCKS
- Each ESB can act as a macrocell and provide product terms
- Each ESB gets 32 inputs from local interconnect, from
adjacent LAB or MegaLAB interconnect
- In this mode, each ESB contains 16 macrocells, and each
macrocell contains 2 product terms and a programmable
register (parallel expanders also provided)
- Each ESB can also act as a memory block (dual-port RAM,
ROM, FIFO, or CAM memory) configured in various sizes