1. T.PAVAN KUMAR Phone : +91-944 8823 531
Email id: pavank690@gmail.com
EDUCATION DETAILS
Name of the
Institution
Board /
Institution
Year of
Passing
Course Branch /
Stream
Aggregate
ABV-IIITM
Gwalior
Autonomous
Institute under
MHRD
2016 M.Tech VLSI design 74.9%
SRK Institute of
Technology,
Vijayawada
JNTU,
Kakinada
2013 B.Tech
Electronics &
Communication
76.82%
Sri Chaitanya
Jr.college, Guntur
Board of
Intermediate
Education,
Andhra
Pradesh
2009 12th
MPC 93.7%
Z.P.High School,
Ganapavaram
Board of
Secondary
Education,
Andhra pradesh
2007 SSC -- 89%
M.Tech Projects
 Project Title: “Efficient Hardware Implementation of Encoder and Decoder for Golaycode”.
 Outline: Golay code is an Error correcting code (ECC) can correct three errors and detect four errors.
Here a new method is proposed and implemented for Encoder and proposed a new hardware
architecture for Decoder using IMLD algorithm, the architectures for encoder and decoder are
achieved better performance than previous architecture. These architecture were implemented in
Xilinx ISE14.5 tool and synthesis is done by using synopsis design compiler using 90 nm technology.
 Project Title: “An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the
(24,12) Extended Golay Code”.
 Outline: In memories probability of occurrence of adjacent errors i.e., single, double adjacent, triple
adjacent errors are very high. IMLD algorithm is not suitable,it requires many clock cycles. A new
parallel algorithm is proposed by interleaving the message and parity check matrix. The proposed
algorithm corrects all single, double adjacent and some of the triple adjacent errors, and achieves
better performance.
PROFILE
Objective Consistently work for the company’s growth, thereby creating a platform to
Enhance my abilities as an engineer.

2.  Project Title: “An Efficient Single,Double and Triple Adjacent Error Correcting Golay Decoder
for Semiconductor Memories”.
 Outline: The Interleaved parallel Decoder was unable to correct some of triple adjacent errors.Here
a new algorithm is proposed by modifying IMLD algorithm. It can able to correct all single,double
and triple adjacent errors with less area and power than previous algorithm.
B.Tech Final Year Project
 Project Title: “GSM based Agricultural motor automation with feedback SMS”.
 Outline: In India farmers are suffered with irregular power cuts. Our project can able to overcome
that problem. We attached a GSM module to agricultural motor by using microcontroller circuit.
The GSM module indicates the power changes through SMS to farmer and farmer can able to
operate the motor by SMS.A sensor is used to check whether the motor delivering water or not, if
not it shutoff the motor and indicates it to farmer.
DECLARATION
I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the
responsibility for the correctness of the above-mentioned particulars.
(T.PAVAN KUMAR)
TECHNICAL SKILLS
 Languages : C, Verilog,Basics of Python.
 Tools known : Xilinx ISE, Micro Wind, Model Sim,Synopsis,Latex.
AREAS OF INTEREST
 Digital Design
 VLSI
 Analog Electronics
 VLSI
ACHIVEMENTS
 Secured EAMCET Rank 9606 In 2009.
 Qualified GATE 2014(Rank 2698).
 Got 2 𝑛𝑑
Prize In Talent Test Conducted By STUAP(State Teachers Union Andhra Pradesh).
Mandal Unit In Dec 2006.
 Secured School 1 𝑠𝑡
And Mandal 2 𝑛𝑑
In SSC Examinations In 2007.