This document provides an introduction to field programmable gate arrays (FPGAs) and their use in next generation computing. It explains that FPGAs allow users to create their own custom processors by programming logic gates and interconnects on the chip. The document discusses how FPGAs can run neural networks and provide more processing power than CPUs. It also summarizes the speaker's past projects using FPGAs on Raspberry Pi boards and their performance advantages over traditional servers.

1. Next generation
computing
using FPGA’s
A small what, why, how, intro
into Field Programmable Gate
Arrays
By Rolf Huisman
Rolf.Huisman@infosupport.com
@rlrhuisman

2. FPGA ?
A field-programmable gate array (FPGA) is an
integrated circuit designed to be configured by
a customer or a designer after manufacturing
– hence "field-programmable”
Source: Wikipedia
Simplified: You can create your own processor
Why should one care ?

3. Innovation Keynote Ignite 2016
Title document 307-11-16
“But we not stopping there. We are now, taking those;
neural nets, deep neural nets, convolution nets and asking
ourselves; What if we can run them not just on cpu’s or
gpu’s, what if we can run them on silicon ?”
Satya Nadella
Source: Innovation Keynote Ignite 2016

4. Innovation Keynote Ignite 2016
Dough Burger
Source: Innovation Keynote Ignite 2016

5. FPGA are powerfull
24-core 2.4 Haswell < 10 Cpu cores + 4 FPGA’s
Source: Innovation Keynote Ignite 2016

6. Last two years at Rolf’s attic
FPGA meets raspberry pi

7. Personal POC
Pension Calculation
50k transactions per second
7 x 300 Watts 1,89 Watts + 3,34 Watts
2100 Watts 5,23 Watts
Title document 707-11-16

8. What am I seeing ?
Raspberry PI
Micro
Service

9. What am I seeing ?
Raspberry PI FPGA Shield
Micro
Service
RAM
SPI
Serial
Peripheral
Interface

10. What am I seeing ?
Raspberry PI FPGA Shield
Micro
Service
RAM
FPGA Chip
My
Processor
SPI
Serial
Peripheral
Interface

11. And Gate
A B Out
0 0 0
1 0 0
0 1 0
1 1 1
Out
ANDA
B

12. Or Gate
A B Out
0 0 0
1 0 1
0 1 1
1 1 1OutORA
B
ANDA
B

13. (Multiplexer) MUX
Choosing between gates
ORA
B
Out
ANDA
B
S
S A B Out
0 0 0 0
0 1 0 0
0 0 1 0
0 1 1 1
1 0 0 0
1 1 0 1
1 0 1 1
1 1 1 1
AND
OR

14. (Multiplexer) MUX
Mux Gate
ORA
B
ANDA
B
S
Out

15. (Multiplexer) MUX
Mux Gate
ORA
B
ANDA
B
S
Out
0

16. (Multiplexer) MUX
Mux Gate
ORA
B
ANDA
B
S
Out
1

17. (Multiplexer) MUX
Mux Gate
ORA
B
ANDA
B
S
OutThe selectors are part of the “Bitstream”
This Bitstream is the configuration you
write to you’re FPGA
That’s how you are configuring/building your own dedicated processor

18. Reality is a bit more complex
In reality:
Gates are Look Up Tables (LUT) with 5 or 6 inputs,
and 2 outputs
Flip-Flops (Memory cells)
Routing Fabric (Lot of Multiplexers to route signals)
IO pins connecting to outside world
And a lot I’ll ignore for now
Signal Timings
Heating within the FPGA chip
Power consumption
…

19. Specifying/Programming
Direct
– VHDL
– Verilog
– Gate Diagrams
Indirect:
– (HLS) C
– Open-CL
VHDL of Blinking light (“Hello World”)

20. Constraints
Specify which pins are connected
Specify Packages
BGAQFP144

21. Synthesis,Mapping,Placing,Routing
Automatic, Manual, or Both
Specify
Can take weeks if very complex

22. Generating Bitstream and upload

23. Debugging
Hardware
simulations
JTAG interface
Oscilloscope

24. Conclusion
FPGA’s is a very interesting technology
– Powerful
– Efficient
FPGA’s is also a difficult technology
– Steep learning curve
– Synthesis, mapping, and routing can take ages
– Highly parallel and physical interference makes for
fun debugging sessions
– Physical behavior (Heating of chip, chirp)
Use abstractions like open-cl if you're able to
Title document 2407-11-16

25. Thanks

26. Spartan-6 LX9 ~17$
715 CLB’s
9.152 LUT6’S
102 IO Pins*
*The XC6SLX9-2TQG144C only has
94 pins bonded

27. In comparison to the Ignite demo
Stratix V D5, depending on the version:
– Between 300k and 952k LUTS (Compared to 9k
Spartan 6-LX9)
– Between 1K $ and 5K $ (Compared to 17 $ Spartan
6-LX9)
And he has four of them J