@LAFK_pl, Polish JUG, May 2014 2
@LAFK_pl, Polish JUG, May 2014 3
MANAGEMENT!!
@LAFK_pl, Polish JUG, May 2014 4
Posted in 2012...
@LAFK_pl, Polish JUG, May 2014 5
... and still not corrected
@LAFK_pl, Polish JUG, May 2014 6
Leslie Lamport
● Distributed system
clocks
● Happens-before
● Sequential
Consistency
@LAFK_pl, Polish JUG, May 2014 7
Bill Pugh
● FindBugs
● Java Memory Model
is broken
● Final - Volatile
● Double-checked
locking
● New JMM
@LAFK_pl, Polish JUG, May 2014 8
Sarita Adve
● Java Memory Model
is broken
● Number of great
papers on memory
(consistency) models
● Best definition of
MCM I found
@LAFK_pl, Polish JUG, May 2014 9
Within these 15-20 minutes
Intro
Memory model means?
Hardware
Java stuff
@LAFK_pl, Polish JUG, May 2014 10
Memory model?
If NOT about GC then...
what's it about?
@LAFK_pl, Polish JUG, May 2014 11
Memory CONSISTENCY
● Allowed optimizations
● Possible behaviours / executions of a (possibly
multithreaded!) program
● Which cores / threads see which values
● How to make it consistent for us, programmers
@LAFK_pl, Polish JUG, May 2014 12
@LAFK_pl, Polish JUG, May 2014 13
@LAFK_pl, Polish JUG, May 2014 14
Where it matters?
● Javac / Jython / ...
● JIT
● Hardware of course
● So JMM is a
LANGUAGE memory
consistency model
@LAFK_pl, Polish JUG, May 2014 15
Hardware
● CISC or RISC CPU
● Number of registers
● Caches size or type
● How many functional units per CPU
● Pipeline:
● Instruction decode > address decode > memory
fetch > register fetch > compute ...
@LAFK_pl, Polish JUG, May 2014 16
Program / code optimizations?
● Reorder
● (e.g. prescient store)
● Remove what's unnecessary
● (e.g. synchronize)
● Replace instructions / shorten machine code
● Function optimizations
● (e.g. Inlining)
● ...
@LAFK_pl, Polish JUG, May 2014 17
Exemplary CPU
@LAFK_pl, Polish JUG, May 2014 18
Barriers / fences
„once memory has been pushed to the cache
then a protocol of messages will occur to
ensure all caches are coherent for any shared
data. The techniques for making memory
visible from a processor core are known as
memory barriers or fences.
– Martin Thompson, Mechanical Sympathy
differs per architecture / CPU / cache type!
@LAFK_pl, Polish JUG, May 2014 19
Barriers / Fences
● CPU instruction
● Means „Flush now!”
● Forces update
● Starts cache
coherency protocols
● Read / Write / Full
@LAFK_pl, Polish JUG, May 2014 20
@LAFK_pl, Polish JUG, May 2014 21
Summarizing Java Language Spec:
● Describes whether the execution trace is a legal
execution of the program
● Works by examining each read and checking
write observed by that read
● Write is valid when it follows certain rules
● Describes possible behaviours of the program
● Implementor adhering to above can optimize
code as he likes
@LAFK_pl, Polish JUG, May 2014 22
What rules?
● Write is valid when it follows certain rules
@LAFK_pl, Polish JUG, May 2014 23
Before, or after?
@LAFK_pl, Polish JUG, May 2014 24
Before, or after?
@LAFK_pl, Polish JUG, May 2014 25
JSR-133 = new JM(C)M
@LAFK_pl, Polish JUG, May 2014 26
Class Reordering {
int x = 0, y = 0;
public void writer() {
x = 1;
y = 2;
}
public void reader() {
int r1 = y; // TUTAJ: y == 2 => x == ?
int r2 = x;
}
}
Reordering - classic example
@LAFK_pl, Polish JUG, May 2014 27
What was wrong with old JM(C)M?
You took a look, read the specs entire and...
@LAFK_pl, Polish JUG, May 2014 28
@LAFK_pl, Polish JUG, May 2014 29
New Java Memory Model
●
SC on single-core and single-thread CPU is
fine but it doesn't cut it now
●
To ensure visibility, JVM JMM spec ensures:
●
final
●
volatile
●
Synchronized
are done well thistime
@LAFK_pl, Polish JUG, May 2014 30
Barriers in Java – rules
● JMM
● volatile – sfence after write, lfence before read
● final – sfence after init (field visibility)
● Atomic instructions (like lock) = mfence
@LAFK_pl, Polish JUG, May 2014 31
Further topics
● Why MCM and not a threading library?
H.Boehm
● Better MCM? Sarita Adve
● Possible optimizations and their gains
● Performance of Java and hardware MCMs?
Clashes?
● JMCM rules in more detail

Java Memory (Consistency) Model - Polish JUG One Beer Talk #2

  • 2.
  • 3.
    @LAFK_pl, Polish JUG,May 2014 3 MANAGEMENT!!
  • 4.
    @LAFK_pl, Polish JUG,May 2014 4 Posted in 2012...
  • 5.
    @LAFK_pl, Polish JUG,May 2014 5 ... and still not corrected
  • 6.
    @LAFK_pl, Polish JUG,May 2014 6 Leslie Lamport ● Distributed system clocks ● Happens-before ● Sequential Consistency
  • 7.
    @LAFK_pl, Polish JUG,May 2014 7 Bill Pugh ● FindBugs ● Java Memory Model is broken ● Final - Volatile ● Double-checked locking ● New JMM
  • 8.
    @LAFK_pl, Polish JUG,May 2014 8 Sarita Adve ● Java Memory Model is broken ● Number of great papers on memory (consistency) models ● Best definition of MCM I found
  • 9.
    @LAFK_pl, Polish JUG,May 2014 9 Within these 15-20 minutes Intro Memory model means? Hardware Java stuff
  • 10.
    @LAFK_pl, Polish JUG,May 2014 10 Memory model? If NOT about GC then... what's it about?
  • 11.
    @LAFK_pl, Polish JUG,May 2014 11 Memory CONSISTENCY ● Allowed optimizations ● Possible behaviours / executions of a (possibly multithreaded!) program ● Which cores / threads see which values ● How to make it consistent for us, programmers
  • 12.
  • 13.
  • 14.
    @LAFK_pl, Polish JUG,May 2014 14 Where it matters? ● Javac / Jython / ... ● JIT ● Hardware of course ● So JMM is a LANGUAGE memory consistency model
  • 15.
    @LAFK_pl, Polish JUG,May 2014 15 Hardware ● CISC or RISC CPU ● Number of registers ● Caches size or type ● How many functional units per CPU ● Pipeline: ● Instruction decode > address decode > memory fetch > register fetch > compute ...
  • 16.
    @LAFK_pl, Polish JUG,May 2014 16 Program / code optimizations? ● Reorder ● (e.g. prescient store) ● Remove what's unnecessary ● (e.g. synchronize) ● Replace instructions / shorten machine code ● Function optimizations ● (e.g. Inlining) ● ...
  • 17.
    @LAFK_pl, Polish JUG,May 2014 17 Exemplary CPU
  • 18.
    @LAFK_pl, Polish JUG,May 2014 18 Barriers / fences „once memory has been pushed to the cache then a protocol of messages will occur to ensure all caches are coherent for any shared data. The techniques for making memory visible from a processor core are known as memory barriers or fences. – Martin Thompson, Mechanical Sympathy differs per architecture / CPU / cache type!
  • 19.
    @LAFK_pl, Polish JUG,May 2014 19 Barriers / Fences ● CPU instruction ● Means „Flush now!” ● Forces update ● Starts cache coherency protocols ● Read / Write / Full
  • 20.
  • 21.
    @LAFK_pl, Polish JUG,May 2014 21 Summarizing Java Language Spec: ● Describes whether the execution trace is a legal execution of the program ● Works by examining each read and checking write observed by that read ● Write is valid when it follows certain rules ● Describes possible behaviours of the program ● Implementor adhering to above can optimize code as he likes
  • 22.
    @LAFK_pl, Polish JUG,May 2014 22 What rules? ● Write is valid when it follows certain rules
  • 23.
    @LAFK_pl, Polish JUG,May 2014 23 Before, or after?
  • 24.
    @LAFK_pl, Polish JUG,May 2014 24 Before, or after?
  • 25.
    @LAFK_pl, Polish JUG,May 2014 25 JSR-133 = new JM(C)M
  • 26.
    @LAFK_pl, Polish JUG,May 2014 26 Class Reordering { int x = 0, y = 0; public void writer() { x = 1; y = 2; } public void reader() { int r1 = y; // TUTAJ: y == 2 => x == ? int r2 = x; } } Reordering - classic example
  • 27.
    @LAFK_pl, Polish JUG,May 2014 27 What was wrong with old JM(C)M? You took a look, read the specs entire and...
  • 28.
  • 29.
    @LAFK_pl, Polish JUG,May 2014 29 New Java Memory Model ● SC on single-core and single-thread CPU is fine but it doesn't cut it now ● To ensure visibility, JVM JMM spec ensures: ● final ● volatile ● Synchronized are done well thistime
  • 30.
    @LAFK_pl, Polish JUG,May 2014 30 Barriers in Java – rules ● JMM ● volatile – sfence after write, lfence before read ● final – sfence after init (field visibility) ● Atomic instructions (like lock) = mfence
  • 31.
    @LAFK_pl, Polish JUG,May 2014 31 Further topics ● Why MCM and not a threading library? H.Boehm ● Better MCM? Sarita Adve ● Possible optimizations and their gains ● Performance of Java and hardware MCMs? Clashes? ● JMCM rules in more detail