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![OUT
CLK
RESET
DETGND
GND
GND
GND
GND
GND
I/O
DETECT
VCC VPP
OUT
BIIN
IN
SCHEMATIC DEFINED CONSTRAINTS (YES/NO)
CKPLUS RULE EXCEPTIONS
TABLE_DASHBOARD_INFO
REQUIRED
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZEDRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
EVT101
BOARD_ID[1]
MLB_C
SIM CARD
SPI0 TEST MODE
MLB
BOARD REVISION
S/W READ FLOW
2. DISABLE PU AND ENABLE PD
1. SET GPIO AS INPUT
BOARD_ID[0]
ID[3-0] SYSTEM
1. SET GPIO AS INPUT
BOOT_CONFIG[3-0]
2. DISABLE PU AND ENABLE PD
BOOT_CONFIG[3] (GPIO29)
S/W READ FLOW
BOOT_CONFIG[0] (GPIO18)
BOOT_CONFIG[2] (GPIO28)
BOARD ID
3. READ
BOARD_ID[3]
BOARD_ID[2]
BRD_REV[2-0]
3. READ
1. SET GPIO AS INPUT
S/W READ FLOW
3. READ
BOOT_CONFIG[1] (GPIO25)
BOOT CONFIG ID
1010 J85 AP
1011 J85 DEV
1100 J86 AP
1101 J86 DEV
1110 J87 AP
1111 J87 DEV
MLB_B
0000
0010
JTAG
SPI0
0011
0001
2. ENABLE PU AND DISABLE PD
NAND <-- SELECTED
NAND TEST MODE
ID_J85_J87
2.2K
5%
01005
1/32W
MF
R1205
01005
5%
MF
1/32W
2.2K
R1201
NOSTUFFNOSTUFF
2.2K
1/32W
5%
R1200
MF
01005 01005
5%
2.2K
1/32W
MF
R1203
NOSTUFF
MF
1/32W
2.2K
5%
R1206
ID_DEV
01005
ID_J86_J87
5%
2.2K
01005
1/32W
MF
R1204
R1260
5%
100
MF
1/32W
01005
01005
1/32W
2.2K
5%
MF
R1213
4 52
100
5%
1/32W
MF
01005
R1210
01005
R1250
0%
0.00
1/32W
MF
NOSTUFF
SIM-CARD-X113-X223
F-ST-SM
CELL
J3000
24 28 52
24 28 52242852
242852
C3002
CELL
CERM
6.3V
5%
100PF
01005
01005
MF
1/32W
1%
CELL
15.00K
R3000
C3001
0402
X5R
10%
16V
1.0UF
CELL
01005
MF
1/32W
5%
2.2K
R1202
1/32W
5%
100
R1211
01005
MF
NOSTUFF
2.2K
01005
5%
MF
R1207
1/32W
2.2K
MF
5%
R1208
01005
1/32W
NOSTUFF
5%
2.2K
01005
1/32W
MF
R1209
NO
SYNC_DATE=04/11/2011SYNC_MASTER=N/A
SOC: MISC & ALIASES
GPIO_BOOT_CONFIG2
SIMCRD_CLK_CONN
SIMCRD_RST_CONN
PP_LDO6_RUIM_1V8
NC_J3000_5
SIMCRD_IO_CONN
SIM_TRAY_DETECT
MAKE_BASE=TRUE
WDOG_SOC WDOG_SOC2PMU_RESET_IN
MAKE_BASE=TRUE
I2S3_BT2SOC_DATA I2S4_BT2SOC_DATA
I2S3_SOC2BT_DATA
MAKE_BASE=TRUE
I2S4_SOC2BT_DATA
I2S3_SOC2BT_BCLK
MAKE_BASE=TRUE
I2S4_SOC2BT_BCLK
I2S3_SOC2BT_LRCK
MAKE_BASE=TRUE
I2S4_SOC2BT_LRCK
RESET_SOC_LJTAG_SOC_TRST_L
JTAG_SOC_SEL
GPIO_BOARD_ID1
GPIO_BOARD_REV1
SOC_FAST_SCAN_CLK
GPIO_BOARD_ID2
GPIO_BOARD_REV2
GPIO_BOOT_CONFIG3
GPIO_BOARD_REV0
GPIO_BOARD_ID3
SOC_HOLD_RESET
SOC_TESTMODE
=PP1V8_SOC
=PP1V8_SOC
GPIO_BOARD_ID0
GPIO_BOOT_CONFIG0
GPIO_BOOT_CONFIG1
051-0886
A.0.0
12 OF 121
10 OF 54
1
2
1
2
1
2
1
2
1
2
1
2
1 2
1
2
1
2
1 2
3
2
8
11
10
12
4
9
6
7
1
5
2
1
1
2
2
1
1
2 1
2
1
2
1
2
1
2
5
24252752
4 48
5 44
5 44
5 44
5 44
4 8 11 24 48 52452
5
5
4
5
5
5
5
5
4
4 52
457101854
457101854
5
5
5](https://image.slidesharecdn.com/ipadmini2fullschematicdiagram-180314104851/85/iPad-mini-2-full-schematic-diagram-11-320.jpg)
Uploaded byPhonefix
iPad mini 2 full schematic diagram
The document contains technical specifications and proprietary information related to printed circuit boards (PCBs) for Apple Inc. It emphasizes the confidential nature of the information and includes various part and drawing numbers associated with the components. Additionally, it outlines the obligations of the possessor regarding the handling of this sensitive information.
iPad mini 2 full schematic diagram
- 1. R2040 R2050 U2720 L2050 L2040 C8190 C8140 C8141 L5700 L8229 DZ5700 R8100 C8149 DZ5703 DZ5704DZ5702 U1400 DZ8120 D8230 D8228 D8100 L2201 DZ5710 Q8104 Q8123 XW1902 XW1903 XW1900 C1026 C1004 C1405 C1007 C1404 C8210 U8550 L8103 L8100 L8104 L8106 L8105 L8102 L8101 L8111 L8108 L8107 L8109 U8100 L8110 C8145 Y8200 U1700 U2200 U0652 Y0602 C2800 C5701 C8233 C8237 C8307 C8139 C8201 C8136 C8200 C8203 C8230 DZ2963 DZ2961 DZ2962 DZ2960 J2201 J1700 D5700D5702D5701D5703 U3000 U3001 U3002 U3003 J7500 C3432 C4235 C4100 C4101 C4232 C4322 C4323 R8323 R8324 R8321 R8322 R8327 L2962 L2961 L2960 L2963 L2901 L2900 L1800 L2602 L2800 L2903 L2902 L1920 L2601 L2600 L1700 L1701 L1702 FL7500 L4440 C1912 C1908 C1906 C1905 C1950 C1907 C1901 C1070 C2907C2910C2901C2904 C1701 C1361 C8235 C2047 C2048 C1909 C2058 C2053 C2052 C2041C2042 C2057 C2043 C8150 C8172 C8171 C8160 C81A2 C81A1 C81A7 C8161C8158C8184C8182C8180C8178C8175C8157C81A3C81A0C81A5C81A6 C2051 C1910 C8193 C8194 C5800 C5801 C3205 C3208 C3206 C3207 C3204 C2202 C2241 C8239 C8290 C8238 C8231 C8226 C8169 C8241 C8155 C8211 C8240 C8232 C8163 C8164 C8153 C8187 C8186 C8185C8183C8181C8179C8177C8176C81A4 C8170 C8162 C8151 C8154 C8168 C8156 C8167 C8166 C8152 C8234 C8188 C8159 C8165 C4507 C4485 R1901 R1951 R1950 R1952 R2051R2041 R5700 R5 82 0 R5 81 0 R5 83 0 R8130 R8116 R8173 R8399 R8303 R4739 R4607 R4139 R4608 R4437 R1953 R1931 R1930 L4801 R4801 R8172 R8146 R8170 R3702 C4058 C4049 L3817 C4048 L3821 R4 60 5 R4701 L4747 L4746 R0770 R0765 R1207 R1454 R1260 R0870 R2450 R0753 R0752 R0871 R2727 R0832 R2750 R0617 R1250 R0705 R0704 R1211 R0703 R0702 R1052 R1051 R1000 R0738 R1940 R0646 R1920 R2757 R2405 R0831 R0655 R0720 R2400 R2406 R2747 R0640 R1461 R1912 R1913 R1910 R1911 R1460 R2902 R2901 R2900 R2903 R0721 R1209 R1208 R0739 R1213 R8352 R1006 R1005 R1001 R0751 R1205 R1206 R0933 R0930 R0941 R0940 R1201 R0701 R0931 R0750 R2801 R2601 R1850 R2800 R2241 R5790 R5791 R1790 R2243 R1753 R1752 R2242 R2250 R8240 R8231 R8232 R8235 R8239 R8227 R5706R5705 R0736 R5802 R5800 R5801 R5804 R5803 R3401 R8330 R3307R3305 R3306 R3304 R3301 R3300 R3530R3531 R4500 R3002 R3003 R3502 R3402 R3403 R3400 R3303 R1751 R2205 R2290 R3000 R2291 R0651 R0771 R1370 R8411 R8435 R8410 R8445 R8450 R8451 R8430 R8420 R8425 R0735 R5805 R4534 R3604 C3905 C3904 C3914 C3913 C3903 R3600 C4146 C3910 R3602 L4029 R3603 R3601 L4012 R4064 L4044 L4030 R4065 L4070 R4300 L4435 L4802 L4803 L1900 L1901 L1902 L1903 L5702 L5701 C5824 C5 82 1 C5814 L5811 C5811 L4765 L3814 L3815 L3813 L3806 L3805 L3804 C3808 L4257 C3810 L4317 L4138 L4097 C4320 L4439 L4136 L4438L4437 L4 61 3 R3700 C4807 L4743 C4799 C3809 L4200 L4701 C4708 C4064 C4056 L3820 L2741 L2702 L2700 L2701 L2660 L2950 L1904 L1905 L1760 L2240 L3520 FL4802 C1411 C1402 C1401 C1400 C2094 C1410 C1412 C1480 C8109 C1116 C2095 C8110 C8105 C2090 C2091 C8131 C8101 C8356 C1115 C8111 C8108 C8117 C8120 C8114C8116 C8112 C1170 C1171 C8115 C8118 C8113 C8119 C8100C8106 C8107 C8102C8103 C8104 C8132 C8130 C2723 C2700 C5880 C5882 C5881 C3222 C3200 C3201 C3202 C3220 C3221 C3223 C3218 C3001 C1753 C8127 C8123 C8122 C8121 C8124 C8126 C8125 C8550 C8128 C8129 C3715 C3701 C4504 C1103 C1148 C1027 C1015 C1009 C1100 C1102 C1101 C1122 C1117 C1119 C1118 C1120 C1121 C1174 C1176 C1172 C1173 C1177 C1175 SL9303 SL9304 SL9300 SL9305 C2962 C2726 C2046 C1914 C1904 C1920 C1932 C1930 C1913 C2963 C1931 C2961 C2960 C2056 C2054 C2093 C2044C2092 C8350 C8352 C9000 C1903 C2803 C2802 C2807 C1801 C4801 C4802 C5704 C1702 C1705 C1708 C7524 C5700 C8285 C8281 C8282 C8283 C8284 C8280 C2233 C2221 C5823 C5825 C5 82 2 C5 82 6 C5820 C5827 C5815 C5813 C5816 C5 81 0 C5817 C5703C5702 C1751 C1750 C2240C8143 C8216 C8142 C8146 C2203 C1302 C2239 C2230 C8259 C8196 C8305 C8306 C8215 C8242 C1917 C1916 C4047 C4060 C4063 L4228 L4229 C4155 L4642 C4151 C4150 C4154 C3434 L4807 C4803 C4208 C4794 R4711 L4072 L4316 L4071 C1406 C2400 C2710 C1911 C1951 C2401 C1407 C2607 C2604 C2601 C1704 C1707 C3417C3405 C3407 C3422 C3433 C1413C1450 C3230 C3210 C3211 C3212 C3213 C3416C3408 C3418 C3419 C3420 C3406 C3410 C3411 C3415 C3404 C3424 C3425 C3401 C3403 C3421 C3400 C3402 C3412 C3409 C3414 C3413 C3426 C3219 C3214 C3217 C3215 C3216 C3431 C8308 C8144 C1360 C1752 C1303 C81A9 C8138 C8137 C8135 C81A8 C8355 C3700 C4002 C4230 C4149 C4487 C4319 C3231 C2045 C2055 C3228 C3224 C3226C3225 C3229 C8250 C8252 C8253 C8254 C8148 C8147 C8251 C8212 C1490C1493 C0618 C1052 C1915 C1902 C1494C0607 C0613 C1461 C1991 C1990 C1491 C1460 C1002 C2725 C2721 C2711 C2701 C2750 C2900 C2905 C2903 C2971 C2805 C2804 C2908 C2970 C2603 C2806 C1822 C1802 C1830 C1820C1821 C1800 C1850 C2608 C2606 C2801 C2911 C2909C2973 C2906C2972 C2980 C2902 C2605 C2602 C2600 C1700 C2249 C2248 C2247 C2246 C1703 C2245 C2244 C1760 C1706 C2251 C2243 C2242 C2250 C1761 C7526 C7523 C7525 C7522 C2260 C2232 C5705 C5707 C3002 C3423 C3520 C1492 C3300 C3227 C3500 C4500 C3203 C3209 C2270 C1321 C8301 C1301 C1320 C1300 C1322 C8400 C8310 C8555 C8460 C3600 C3720 C3718 C3717 C3601 C3704 C3703 C3702 C3714 C3713 C3712 C3705 C3711 C3710 C4797 C4545C3719 C3708 C3707 C3709 C4798 C4739 C4738 C4737 C4736 C4710 C3902 C3706 C3906 C3716 C3908 C3909 C3721 C3801 C3911 C3804 C3803 C3800 C3807 C3806 C4502 C4503C4148 C3912C3805C3802 C4508 C3602 C4008 C4227 C4228 C4229 C4219C4218 C4038 C4042 C4054 C4023 C4076 C4075 C4072 C4012 C4039 C3811 C4052 C4147 C4053 C4074 C4073 C4001 C4043 C4041 C4669C4668 C4034C4033 C4055 C4664 C4663 C4639 C4666 C4665 C4622 C4317 C4316 C4641 C4489 C4318 C4486 C4483 C4471 C4484 C4488 C4472 C4467 C4805 C4804 C4809 C4234 C4233 C4207 C4104 C4102 C4103 C4324C4325 C4326 C4327 C4239 L4045 C4231 L4020 J5820 J5810 U2201 U2710 U8350 J2960 J4800 J4910 XW5897 XW5891 XW5890 XW5892 XW5896 XW5895 XW5894 XW5893 XW3301 XW3303 XW3200 XW3305 XW8410 PP9406 PP9416 PP9417 PP9419 PP9420 PP9421 PP9422 PP9423 PP9424 PP9425 PP9403 PP9468PP9469 PP9471 PP9472 PP9482PP9483 FL4801 J1800 U2601 U2600 J2601 J4802 J2800 J2950 U2800 L2801 L2803 L2807 XW2700 L2808 L2802 L2804 MH9300 XW2701 XW3002 XW3003 SP* SSSPPP*** U8400 Q8440 XW2051 XW2050 XW2951 XW2950 XW2600 XW7520 U2400 XW8114 X W 8 1 0 2 X W 8 1 0 1 XW8106 XW2041 XW2040 XW8103 X W 8 1 0 7 XW8104 XW8105 L5 81 0 L4083 L4806 L4805 L4804 C4071 L3809 L3808 C4046 C4061 L3204 Y3300 XW3304 XW3302 XW3300 U3520 L3201 L3202L3203 L3200 STD9302 J3000 L2212L2242L2232L2202L2222 U5820 L2200 L5703 L2911L2910L2912 L2610L2611 L5704 U1900 U3400 U3300 U5810 MH9302 STD9301 STD9300 L4740 C4756 C4755 L4742 L3903 L3902 L3909 C3901 L3901 L3906 L3824 L3822 L3908 L3907 L3905 L3904 L3823 L4122 L4182 L4254 L4253 C4216 L4123 L4314L4315 L4436 L3807 L3811 L3812 L3810 C4037 C4040 R3901 C3907 L3819 U4722 U4500 U3803 FL4211 U4215 U4358 U4027 U4617 U4410 U4714 U4000 U3801 SW4601 U3802 FL4012 L4500 U4801 U3600 U2700 C3000 L3800L3802 L3803L3801 L8225 U5800 U3901 C4 23 6 C4640 FL3901 U4123 U4025 U2040 U2050 U9000 U1300 L8112 U5811 FL3902 L3840 L3825 C4321 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * *** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * TOP SIDE ASSEMBLY LAYER BOARDS) AS APPLICABLE. 062-0031 (DOUBLE-SIDED BOARDS) OR 062-0073 (MULTI- TO STANDARDS AS DEFINED IN APPLE SPECIFICATION ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM NOTES: ORIG DIV APPLE THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED HURLEY DESIGNER 01/08/13 DATE SCALE 1:1 (II) NOT TO REPRODUCE OR COPY IT (III) NOT TO REVEAL OR PUBLISH IT THE POSSESSOR AGREES TO THE FOLLOWING (I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE PROPRIETARY PROPERTY OF APPLE THE INFORMATION CONTAINED HEREIN IS THE NOTICE OF PROPRIETARY PROPERTY DRAWING NUMBER TITLE 820-4124-A X200 MLB (C1) PCBF,
- 2. Apple Inc. NOTICE OFPROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART 8 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. IV ALL RIGHTS RESERVED II NOT TO REPRODUCE OR COPY IT 3 B 7 BRANCH DRAWING NUMBER SIZE D SHEET R DATE D A C PAGE A C 3456 D B 8 7 6 5 4 2 1 12 APPD CK 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DRAWING TITLE DESCRIPTION OF REVISIONREV ECN REVISION PROPRIETARY PROPERTY OF APPLE INC. TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_HEAD REFERENCE DESIGNATOR(S) BOM OPTION TABLE_5_HEAD QTY DESCRIPTIONPART# DRAWING TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM SCH AND BOARD PART NUMBERS MLB-C1 X200 0002535199A 051-0886 A.0.0 2014-01-13PRODUCTION RELEASED 1 OF 121 1 OF 54 SCH,MLB-C1,X200 LAST_MODIFIED=Tue Oct 29 15:52:27 2013 J85 MLB_C12/05/20122218 VIDEO: EDP SUPPORT & CONN BUTTON: CONN N/A N/A2117 AUDIO: CS35L19A AMPS KAVITHA 01/18/20122016 KAVITHA 01/18/20121915 AUDIO: L81 CODEC AUDIO: HP FLEX CONN N/A1814 TOUCH: SUPPORT CKT & CONN N/A 06/21/20101713 IO: TRISTAR N/A N/A1311 SOC: MISC & ALIASES N/A 04/11/20111210 SOC: VDD, SRAM, CPU, GPU PWRS N/A 04/18/2011119 SOC: SRAM, IO PWRS N/A 04/18/2011108 SOC: DP,MIPI MLB 05/04/201297 SOC: NAND N/A 04/18/201186 N/A 05/05/201175 SOC: MAIN N/A 04/18/201164 BOM TABLES J72_MLB_C11/26/201243 BLOCK DIAGRAM: SYSTEM J85_MLB_B04/02/201322 11/26/201212154 POWER: ALIASES J72_MLB_C J85 MLB_C12/03/129352 J72_MLB_C11/26/20129051 SEP: EEPROM & SOC DEBUG J85 MLB_C11/26/201285 POWER: PP1V8_SW J72_MLB_C11/26/20128449 PMU: ANYA PAGE 4 J72_MLB_C11/26/20128348 PMU: ANYA PAGE 3 J85 MLB_C12/03/20128247 PMU: ANYA PAGE 2 J72_MLB_C11/26/20128146 PMU: ANYA PAGE 1 N/A N/A7545 POWER: BATTERY CONNECTOR WIFI_DEV05/20/20135844 WIFI/BT: MODULE N/A 04/18/20115743 IO: FILTERS & HOTBAR CONN RADIO_MLB_8710/29/20134942 CELL: ANTENNA FEEDS RADIO_MLB_8710/29/20134841 CELL: GPS RADIO_MLB_8710/29/20134740 CELL: RX DIVERSITY RADIO_MLB_8710/29/20134639 CELL: ASM AND HB LTE FRONT-END RADIO_MLB_8710/29/20134538 CELL: PA DCDC CONVERTER RADIO_MLB_8710/29/20134437 CELL: 2G PA RADIO_MLB_8710/29/20134336 CELL: BAND 5/8 PAD RADIO_MLB_8710/29/20134235 CELL: BAND 7/20 PAD RADIO_MLB_8710/29/20134134 CELL: BAND 2/3 PAD RADIO_MLB_8710/29/20134033 CELL: PENTABAND PA RADIO_MLB_8710/29/20133932 CELL: RF TRANSCEIVER (3 OF 4) RADIO_MLB_8710/29/20133831 CELL: RX MATCHING RADIO_MLB_8710/29/20133730 CELL: RF TRANSCEIVER (2 OF 2) RADIO_MLB_8710/29/20133629 CELL: RF TRANSCEIVER (1 0F 2) RADIO_MLB_8710/29/20133528 CELL: BASEBAND (2 OF 2) RADIO_MLB_8710/29/20133427 CELL: BASEBAND (1 OF 2) RADIO_MLB_8710/29/20133326 CELL: BASEBAND PMU (2 OF 2) RADIO_MLB_8710/29/20133225 CELL: BASEBAND PMU (1 0F 2) RADIO_MLB_8710/29/20133024 CELL:AP INTERFACE & DEBUG CONNECTORS N/A N/A2923 CAMERA: REAR CONN & FILTERS J85 MLB_C12/05/122822 SENSOR: PROX CONTENTS DATESYNC MASTERPDF CSA N/A N/A2721 SENSOR: ACCEL, COMPASS, GYRO SYNC MASTERCONTENTS DATECSAPDF TABLE OF CONTENTS N/A N/A11 PCB11820-4124 PCBF,MLB-C1,X200 1 SCH1051-0886 SCH,MLB-C1,X200 J72_MLB_C11/26/20129453 TEST: EE TP/PPCAMERA: FF-ALS CONN & FILTERS J85 MLB_C12/03/20122620 SENSOR: OSCAR J72_MLB_C11/26/20122419 NAND STORAGE 05/04/20121412 TEST: TP/HOLES/FIDUCIALS 50 03/31/2011 MLB SOC: I/OS
- 3. Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT HSIC2 HSIC1 I2C2 I2S1 ALS I2C3 CSA 27CSA 27CSA 27 BATTERY I2S3 I2S4 CSA 13 SPI2 I2S2 CSA 14 CSA 28 1-3 CSA 17 HALL EFF OSCAR I2C0 CSA 24 FMI0 COMPASS SPI1 I2C0 CUMULUS CSA 81-84 FRONT CAMERA UART3 DISPLAY/ BUTTON FLEX AMP LEFT SPEAKER USB2.0 WIFI/BT ANT WIFI/BT ANT CSA 58 TRISTAR REAR CAMERA BT_I2S MIPI1C MIPI0C ISP1_I2C ISP0_I2C UART2 UART6 SPI XSP HP FMI1 NAND FLASH UART4 DWI UART5 EDP CSA 75 I2C1 PMU BACKLIGHT TOUCH PANEL SPI BUS GYROACCELEROMETER HOME BUTTON PROX SENSOR ANYA PRIMARY CELLULAR ANT NOT ON CELLULAR/ JTAG GRAPE GPS DIVERSITY CELLULAR ANT HSIC1 WIFI-ONLY CONFIG WIFI/BTUART1 GPS ANT SIM CARD USART ALCATRAZ MBUS CSA 31-46 MIMO MIC1 MIC2 CSA 19 L81 CODEC AUDIO RIGHT USB ASPI2S0 CSA 20 CSA 20 UART0 AMP SPEAKER CUMULUS SYNC_DATE=04/02/2013SYNC_MASTER=J85_MLB_B BLOCK DIAGRAM: SYSTEM 051-0886 A.0.0 2 OF 121 2 OF 54
- 4. TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART#DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD REFERENCE DESIGNATOR(S) BOM OPTION TABLE_5_HEAD QTY DESCRIPTIONPART# TABLE_5_ITEM Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT BOM OPTIONSBOM GROUP TABLE_BOMGROUP_HEAD TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_5_ITEM TABLE_5_ITEM TABLE_BOMGROUP_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) TABLE_5_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM TABLE_5_ITEM CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_HEAD PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S) REFERENCE DESIGNATOR(S) BOM OPTION TABLE_5_HEAD QTY DESCRIPTIONPART# TABLE_5_ITEM WIFI 4.3UF CAP U2200 338S1233 ST MICRO - DISQUAL’ED PMU 338S1191 OLD ACCEL - ST MICRO 338S1114 OLD ACCEL - ST MICRO 338S1158 OLD GYRO - ST MICRO OLD INVENSENSE P/N 338S1200 (3/22/13) OLDER INVENSENSE P/N 338S1135 GYRO MECHANICAL PARTS Page Notes ACCEL Power aliases required by this page: 128GB_PROD ANDGATE_TI FERRITE_TY JTAG_DAP DEVELOPMENT_JTAG_TAP COMMON BOM OPTIONS 64GB_PROD ALTERNATE MLB (WDOG TO PMU) BOM options provided by this page: 32GB_PROD 16GB_PROD FERRITE_TDK Signal aliases required by this page: (NONE) WIFI BOM OPTIONS SOC (NONE) FLASH CONFIGURATIONS BARCODE LABEL/EEEE CODES NOTE: FOLLOWING J72, U2200 USES 353S3672 FOOTPRINT (353S4272 HAS SMALLER PADS DUE TO NEW DFM RULES) U5800339S0213339S0223 RDAR #13988471C1009,C1015,...138S0657138S0702 132S0288 1 CRITICAL338S1163 IC,ACCEL,3-AXIS,DIG,BMA282,LGA14 U2700 CRITICALU81001343S0656 IC,PMU,ANYA,D2089A1,OTPXX,FCCSP342 1 U1400TOS,19NM,PPN1.5,C,12DP,64GB 96GB335S0929 SYNC_DATE=11/26/2012SYNC_MASTER=J72_MLB_C BOM TABLES FENCE,RADIO,MLB,C BRD,X221806-7613 1 PD_CAN_RADIO CRITICAL 1 CRITICALPD_FENCE_MLB806-6207 FENCE,TALL,MLB,X221 BASIC COMMON,ALTERNATE C2726CAP 0.1UF 16V 0201 CRITICAL GYRO_INVENSENSE1 C2726CAP 0.01UF 25V 0201132S0391 CRITICAL GYRO_STMICRO1 U27201 GYRO_INVENSENSECRITICAL338S1218 TOS,19NM,PPN1.5,C,QDP,32GB335S0922 32GB1 U1400 1 U1400 64GB335S0923 TOS,19NM,PPN1.5,C,ODP,64GB CRITICAL EEEE_X200C_BETTER_IVSFNJFEEEE FOR 639-5389 (X200C1 BETTER IVS)1825-7639 CRITICAL GYRO_STMICRO338S1192 1 GYRO, ST MICRO U2720 U0652H6P + 1GB ELPIDA339S0207 1 CRITICAL HYNIX DDRU0652339S0207339S0208 335S0923 HYNIX 20NM PPN1.5 64GB64GB U1400335S0932 335S0931 335S0922 HYNIX 20NM PPN1.5 32GB32GB U1400 U140016GB HYNIX 20NM PPN1.5 16GB335S0921335S0930 U14001 TOS,19NM,PPN1.5,C,16DP,128GB 128GB335S0924 EEEE FOR 639-5391 (X200C1 BEST+ IVS) EEEE_X200C_BEST+_IVSFNJ7 CRITICAL1825-7639 EEEE_X200C_ULTIMATEFNJ6EEEE FOR 639-5387 (X200C1 ULTIMATE)825-7639 1 CRITICAL EEEE_X200C_BESTFNJ9EEEE FOR 639-5385 (X200C1 BEST)825-7639 1 CRITICAL EEEE_X200C_BETTERFNJ5EEEE FOR 639-5394 (X200C1 BETTER) CRITICAL825-7639 1 EEEE_X200C_GOODFNJDEEEE FOR 639-5393 (X200C1 GOOD)1 CRITICAL825-7639 EEEE_X200C_GOOD_IVSFNJ8EEEE FOR 639-5388 (X200C1 GOOD IVS)825-7639 CRITICAL1 EEEE_X200C_ULTIMATE_IVSFNJGEEEE FOR 639-5392 (X200C1 ULTIMATE IVS) CRITICAL1825-7639 EEEE_X200C_BEST_IVSFNJCEEEE FOR 639-5390 (X200C1 BEST IVS) CRITICAL1825-7639 EEEE_X200C_BEST+FNJHEEEE FOR 639-5386 (X200C1 BEST+)825-7639 1 CRITICAL U14001 16GB335S0921 TOS,19NM,PPN1.5,C,DDP,16GB U2200IC,SLG5AP1423V,PWR SW,GREENFET3,4A,TDFN8353S4272 1 GYRO, INVENSENSE 051-0886 A.0.0 4 OF 121 3 OF 54
- 5. SYM 1 OF13 HSIC2_STB USB_VSSA0 USB_ANALOGTEST TESTMODE USB_DP USB_DM WDOG TST_CLKOUT FAST_SCAN_CLK USB_REXT USB_VBUS USB_ID JTAG_SEL JTAG_TRST* JTAG_TDO JTAG_TDI HSIC_VSS120 JTAG_TCK JTAG_TMS JTAG_TRTCK XI0 XO0 HSIC0_DATA HSIC0_STB HSIC2_DATA HSIC_VSS121 HSIC_VSS122 RESET* CFSB HOLD_RESET FUSE1_FSRC HSIC1_DATA HSIC1_STB USB_VDD330 USB_DVDD VDD_ANA_PLL_CCC ANALOGMUXOUT HSIC_VDD120 HSIC_VDD122 HSIC_VDD121 VDD_ANA_PLL IN BI BI OUT IN IN IN BI BI BI BI IN IN IN IN TP IN IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT H6P: JTAG, USB, PLL, HSIC, XTAL USBHS ON/OFF TOLERANCE 5V/1.98V NOTE: NEW USB_REXT VALUE FOR H6 = 200 OHM TBD: XTAL PASSIVES WILL CHANGE ON H6P WITH FIRST HW BUILD OLD (H5) VALUE: 44.2 OHM (REPLACE WITH XW LATER?) NOTE: CANDIDATE FOR COST-SAVINGS (25MA) (25MA) (5.4MA) (6X1MA) (1MA) VDDIO18_GRP4 VDDIO18_GRP1 (3X13MA) HSIC_VDD120 HSIC_VDD122 HSIC_VDD121 VDDIO18_GRP3 1.8V TOLERANT C0630 20% 0.1UF 01005 X5R-CERM 6.3V R0642 MF 1% 01005 200 1/32W R0622 010050.00 C0608 X5R 10% 0.01UF 6.3V 01005 C0648 10% X5R 6.3V 0.01UF 0100501005 0.1UF 20% C0651 6.3V X5R-CERM C0690 0.22UF 6.3V 20% X5R 0201 U0652 H6P FCMSP POP-1GB-DDR OMIT C0607 12PF 16V CERM 01005 5% 100K 1% R0617 01005 MF 1/32W C0618 10% 6.3V X5R-CERM 01005 1000PF R0651 68.1K 1/32W MF 1% 01005 46 11 52 11 52 10 81011244852 1052 C0613 5% 16V CERM 12PF 01005 1052 100K R0647 1% 01005 MF 1/32W R0646 1/32W MF 01005 1% 100K 1/32W MF 01005 1% 100K R0645 4453 4453 242753 242753 41152 41152 Y06021.60X1.20MM-SM 24.000MHZ-30PPM-9.5PF-60OHM 10 452 TP-P55 TP0600 10 10 52 C0691 0.22UF 6.3V 20% X5R 0201 R0655 01005 1% 1/32W MF 1.00M MF 1/32W 1% 01005 R0640 1.33K C0627 6.3V 10% 01005 0.01UF X5R SOC: MAIN SYNC_DATE=04/18/2011SYNC_MASTER=N/A =PP1V8_SOC =PP1V0_USB_SOC XTAL_SOC_24M_I XTAL_SOC_24M_O =PP3V3_USB_SOC PP1V8_PLL_SOC_F =PP1V2_HSIC_SOC RESET_SOC_L SOC_24M_O USB_VBUS_DETECT USB_REXT =PP1V8_PLL_SOC NC_USB_ANALOGTEST SOC_TESTMODE USB_SOC_P USB_SOC_N WDOG_SOC SOC_TEST_CLKOUT SOC_FAST_SCAN_CLK USB_VBUS_DETECT_R NC_USB_ID TP_JTAG_SOC_TDO NC_JTAG_SOC_TRTCK NC_HSIC0_DATA NC_HSIC0_STB NC_ANALOGMUXOUT JTAG_SOC_SEL JTAG_SOC_TMS JTAG_SOC_TDI JTAG_SOC_TCK SOC_HOLD_RESET JTAG_SOC_TCK JTAG_SOC_TMS JTAG_SOC_TDI =PP1V8_SOC MAKE_BASE=TRUE HSIC2_WLAN_STB HSIC2_BB_STB HSIC2_BB_DATA HSIC1_WLAN_STB MAKE_BASE=TRUE HSIC1_BB_DATA JTAG_SOC_TRST_L HSIC1_BB_STB MAKE_BASE=TRUE HSIC2_WLAN_DATA MAKE_BASE=TRUE HSIC1_WLAN_DATA 6 OF 121 A.0.0 4 OF 54 051-0886 2 1 1 2 1 2 2 1 2 1 2 1 2 1 AM34 H23 D26 AB3 B29 A29 AD4 AC3 AD3 E23 D23 E24 D28 E28 E27 F27 H20 C28 F28 D27 F25 E25 A26 B26 AM33 H21 AM32 F29 E29 D29 H16 A27 B27 F23 F24 AE20 E26 G22 AM31 G23 U16 1 2 1 2 2 1 1 2 1 2 1 2 1 2 42 13 2 1 1 2 1 2 2 1 457101854 54 54 52 54 54 52 41152 41152 452 457101854
- 6. OUT OUT IN OUT IN IN IN IN IN IN IN OUT OUT OUT OUT IN OUT OUT OUT IN OUT OUT OUT IN OUT IN OUT IN IN IN IN IN IN IN BI IN OUT OUT OUT OUT IN OUT OUT OUT OUT IN IN IN OUT IN OUT OUT IN IN OUT IN OUT IN OUT OUT IN OUT IN IN OUT OUT OUT OUT IN OUT IN OUT SYM 2 OF13 GPIO4 UART6_TXD UART6_RXD UART5_RTXD UART4_RTSN UART4_CTSN UART3_RXD UART3_RTSN UART3_CTSN UART2_TXD UART2_RXD UART2_RTSN UART2_CTSN UART1_TXD UART1_RXD UART1_RTSN UART1_CTSN UART0_TXD UART0_RXD TMR32_PWM2 TMR32_PWM1 TMR32_PWM0 GPIO8 GPIO7 GPIO6 GPIO5 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 GPIO31 GPIO3 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO2 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO1 GPIO0 UART4_RXDGPIO29 GPIO30 UART3_TXD UART4_TXD GPIO10 GPIO9 SPI3_SSIN SPI3_MOSI SPI3_MISO SPI2_SSIN SPI2_SCLK SPI2_MOSI SPI2_MISO SPI1_SSIN SPI1_SCLK SPI1_MOSI SPI1_MISO SPI0_SSIN SPI0_SCLK SPI0_MOSI SPI0_MISO SOCHOT1 SOCHOT0 SIO_7816UART1_SCL SIO_7816UART1_RST SIO_7816UART0_SCL SEP_7816UART1_SCL SEP_7816UART0_RST I2S4_MCK I2S4_LRCK I2S4_DOUT I2S4_DIN I2S4_BCLK I2S3_MCK I2S3_LRCK I2S3_DOUT I2S3_DIN I2S3_BCLK I2S2_MCK I2S2_LRCK I2S2_DOUT I2S2_DIN I2S2_BCLK I2S1_MCK I2S1_LRCK I2S1_DOUT I2S1_DIN I2S1_BCLK I2S0_MCK I2S0_LRCK I2S0_DOUT I2S0_DIN I2S0_BCLK I2C3_SDA I2C3_SCL I2C2_SDA I2C2_SCL I2C1_SDA I2C1_SCL I2C0_SDA I2C0_SCL DWI_DO DWI_DI DWI_CLK SIO_7816UART0_SDA SIO_7816UART0_RST SEP_7816UART1_SDA SEP_7816UART1_RST SEP_7816UART0_SCL SEP_7816UART0_SDA SIO_7816UART1_SDA SPI3_SCLK DISP_VSYNC SYM 3 OF 13 OUT OUT BI BI BI BI OUT OUT OUT OUT IN OUT IN IN IN IN OUT IN IN IN OUT OUT OUT IN IN IN IN OUT IN BI OUT IN OUTOUT OUT OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT VDDIO18_GRP2VDDIO18_GRP2 (SCREEN ROTATION LOCK) VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP1 VDDIO18_GRP2 VDDIO18_GRP1 SOC I/OS VDDIO18_GRP2 VDDIO18_GRP2 VDDIO18_GRP1 VDDIO18_GRP1 PMU TRISTAR SPK AMPS PROX ALS R0700 1/32W 5% 2.2K MF 01005 MF 01005 2.2K 5% 1/32W R0701 MF 01005 1.8K 1/32W 5% R0702 MF 01005 1.8K 1/32W 5% R0703 01005 MF 2.2K 5% 1/32W R0705R0704 5% 1/32W 2.2K MF 01005 13 1352 1352 1352 220K 1/32W MF 5% 01005 R0771 220K 5% 1/32W MF 01005 R0770 R0765 5% MF 1/32W 220K 01005 1/32W 1% MF 01005 R0738 100K 1/32W 100K 1% MF 01005 R0737 100K 1/32W 1% 01005 MF R0736R0735 01005 1% 100K MF 1/32W 51348 51748 22 242652 10 10 11 24 28 52 11 24 28 52 15 15 15 15 1553 1553 15 15 10 10 10 10 48 53 48 52 1% MF 01005 33.2 1/32W R0720 1553 10 10 10 17 17 51748 10 45 48 1653 1653 1653 1653 1553 1553 1553 15 1% 1/32W 33.2 01005 MF R0721 1653 548 48 10 1352 1352 44 44 44 53 44 53 11 52 11 52 19 48 19 19 53 19 53 4453 24 28 24 28 10 19 13 52 242752 242752 242752 242752 242752 11 52 11 52 FCMSP H6P POP-1GB-DDR U0652 OMIT CRITICAL OMIT H6P FCMSP POP-1GB-DDR CRITICAL U0652 13 5 51 5 51 5 16 52 5 11 48 52 5 19 5 16 52 5 19 5 11 48 52 5 48 R0751 1/32W 5% 2.2K MF 01005 R0750 01005 MF 2.2K 1/32W 5% R0753 NOSTUFF 1/32W 5% 2.2K MF 01005 R0752 NOSTUFF 01005 MF 2.2K 1/32W 5% 100K 5% MF 1/32W 01005 R0754 1/32W 100K 01005 MF 5% R0755 44 53 44 53 10 10 10 1552 2852 20 2428 552 19 242652 18 1148 16 28 28 516 R0739 1/32W MF 100K 1% 01005 28 5 20 22 5 20 22 16 5 16 5214 14 SYNC_DATE=05/05/2011SYNC_MASTER=N/A SOC: I/OS GPIO_SOC2BEACON_EN GPIO_SOC2AJ_HS3_SHUNT_EN DISPLAY_SYNC GPIO_SOC2AJ_HS4_SHUNT_EN =PP1V8_SOC NC_SPI1_NAVAJO_MISO NC_SPI1_NAVAJO_MOSI NC_SPI1_NAVAJO_SCLK NC_GPIO_NAVAJO2SOC_INT GPIO_SPKAMP_RST_L GPIO_SOC2PMU_KEEPACT HSIC1_SOC2WLAN_HOST_RDY HSIC2_BB2SOC_REMOTE_WAKE HSIC2_BB2SOC_DEVICE_RDY HSIC2_SOC2BB_HOST_RDY SOCHOT1_L SOCHOT0_L I2C2_SCL_1V8 GPIO_BTN_VOL_UP_L HSIC1_SOC2WLAN_HOST_RDY GPIO_FORCE_DFU GPIO_SPKAMP_KEEPALIVE HSIC1_WLAN2SOC_REMOTE_WAKE NC_SEP_7816UART1_SDA DWI_AP_DO PMU_GPIO_OSCAR2PMU_HOST_WAKE UART3_SOC2BB_TX UART2_WLAN2SOC_TX UART2_SOC2WLAN_TX UART1_SOC2BT_TX UART1_BT2SOC_TX UART1_BT2SOC_RTS_L UART1_SOC2BT_RTS_L UART0_SOC_RXD GPIO_OSCAR_RESET_L GPIO_BTN_VOL_DOWN_L GPIO_BTN_ONOFF_L UART0_SOC_TXD UART3_BB2SOC_TX UART3_SOC2BB_RTS_L UART3_BB2SOC_RTS_L SOCHOT1_L =PP1V8_S2R_MISC GPIO_BTN_SRL_L I2C1_SOC2OSCAR_SWDIO_1V8 I2C1_SOC2OSCAR_SWDCLK_1V8 =PP1V8_SOCGPIO_BTN_HOME_L GPIO_BTN_ONOFF_L =PP1V8_S2R_MISC =PP1V8_ALWAYS NC_SEP_7816UART0_RST SEP_I2C0_SDA HSIC1_WLAN2SOC_DEVICE_RDY NC_SEP_7816UART1_SCL I2C0_SCL_1V8 I2C1_SOC2OSCAR_SWDIO_1V8 I2C0_SDA_1V8 I2S2_CODEC_XSP_LRCK I2S2_CODEC_XSP_DIN I2S1_SPKAMP_DOUT I2S1_SPKAMP_MCK I2S0_CODEC_ASP_LRCK SPI2_CODEC_CS_L SPI2_CODEC_SCLK SPI2_CODEC_MOSI SPI2_CODEC_MISO SPI1_GRAPE_CS_L SPI1_GRAPE_SCLK SPI1_GRAPE_MOSI NC_SPI0_SSIN GPIO_BOARD_ID1 BB_JTAG_TCK BB_JTAG_TDI BB_JTAG_TMS I2S3_SOC2BT_DATA I2S3_BT2SOC_DATA I2S2_CODEC_XSP_BCLK I2S0_CODEC_ASP_MCK_R I2S0_CODEC_ASP_DOUT I2S0_CODEC_ASP_DIN I2S0_CODEC_ASP_BCLK OSCAR_TIME_SYNC_HOST_INT GPIO_BTN_SRL_L GPIO_BTN_HOME_L I2S0_CODEC_ASP_MCK I2S2_CODEC_XSP_DOUT I2S3_SOC2BT_BCLK SPI1_GRAPE_MISO GPIO_BOARD_ID0 I2S1_SPKAMP_LRCK I2S1_SPKAMP_DIN UART6_TS_ACC_RXD UART6_TS_ACC_TXD UART4_SOC2OSCAR_TXD CLK_32K_SOC2CUMULUS UART5_BATT_RTXD UART4_OSCAR2SOC_RXD NC_UART2_CTS NC_UART2_RTS I2C3_SDA_1V8 I2C3_SCL_1V8 SEP_I2C0_SDA SEP_I2C0_SCL BB_JTAG_TDO BB_JTAG_TRST_L I2C2_SCL_1V8 I2C0_SDA_1V8 I2C0_SCL_1V8 I2C2_SDA_1V8 TP_SOC_TST_CPUSWITCH_OUT SEP_I2C0_SCL NC_SEP_7816UART1_RST I2S3_SOC2BT_LRCK GPIO_BOARD_REV0 GPIO_BOARD_REV1 GPIO_BOARD_REV2 GPIO_CODEC_IRQ_L GPIO_SOC2BB_WAKE_MODEM GPIO_GRAPE_IRQ_L BB_IPC_GPIO GPIO_ALS_IRQ_L GPIO_BOARD_ID3 GPIO_BB2SOC_RESET_DET_L GPIO_BOOT_CONFIG0 GPIO_PMU2SOC_IRQ_L GPIO_SOC2PMU_KEEPACT GPIO_GRAPE_RST_L GPIO_BB2SOC_GPS_SYNC GPIO_SOC2BB_RADIO_ON_L GPIO_BOOT_CONFIG1 GPIO_FORCE_DFU TP_GPIO_DFU_STATUS GPIO_SOC2OSCAR_DBGEN GPIO_BOOT_CONFIG2 GPIO_BOOT_CONFIG3 GPIO_SOC2BB_RST_L GPIO_PROX_IRQ_L GPIO_SPKAMP_RST_L GPIO_TS2SOC2PMU_INT GPIO_SPKAMP_LEFT_IRQ_L GPIO_SOC2LCD_PWREN GPIO_BT_WAKE GPIO_BB2SOC_GSM_TXBURST I2C1_SOC2OSCAR_SWDCLK_1V8 GPIO_BOARD_ID2 I2C2_SDA_1V8 I2C3_SCL_1V8 I2C3_SDA_1V8 DWI_AP_CLK GPIO_SPKAMP_RIGHT_IRQ_L GPIO_SPKAMP_KEEPALIVE NC_GPIO_BB_HSIC_DEV_RDY NC_GPIO_GYRO_IRQ1 I2S1_SPKAMP_BCLK I2S1_SPKAMP_MCK_R =PP1V8_S2R_MISC SOCHOT0_L 051-0886 A.0.0 7 OF 121 5 OF 54 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 AD5 Y31 W31 AM5 AU3 AV3 AP1 AN4 AN3 AM1 AM2 AM3 AL5 AK3 AK4 AL4 AL2 AR18 AR19 AC32 AD34 AC31 AE5 AE2 AF1 AE4 AT17 AT16 AR16 AP16 AT15 AT14 AR14 AP15 AD1 AV13 AT13 AT12 AN14 AR13 AP12 AP13 AK2 AJ4 AB2 AJ5 AG5 AH4 AH2 AH3 AG4 AG3 AG1 AF2 AB1 AC5 AT3AP14 AU13 AN1 AT2 AF4 AF3 AP11 AN12 AV10 AN8 AP7 AR6 AU6 AR5 AU4 AV4 AU5 AV5 AT5 AP5 AN6 AP17 AP18 AA32 AA33 AA31 AR2 AR1 AE31 AE32 AE33 AD31 AF33 AG31 AH33 AG34 AF31 AG32 E30 AJ34 AH34 AH31 AJ33 AL33 AK33 AK34 AJ32 AL34 C30 AL31 AK31 AJ31 AL32 W32 W30 AR11 AT11 AU7 AP8 AR7 AV6 AT19 AT18 AP19 AB31 AB33 AP4 AR4 AP3 AP2 AA34 AT10 AN17 1 2 1 2 1 2 1 2 1 2 1 2 1 2 457101854 5 16 5 48 5 44 53 28 24 28 24 28 5 49 52 5 44 53 5 52 5 16 52 44 53 5 48 55154 5 17 48 519 519 4571018545 13 48 5 17 48 55154 54 44 53 52022 52022 551 551 51652 5114852 5114852 51652 55154 5 49 52
- 7. OUT OUT OUT OUT OUT BI BI BI BI BI BI BI BI OUT BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT PPN0_ALE PPN0_CEN0 PPN0_CEN1 PPN0_CLE PPN0_DQS PPN0_IO0 PPN0_IO1 PPN0_IO2 PPN0_IO3 PPN0_IO4 PPN0_IO5 PPN0_IO6 PPN0_IO7 PPN0_REN PPN0_VREF PPN0_WEN PPN0_ZQ PPN1_ALE PPN1_CEN0 PPN1_CEN1 PPN1_CLE PPN1_IO0 PPN1_IO1 PPN1_IO2 PPN1_IO3 PPN1_IO4 PPN1_IO5 PPN1_IO6 PPN1_REN PPN1_VREF PPN1_WEN PPN1_ZQ PPN1_DQS PPN1_IO7 SYM 4OF 13 VSS VSS SYM 11 OF 13 VSSVSS SYM 12 OF 13 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT VDDIO18_GRP3 1252 12 12 12 12 12 12 12 1253 12 12 12 12 100K 1/32W 1% MF 01005 R0831 MF R0832 100K 1% 1/32W 01005 12 52 12 12 12 12 12 12 12 12 1253 12 12 12 12 12 10% 0.01UF X5R 01005 6.3V C0860 C0861 10% 0.01UF X5R 01005 6.3V R0860 50K MF 1/32W 01005 1% R0861 50K MF 1/32W 1% 01005 U0652 POP-1GB-DDR H6P FCMSP OMIT CRITICAL 01005 R0870 1% 240 1/32W MF 01005 R0871 1% 240 MF 1/32W FCMSP POP-1GB-DDR H6P U0652 OMIT CRITICAL FCMSP POP-1GB-DDR H6P U0652 OMIT CRITICAL SYNC_DATE=04/18/2011SYNC_MASTER=N/A SOC: NAND NC_PPN1_CEN1NC_PPN0_CEN1 FMI1_CE0_L PPVREF_FMI_SOC FMI0_AD<4> FMI0_AD<0> FMI0_CE0_L FMI0_WE_L FMI0_AD<7> FMI0_AD<6> FMI0_AD<5> FMI0_AD<2> FMI0_AD<1> FMI0_DQS FMI0_ALE FMI1_AD<1> FMI1_AD<0> FMI1_AD<2> FMI1_AD<4> FMI1_AD<3> FMI1_AD<7> FMI1_AD<6> FMI1_AD<5> FMI1_CLE FMI1_ALE FMI1_DQS =PP1V8_NAND_SOC FMI0_ZQ FMI1_ZQ FMI1_WE_L FMI1_RE_LFMI0_RE_L FMI0_CLE FMI0_AD<3> =PP1V8_NAND_SOC 051-0886 A.0.0 8 OF 121 6 OF 54 1 2 1 2 2 1 2 1 1 2 1 2 A31 G32 H31 B31 D34 B32 C32 C33 C34 F32 F33 F34 G34 D33 D31 A32 E33 N34 R32 P32 P31 M34 M33 L32 M32 K32 J32 H33 L31 N31 N32 K33 L34 H34 1 2 1 2 A11 A1 AA3 AF29 AJ30 A3 A4 A5 A7 A9 A13 A14 A16 A18 A25 A28 A30 A33 A34 AA1 AA2 AA4 AA8 AA10 AA12 AA14 AA16 AA18 AA22 AA24 AA26 AA28 AA30 AB5 AB7 AB9 AB11 AB15 AB17 AB19 AB21 AB23 AB25 AB27 AB29 AB32 AC4 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AC24 AC26 AC28 AC30 AC34 AD2 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD21 AD23 AD25 AD29 AD32 AE3 AE8 AE10 AE12 AE16 AE18 AE22 AE24 AE26 AE28 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF23 AF32 AG2 AG8 AG10 AG12 AG14 AG16 AG18 AG20 AG22 AG24 AG26 AG28 AG30 AH5 AH7 AH9 AH11 AH13 AH15 AH17 AH19 AH21 AH23 AH25 AH27 AH29 AH32 AJ1 AJ3 AJ8 AJ10 AJ12 AJ14 AJ16 AJ18 AJ22 AJ24 AJ26 AK5 AK7 AK9 AK11 AK13 AK15 AK17 AK19 AK21 AK23 AK27 AK29 AK32 AL3 AL6 AL8 AL10 AL12 AL14 AL16 AL18 AL20 AL22 AL24 AL26 AL28 AL30 AM4 AM7 AM18 AM30 AN2 AN5 AN7 AB6 AM9 AM11 AM13 AN16 AM15 AN19 AN20 AN21 AN22 AN23 AN24 AJ28 A2 AB13 AE14 AN31 AP25 AP26 E10 E11 E12 G28 G26 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G1 F31 F30 F26 F15 F14 F13 F12 F10 F9 F8 F7 F6 F5 F4 F3 F2 E34 E32 E31 E22 E21 E20 E19 E18 E15 E14 E13 E8 E7 E5 E4 E3 E1 D22 D21 D20 D19 D18 D17 D15 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C31 C29 C27 C26 C23 C22 C19 C18 C17 C16 C15 C13 C11 C10 C9 C7 C6 C5 C3 C2 C1 B34 B33 B30 B28 B25 B19 B18 B17 B16 B15 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B2 B1 AV34 AV33 AV20 AV18 AV16 AV14 AV11 AV9 AV2 AV1 AU34 AU33 AU21 AU18 AU16 AU11 AU2 AU1 AT32 AT31 AT30 AT29 AT28 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 AT6 AT4 AT1 AR32 AR20 AR17 AR15 AR12 AR8 AR3 AP28 AP27 AP24 AN33 AN32 AR29 AR28 AR25 AR24 AR22 AR21 E9 C12 AP21 AP20 AP6 AN34 AP32 AR23 E6 C24 AP30 AP31 D32 D16 AP29 6 54 654
- 8. OUT OUT OUT BI IN IN OUT OUT OUT OUT BI OUT OUT OUT IN IN IN IN DP_PAD_AUXN DP_PAD_AUXP DP_PAD_AVDD_AUX DP_PAD_AVDD0 DP_PAD_AVDD1 DP_PAD_AVDD2 DP_PAD_AVDD3 DP_PAD_AVDDP0 DP_PAD_AVDDX DP_PAD_AVSS_AUX DP_PAD_AVSS0 DP_PAD_AVSS1 DP_PAD_AVSS2 DP_PAD_AVSS3 DP_PAD_AVSSP0 DP_PAD_AVSSX DP_PAD_DC_TP DP_PAD_DVDD DP_PAD_DVSS DP_PAD_R_BIAS DP_PAD_TX0N DP_PAD_TX0P DP_PAD_TX1N DP_PAD_TX1P DP_PAD_TX2N DP_PAD_TX2P DP_PAD_TX3N DP_PAD_TX3P EDP_HPD SYM 6 OF13 MIPI0C_DPDATA0 SENSOR1_RST SENSOR1_CLK MIPI1C_DPDATA0 SENSOR0_RST SENSOR0_ISTRB SENSOR0_CLK MIPI1D_VREG_0P4V MIPI1D_VDD18 MIPI1C_DPDATA1 MIPI1C_DPCLK MIPI1C_DNDATA1 MIPI1C_DNDATA0 MIPI1C_DNCLK MIPI0D_VREG_0P4V MIPI0D_VDD18 MIPI0D_DPCLK MIPI0D_DNCLK MIPI0C_DPDATA2 MIPI0C_DPDATA1 MIPI0C_DNDATA2 MIPI0C_DNDATA1 MIPI_VSS ISP0_SDA ISP0_SCL ISP1_SCL MIPI0C_DPDATA3 MIPI0C_DNDATA3 MIPI0C_DPCLK MIPI0D_DNDATA3 MIPI0D_DPDATA3 MIPI0D_DNDATA2 MIPI0D_DPDATA2 MIPI0D_DNDATA1 MIPI0D_DPDATA1 MIPI0C_DNCLK MIPI0D_DPDATA0 MIPI0D_DNDATA0 MIPI_VDD10 SENSOR1_ISTRB MIPI0C_DNDATA0 ISP1_SDA SENSOR0_XSHUTDOWN SENSOR1_XSHUTDOWN SYM 5 OF 13 OUT OUT OUT OUT OUT OUT IN BI BI OUT OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (2MA) (2MA) (55MA) VDDIO18_GRP1 VDDIO18_GRP1 MIPI_VDD10 (50MA) (50MA) (1MA) (50MA) (14MA) (50MA) VDDIO18_GRP3 (14MA) (10MA) DISPLAYPORT 20 52 20 52 20 52 20 52 20 53 20 53 R0940 49.9 01005 01005 5% 2.2K 1/32W MF R0932 1/32W R0933 01005 5% 2.2K MF 20 53 20 53 R0941 01005 100 23 52 23 52 01005 5% 2.2K 1/32W MF R0931 01005 2.2K 5% 1/32W MF R0930 23 52 23 52 2353 2353 2353 2353 2353 2353 CRITICAL OMIT U0652 FCMSP POP-1GB-DDR H6P C0962 20% 0.1UF X5R-CERM 6.3V 01005 20% 0204 1UF 4V X6S C0930 CRITICAL OMIT U0652 POP-1GB-DDR H6P FCMSP C0957 1.0UF 0201-1 6.3V X5R 20% 18 53 18 53 18 53 18 53 18 53 18 53 18 18 18 18 53 18 53 R0900 01005 MF 1/32W 4.99K 1% NOSTUFF 01005 6.3V X5R 0.01UF 10% C0950 C0958 01005 16V NP0-C0G-CERM 8.2PF +/-0.5PF 1/32W 0% 0.00 MF R0901 01005 C0951 16V 01005 5% 56PF NP0-C0G C0952 01005 16V NP0-C0G-CERM 8.2PF +/-0.5PF 01005 NP0-C0G C0953 56PF 5% 16V 0201 20% X5R 6.3V C0954 0.22UF C0955 0201-1 6.3V X5R 1.0UF 20% C0956 0201-1 6.3V X5R 1.0UF 20% SOC: DP,MIPI SYNC_MASTER=MLB SYNC_DATE=05/04/2012 =PP1V8_MIPI_SOC NC_MIPI1D_VREG NC_MIPI0D_VREG NC_SENSOR1_XSHUTDOWN NC_SENSOR1_ISTRB NC_SENSOR0_ISTRB NC_SENSOR0_XSHUTDOWN NC_MIPI0C_CAM_REAR_DATA_P2 NC_MIPI0C_CAM_REAR_DATA_N2 MIPI0C_CAM_REAR_DATA_P<0> EDP_DATA_P<1> PP1V8_EDP_AVDD_AUX =PP1V8_SOC ISP0_CAM_REAR_SCL ISP0_CAM_REAR_SDA ISP0_CAM_REAR_CLK ISP1_CAM_FRONT_CLK_R MIPI1C_CAM_FRONT_DATA_P<0> ISP0_CAM_REAR_CLK_R NC_MIPI1C_CAM_FRONT_DATA_P1 MIPI1C_CAM_FRONT_CLK_P NC_MIPI1C_CAM_FRONT_DATA_N1 MIPI1C_CAM_FRONT_DATA_N<0> MIPI1C_CAM_FRONT_CLK_N NC_MIPI0D_DPCLK NC_MIPI0D_DNCLK MIPI0C_CAM_REAR_DATA_P<1> MIPI0C_CAM_REAR_DATA_N<1> NC_MIPI0C_CAM_REAR_DATA_P3 NC_MIPI0C_CAM_REAR_DATA_N3 MIPI0C_CAM_REAR_CLK_P NC_MIPI0D_DNDATA3 NC_MIPI0D_DPDATA3 NC_MIPI0D_DNDATA2 NC_MIPI0D_DPDATA2 NC_MIPI0D_DNDATA1 NC_MIPI0D_DPDATA1 MIPI0C_CAM_REAR_CLK_N NC_MIPI0D_DPDATA0 NC_MIPI0D_DNDATA0 MIPI0C_CAM_REAR_DATA_N<0> =PP1V0_MIPI_SOC =PP1V8_EDP_SOC SOC_EDP_R_BIAS EDP_AUX_N EDP_AUX_P TP_EDP_PAD_DC_TP EDP_DATA_N<0> EDP_DATA_P<0> EDP_DATA_N<1> EDP_DATA_N<2> EDP_DATA_P<2> EDP_DATA_N<3> EDP_DATA_P<3> EDP_HPD ISP1_CAM_FRONT_SDA ISP1_CAM_FRONT_SCL ISP0_CAM_REAR_SHUTDOWN_L ISP1_CAM_FRONT_CLK ISP1_CAM_FRONT_SHUTDOWN_L =PP1V0_EDP_PAD_DVDD_SOC 051-0886 A.0.0 9 OF 121 7 OF 54 1 2 1 2 1 2 1 2 1 2 1 2 B20 A20 F18 F19 F20 F21 F22 G18 F17 G17 H19 G19 G20 G21 H18 H17 E16 F16 G16 E17 B21 A21 B22 A22 B23 A23 B24 A24 D30 2 1 2 1 AU27 AT9 AU9 AT33 AN28 AT8 AN10 AV8 AR30 AR31 AP33 AR33 AP34 AT34 AR34 AR27 AR26 AU30 AV30 AU24 AU26 AV24 AV26 AM28 AM27 AM26 AM25AN29 AV7 AT7 AU8 AU23 AV23 AU25 AV28 AU28 AV29 AU29 AV31 AU31 AV25 AU32 AV32 AN25 AN26 AN27 AM29 AL25 AR10 AV27 AP9 AR9 AP10 2 1 1 2 2 1 2 1 1 2 2 1 2 1 2 1 2 1 2 1 2 1 54 4 5 10 18 54 54 54 54
- 9. DDR1_VREF_CA DDR0_VREF_CA DDR1_RREF_DQ VSS DDR0_CKEIN DDR0_VDD_CKE DDR1_RREF_CA DDR0_RREF_CA DDR0_RREF_DQ DDR0_VREF_DQ DDR1_VREF_DQ VDDCA VDD2 VDD1 VDDQ DDR1_VDD_CKE DDR1_CKEIN SYM 7 OF13 VDDIOD_DDR1CA VDDIOD_DDR0CA VDDIO18_GRP4 VSS VDDIO18_GRP2 VDDIO18_GRP1 VDDIOD_DDRDQ VDDIO18_GRP3 SYM 9 OF 13 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (DDR IMPEDANCE CONTROL) ON 5/6/12, BY MANU G NOTE: CKEIN CONFIRMED 1.8V TOLERANT CAPS FOR VDDIOD ARE SHARED WITH VDDQ (45MA) (500MA) SHARED WITH VDDIOD) (CURRENT CONSUMPTION (CURRENT CONSUMPTION SHARED WITH VDDIOD) (<1MA) (<1MA) (1000MA) (20MA) (31MA) (2MA) (65MA) (GPIO,UART,SPI,I2C) (SENSOR,SOCHOT,PMU) CAPS FOR VDDIO18_X ARE SHARED WITH VDDIODX NOSTUFF 0.01UF 10% 6.3V C1056 X5R 01005 R1056 01005 1.00K MF 1% 1/32W R1055 01005 1/32W MF 1% 1.00K X5R 6.3V 01005 NOSTUFF C1054 0.01UF 10% R1053 01005 MF 1% 1.00K 1/32W R1054 01005 1% 1/32W 1.00K MF 0204 1UF 20% 4V X6S C1007 1UF 0204 20% 4V X6S C1006 R1031 MF 01005 240 1% 1/32W 01005 MF R1001 240 1/32W 1% 01005 0.1UF C1000 20% 6.3V X5R-CERM C1009 0610 4V 4.3UF X5R-CERM 20% 20% 4V X7S 0204 0.47UF C1004 20% 4V X5R-CERM 0610 4.3UF C1015 0610 4V 20% X5R-CERM 4.3UF C1027 OMIT CRITICAL U0652 H6P POP-1GB-DDR FCMSP 4V 0204 20% X6S 1UF C1029 4V 0204 X7S 20% 0.47UF C1026 X6S 1UF 4V 0204 20% C1028 20% 0.47UF X7S 0204 4V C1031 X6S 0204 1UF 20% 4V C1071 20% 4V X7S 0.47UF 0204 C1073 402 4.7UF X5R 6.3V 20% C1070 X6S 4V 20% 1UF 0204 C1072 H6P POP-1GB-DDR FCMSP OMIT CRITICAL U0652 0201 FL1000 1KOHM-25%-0.2A X5R-CERM 10V 20% 1.0UF 0201-1 C1042 01005 MF R1000 240 1/32W 1% R1030 MF 01005 240 1% 1/32W NOSTUFF X5R 10% 01005 0.01UF 6.3V C1002 R1005 01005 1/32W MF 2.21K 1% R1006 01005 MF 2.21K 1% 1/32W NOSTUFF 6.3V C1052 0.01UF X5R 10% 01005 01005 MF 2.21K 1% 1/32W R1051 R1052 01005 MF 1/32W 1% 2.21K SOC: SRAM, IO PWRS SYNC_MASTER=N/A SYNC_DATE=04/18/2011 DDR0_CA_ZQ DDR0_DQ_ZQ DDR1_CA_ZQ =PP1V2_S2R_DDR_SOC PPVREF_DDR1_DQ MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0.6V VOLTAGE=0.6V MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM MAX_NECK_LENGTH=3 MM PPVREF_DDR1_CA VOLTAGE=0.6V MIN_LINE_WIDTH=0.3MM MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2MM PPVREF_DDR0_DQ MIN_LINE_WIDTH=0.3MM MAX_NECK_LENGTH=3 MM VOLTAGE=0.6V PPVREF_DDR0_CA =PP1V2_VDDQ_DDR =PP1V2_S2R_DDR =PP1V2_VDDQ_DDR =PP1V2_S2R_DDR PPVREF_DDR1_DQ PPVREF_DDR0_DQ =PP1V2_VDDQ_DDR =PP1V8_S2R_DDR RESET_SOC_L =PP1V8_VDDIO18_SOC =PP1V2_VDDIOD_SOC PP1V8_XTAL PPVREF_DDR1_CA =PP1V2_S2R_DDR DDR1_DQ_ZQ PPVREF_DDR0_CA 051-0886 A.0.0 10 OF 121 8 OF 54 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.15 MM NET_SPACING_TYPE=PWR 2 11 2 1 2 2 1 1 2 1 2 2 1 2 1 1 2 1 2 2 1 2 1 2 1 2 1 2 1 Y33 AU17 T4 H27 K9 H25 J31 J20 G30 G31 G33 H1 H2 H3 H4 H5 H29 H32 J2 J3 J4 J5 J10 J12 J18 J22 J24 J26 J28 J30 K1 K3 K4 K7 K11 K13 K15 K17 K19 K21 K23 K25 K27 K29 K31 K34 L2 J6 J8 J14 K5 AP22 AP23 AC33 AU15 F11 D14 U4 AB34 AF34 AV12 AV15 R34 W34 AC2 AD33 C20 G2 J33 L3 P33 U2 U33 Y34 AJ2 AG33 AU10 AU14 AU22 AV17 AU20 C8 C4 C14 D24 AK1 AE34 B3 D25 B14 E2 J34 P34 V33 U1 AU12 AV22 AU19 A6 A8 C25 C21 J1 F1 L1 R1 N1 V1 A10 A12 A15 A17 A19 AE1 AC1 AH1 AL1 Y1 K2 J16 U31 U32 AV21 AV19 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 AG6 AE6 AC6 Y30 AM17 Y19 Y21 Y23 Y27 Y29 Y32 AM8 AM12 Y17 Y15 Y13 Y9 Y5 Y4 Y2 W33 W28 W26 W24 W22 W20 W18 W16 W12 W8 W5 W3 V34 V32 V30 V27 V25 V15 V13 V9 V7 V5 V4 V3 V2 U34 U30 V29 U29 T29 R29 AM24 AM23 AM22 AM21 AM20 Y6 W10 W14 U6 T6 G29 G24 P30 H30 K30 M30 W2 T11 T9 T7 V23 V21 V19 V17 U22 U20 U18 U14 U12 U10 U8 U5 U3 T34 T33 T32 T31 T30 T27 T25 T23 T21 T19 T17 T15 T13 T5 T3 T2 T1 R33 AH30 AD30 AM19 AM10 AH6 AD6 V11 Y3 Y7 Y11 AA6 H10 H11 H12 H13 H14 H15 M6 N6 P6 R6 V6 W6 AM14 AM16 H9 W4 W1 U28 U26 H6 H7 H8 U24 G27 G25 AJ6 AE30 21 2 1 1 2 1 2 2 1 1 2 1 2 2 1 1 2 1 2 54 8 8 8 8 854 854 854 854 8 8 854 54 41011244852 954 54 52 8 854 8
- 10. VDD_SENSE VDDVDD SYM 10 OF13 SYM 8 OF 13 VDD_ANA_TMPSADC0 VDD_ANA_TMPSADC1 VDD_ANA_TMPSADC2 VDD_ANA_TMPSADC3 VDD_SRAM_SOC VSS VDD_SRAM_CPU VDD_GPUVDD_CPU VDD_GPU_SENSE VDD_SENSE_CPU SYM 13 OF 13 Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (VDD BALLS = VDD_SOC PWR DOMAIN) 7,500MA FOR G3 GPU @125C @1.1V/1.2GHZ 10,800MA FOR CPU0+1 @1.1V @125C (2.5MA) (2.5MA) (2.5MA) (2.5MA) @125C @1.0V (1500MA) 1,500MA FOR CYCLONE + M$ SRAM (THERMAL VIRUS) @1.0V @125C 2,500MA FOR VDD_SOC POP-1GB-DDR H6P FCMSP U0652 OMIT CRITICAL 20% 4V 0610 4.3UF X5R-CERM C1148 20% C1151 1UF 4V X6S 0204 4V 0.47UF 20% C1153 X7S 0204 0204 X6S C1150 1UF 20% 4V X7S 4V 20% 0204 C1152 0.47UF FCMSP POP-1GB-DDR H6P U0652 OMIT CRITICAL C1160 20% 0.1UF 01005 6.3V X5R-CERM OMIT POP-1GB-DDR H6P U0652 CRITICAL FCMSP CRITICAL C1103 4V X5R-CERM 4.3UF 0610 20% C1102 X5R-CERM 4.3UF 0610 20% 4V CRITICAL C1101 4V 20% X5R-CERM 4.3UF 0610 CRITICALCRITICAL C1100 0610 20% 4V X5R-CERM 4.3UF C1109 CRITICAL 0204 X6S 4V 20% 1UF C1114 +/-0.5PF 8.2PF 01005 NP0-C0G-CERM 16V C1108 CRITICAL 1UF 20% 4V X6S 0204 C1107 CRITICAL 1UF 20% 4V X6S 0204 0201 0.22UF 20% X5R 6.3V C1113 C1106 20% 1UF 4V 0204 X6S CRITICAL 4V 20% 1UF C1105 0204 X6S CRITICAL 0201 0.22UF 20% X5R 6.3V C1112C1111 0.47UF 20% 0204 X7S 4V CRITICAL 0204 X6S 20% C1104 1UF 4V CRITICAL 0204 20% 0.47UF C1110 CRITICAL X7S 4V C1118 CRITICAL 4V X5R-CERM 0610 4.3UF 20% C1117 CRITICAL 4.3UF 4V 20% 0610 X5R-CERM C1122 4V 20% X5R-CERM 4.3UF 0610 CRITICAL C1126 20% 1UF 4V 0204 X6S CRITICAL C1121 CRITICAL 4V 20% X5R-CERM 4.3UF 0610 C1125 1UF 20% 4V X6S 0204 CRITICAL C1116 20% X5R 4V 0402 15UF C1115 20% X5R 4V 0402 15UF 4.3UF 0610 X5R-CERM 20% 4V CRITICAL C1120 C1124 20% 1UF 4V X6S 0204 CRITICAL 4.3UF X5R-CERM 0610 20% 4V CRITICAL C1119 C1123 20% 1UF 4V 0204 X6S CRITICAL C1130 20% 1UF 4V X6S 0204 CRITICAL C1129 20% 1UF 4V X6S 0204 CRITICAL C1134 01005 8.2PF NP0-C0G-CERM 16V +/-0.5PF 0201 0.22UF 20% C1133 6.3V X5R C1128 20% 1UF 4V 0204 X6S CRITICAL C1127 1UF 20% 4V 0204 X6S CRITICAL C1132 CRITICAL 0204 X6S 4V 20% 1UF C1131 CRITICAL 0204 X6S 4V 20% 1UF C1138 4V 0204 0.47UF 20% CRITICAL X7S 0.47UF 4V 20% 0204 CRITICAL C1142 X7S C1137 4V 20% 0204 0.47UF CRITICAL X7S CRITICAL 4V 20% 0204 C1141 0.47UF X7S 0201 6.3V X5R C1145 0.22UF 20% C1136 20% 0204 4V 0.47UF CRITICAL X7S C1140 CRITICAL 4V 0204 0.47UF 20% X7S 20% CRITICAL C1135 0.47UF 4V X7S 0204 C1139 CRITICAL 20% 0.47UF 0204 4V X7S 01005 20% 6.3V X5R 0.22UF C1144 01005 20% 6.3V 0.22UF X5R C1143 CRITICAL C1187 X7S 4V 20% 0.47UF 0204 CRITICAL C1186 20% 4V 0204 0.47UF X7S CRITICAL C1185 0.47UF 20% 0204 X7S 4V CRITICAL C1184 20% 0204 X7S 4V 0.47UF CRITICAL C1183 0204 4V 1UF 20% X6S CRITICAL C1182 4V 1UF 20% X6S 0204 C1194 8.2PF +/-0.5PF 01005 NP0-C0G-CERM 16V 0.22UF X5R 6.3V 20% 01005 C1193C1192 01005 20% 6.3V X5R 0.22UF C1191 01005 20% 6.3V X5R 0.22UF C1190 01005 20% 6.3V X5R 0.22UF CRITICAL 20% 1UF 4V 0204 X6S C1181 CRITICAL 20% 0204 1UF 4V X6S C1180 CRITICAL 20% 1UF 4V X6S C1179 0204 CRITICAL X6S 4V 20% 1UF 0204 C1178 CRITICAL 0610 4V 20% X5R-CERM 4.3UF C1177 CRITICAL 4V X5R-CERM 4.3UF 0610 20% C1176 CRITICAL 20% X5R-CERM 4.3UF 0610 4V C1175 CRITICAL 4.3UF 0610 4V 20% X5R-CERM C1174 CRITICAL 4V 20% 4.3UF 0610 X5R-CERM C1173 CRITICAL X5R-CERM 4V 20% 4.3UF 0610 C1172 15UF 0402 4V X5R 20% C1171 15UF 0402 4V 20% X5R C1170 0.47UF 0204 4V X7S 20% C1189 CRITICAL 0204 4V X7S 20% 0.47UF CRITICAL C1188 SOC: VDD, SRAM, CPU, GPU PWRS SYNC_MASTER=N/A SYNC_DATE=04/18/2011 =PPVDD_CPU =PPVDD_GPU PPVDD_CPU_SOC_SENSE PPVDD_GPU_SOC_SENSE =PP1V8_VDDIO18_SOC =PPVDD_SRAM_SOC PPVDD_SOC_SOC_SENSE =PPVDD_SOC 051-0886 A.0.0 11 OF 121 9 OF 54 P20 P22 K10 K8 K18 K16 K14 K12 K6 J29 J27 J23 J21 J19 J17 J15 J13 J11 AK6 AK20 R7 V31 R17 U23 R25 V22 J25 N27 N17 N15 N13 AN11 Y20 Y18 Y16 W19 W17 W7 V28 V26 V24 V20 V18 V16 V14 U27 U25 U21 U19 U17 U7 T28 T26 T24 T22 T20 T18 T16 T14 R27 R23 R21 R19 R15 R13 P28 P24 P18 P16 P14 P12 P10 P8 N29 N25 N23 N21 N19 N11 N9 N7 M26 M24 M22 M20 M18 M16 M14 M12 M10 L27 L25 L23 L21 L19 L17 L15 L13 L11 L9 L7 K28 J9 J7 H28 H24 AN9 AL23 AK30 AN18 AF30 AF20 AF6 AE21 AN15 AD20 AN13 AB20 AB14 AA17 K20 AA7 U15 P26 M28 L29 AA19 R11 R9 K26 K24 K22 H26 AH20 AB30 M8 2 1 2 1 2 1 2 1 2 1 R28 R30 R31 AJ20 AA20 AB4 H22 AA9 AA11 AA13 AA15 AB8 T10 T12 U11 L4 L5 L6 L8 L10 L12 L14 L16 L18 L20 L22 L24 L26 L28 L30 L33 M1 M2 M3 M4 M5 M7 M9 M11 M13 M15 M17 M19 M21 N3 N5 N8 N10 N12 N14 N16 N18 N20 N22 N24 N26 N28 N30 P1 P2 P3 P4 P7 P9 P11 P13 P17 P19 P21 P23 P25 P27 P29 R2 R3 R4 R5 R8 R10 R16 R18 R24 R26 T8 U9 W13 V10 V8 U13 W15 W11 W9 V12 Y8 AD24 AD26 AD28 AE23 AE25 AE27 AF24 AF26 AF28 AK25 Y25 M23 M25 M27 M29 M31 N2 N4 N33 P5 P15 R12 R22 R14 R20 Y14 Y12 Y10 2 1 AL29 AL9 AL7 AL19 AC29 AD22 AL13 AL11 AK8 AK14 AK10 AJ9 AJ19 AJ17 AJ15 AH8 AH16 AH12 AG13 AB18 AF8 AF18 AF10 AE9 AE7 AE19 AE17 AB16 AE13 AE11 AD8 AD18 AD16 AD14 AD12 AD10 AB10 AB26 AB24 Y28 Y26 Y24 Y22 W27 W25 W21 AA29 AL27 AL21 AK28 AJ29 AJ25 AJ23 AA27 AJ21 AH26 AH24 AH22 AG21 AB12 AC9 AC19 AF27 AF25 AC27 AC25 AB28 AC23 AC21 AE15 AG9 AG7 AC11 AA25 AA23 AC17 AC15 AC13 AF12 AF14 AF16 AG23 AG27 AF22 AE29 AD27 AK12 AJ7 AJ13 AH18 AH14 AH10 AG15 AC7 AA21 AB22 AG11 AG17 AJ11 AK16 AK18 AL15 AL17 AA5 AM6 AN30 AG19 AG25 AG29 AH28 AJ27 AK22 AK24 AK26 W29 W23 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 54 54 53 854 54 53 54
- 11. OUT CLK RESET DETGND GND GND GND GND GND I/O DETECT VCC VPP OUT BIIN IN SCHEMATIC DEFINEDCONSTRAINTS (YES/NO) CKPLUS RULE EXCEPTIONS TABLE_DASHBOARD_INFO REQUIRED Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT EVT101 BOARD_ID[1] MLB_C SIM CARD SPI0 TEST MODE MLB BOARD REVISION S/W READ FLOW 2. DISABLE PU AND ENABLE PD 1. SET GPIO AS INPUT BOARD_ID[0] ID[3-0] SYSTEM 1. SET GPIO AS INPUT BOOT_CONFIG[3-0] 2. DISABLE PU AND ENABLE PD BOOT_CONFIG[3] (GPIO29) S/W READ FLOW BOOT_CONFIG[0] (GPIO18) BOOT_CONFIG[2] (GPIO28) BOARD ID 3. READ BOARD_ID[3] BOARD_ID[2] BRD_REV[2-0] 3. READ 1. SET GPIO AS INPUT S/W READ FLOW 3. READ BOOT_CONFIG[1] (GPIO25) BOOT CONFIG ID 1010 J85 AP 1011 J85 DEV 1100 J86 AP 1101 J86 DEV 1110 J87 AP 1111 J87 DEV MLB_B 0000 0010 JTAG SPI0 0011 0001 2. ENABLE PU AND DISABLE PD NAND <-- SELECTED NAND TEST MODE ID_J85_J87 2.2K 5% 01005 1/32W MF R1205 01005 5% MF 1/32W 2.2K R1201 NOSTUFFNOSTUFF 2.2K 1/32W 5% R1200 MF 01005 01005 5% 2.2K 1/32W MF R1203 NOSTUFF MF 1/32W 2.2K 5% R1206 ID_DEV 01005 ID_J86_J87 5% 2.2K 01005 1/32W MF R1204 R1260 5% 100 MF 1/32W 01005 01005 1/32W 2.2K 5% MF R1213 4 52 100 5% 1/32W MF 01005 R1210 01005 R1250 0% 0.00 1/32W MF NOSTUFF SIM-CARD-X113-X223 F-ST-SM CELL J3000 24 28 52 24 28 52242852 242852 C3002 CELL CERM 6.3V 5% 100PF 01005 01005 MF 1/32W 1% CELL 15.00K R3000 C3001 0402 X5R 10% 16V 1.0UF CELL 01005 MF 1/32W 5% 2.2K R1202 1/32W 5% 100 R1211 01005 MF NOSTUFF 2.2K 01005 5% MF R1207 1/32W 2.2K MF 5% R1208 01005 1/32W NOSTUFF 5% 2.2K 01005 1/32W MF R1209 NO SYNC_DATE=04/11/2011SYNC_MASTER=N/A SOC: MISC & ALIASES GPIO_BOOT_CONFIG2 SIMCRD_CLK_CONN SIMCRD_RST_CONN PP_LDO6_RUIM_1V8 NC_J3000_5 SIMCRD_IO_CONN SIM_TRAY_DETECT MAKE_BASE=TRUE WDOG_SOC WDOG_SOC2PMU_RESET_IN MAKE_BASE=TRUE I2S3_BT2SOC_DATA I2S4_BT2SOC_DATA I2S3_SOC2BT_DATA MAKE_BASE=TRUE I2S4_SOC2BT_DATA I2S3_SOC2BT_BCLK MAKE_BASE=TRUE I2S4_SOC2BT_BCLK I2S3_SOC2BT_LRCK MAKE_BASE=TRUE I2S4_SOC2BT_LRCK RESET_SOC_LJTAG_SOC_TRST_L JTAG_SOC_SEL GPIO_BOARD_ID1 GPIO_BOARD_REV1 SOC_FAST_SCAN_CLK GPIO_BOARD_ID2 GPIO_BOARD_REV2 GPIO_BOOT_CONFIG3 GPIO_BOARD_REV0 GPIO_BOARD_ID3 SOC_HOLD_RESET SOC_TESTMODE =PP1V8_SOC =PP1V8_SOC GPIO_BOARD_ID0 GPIO_BOOT_CONFIG0 GPIO_BOOT_CONFIG1 051-0886 A.0.0 12 OF 121 10 OF 54 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 3 2 8 11 10 12 4 9 6 7 1 5 2 1 1 2 2 1 1 2 1 2 1 2 1 2 1 2 5 24252752 4 48 5 44 5 44 5 44 5 44 4 8 11 24 48 52452 5 5 4 5 5 5 5 5 4 4 52 457101854 457101854 5 5 5
- 12. OUT IN OUT OUT OUT DIG_DP DVSS DVSS DVSS DIG_DN USB1_DP USB1_DN USB0_DP UART0_TX USB0_DN UART1_TX UART0_RX UART2_TX UART1_RX JTAG_CLK UART2_RX JTAG_DIO ACC_PWR VDD_3V0 VDD_1V8 P_IN ACC1 ACC2 DP1 DN1 DP2 DN2 CON_DET_L HOST_RESET SWITCH_EN SDA INT SCL BYPASS POW_GATE_EN* BRICK_ID Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 343S0658 = TRISTAR 2, A1 TRISTAR 343S0614 = TRISTAR 1 TO USB BB MUX (T’S OFF TO H4A UART4) AP USB ACCESSORY UART AP DEBUG UART TRISTAR BYPASS FOR 3V LDO BB DEBUG UART 343S0639 = TRISTAR 2, A0 998-5855 = TRISTAR 2, TC 46 4 8 10 24 48 52 48 CRITICAL C1303 1.0UF X5R-CERM 10V 20% 0201-1 0.1UF 6.3V C1302 10% CERM-X5R 0201 0.1UF X5R-CERM C1300 01005 6.3V 20% 0.1UF 20% 6.3V X5R-CERM 01005 C1301 5 48 +/-0.5PF 16V 01005 8.2PF C1321 NP0-C0G-CERM C1320 16V 01005 NP0-C0G-CERM 8.2PF +/-0.5PF C1322 16V NP0-C0G-CERM 01005 +/-0.5PF 8.2PF R1370 MF 0.00 0% 1/32W 01005 15 C1360 10V 20% X5R-CERM 1.0UF 0201-1 CRITICAL C1361 10% 1UF 402 X5R 25V CBTL1610A1UK U1300 CRITICAL WLCSP SYNC_DATE=N/ASYNC_MASTER=N/A IO: TRISTAR MIKEY_TS_P MIKEY_TS_N USB_BB_P USB_BB_N USB_SOC_P UART6_TS_ACC_TXD USB_SOC_N UART0_SOC_TXD UART6_TS_ACC_RXD UART3_BB2SOC_TX UART0_SOC_RXD JTAG_SOC_TCK UART3_SOC2BB_TX JTAG_SOC_TMS =PP3V0_S2R_TRISTAR PPVBUS_PROT PPOUT_E75_ACC_ID1 PPOUT_E75_ACC_ID2 E75_DPAIR1_P E75_DPAIR1_N E75_DPAIR2_P E75_DPAIR2_N TS_CON_DET_L TS2PMU_RESET_IN RESET_SOC_L I2C0_SDA_1V8 GPIO_TS2SOC2PMU_INT I2C0_SCL_1V8 TRISTAR_BYPASS NET_SPACING_TYPE=PWR VOLTAGE=3V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM MAX_NECK_LENGTH=0.5MM OVP_SW_EN_L PMU_USB_BRICKID L81_MBUS_REF =PP1V8_S2R_TRISTAR =PP3V3_ACC 051-0886 A.0.0 13 OF 121 11 OF 54 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 2 1 C3 F5 C1 A6 C4 A1 B1 A3 E2 B3 F2 E1 D2 F1 A5 D1 B5 D5 F4 F3 F6 C5 E5 A2 B2 A4 B4 E3 B6 E4 D3 C6 D4 E6 D6 C2 1552 1552 245253 245253 452 552 452 552 552 5242852 552 452 5242852 452 54 46 52 43 43 43 43 43 43 43 5 48 52 5 48 52 48 54 54
- 13. IN IN IN IN IN IN IN IN IN IN IN IN BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI IO0-1 IO7-1 IO6-1 IO3-1 IO4-1 IO5-1 IO1-1 IO2-1 IO7-0 IO5-0 IO6-0 IO4-0 IO2-0 IO3-0 IO1-0 IO0-0 VCC CLE1 CE1* CLE0 CE0* WE0* ALE0 RE0 RE0* DQS0* R/B0* DQS0 ALE1 WE1* RE1 RE1* DQS1 DQS1* R/B1* ZQ VREF VSSQVSS VCCQ VDDI TMSC TCKC Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT ENSURE TRACE INDUCTANCE < 2NH LAYOUT NOTE FOR U1400 VDDI: C1413 2.2UF X5R-CERM 0201 20% 4V 20% C1412 15UF 4V 0402 X5R 20% C1411 15UF 4V 0402 X5R 20% C1410 4V X5R 15UF 0402 C1404 20% 4V X7S 0.47UF 0204 C1407 1UF 20% X5R 6.3V 02010204 20% C1405 X6S 4V 1UF 6 52 6 6 6 6 6 53 6 52 6 6 6 6 6 R1454 MF 1% 243 1/32W 01005 0201 20% 4V C1450 2.2UF X5R-CERM 6 6 6 653 6 6 6 6 6 6 6 6 6 6 6 6 OMIT LGA-12X17 U1400 CRITICAL XXNM-XGBX8-MLC-PPN1.5-ODP R1460 01005 1% 1/32W MF 50K R1461 01005 1% 1/32W MF 50K 6.3V 01005 C1460 X5R 0.01UF 10% 6.3V 01005 C1461 X5R 0.01UF 10% 16V 5% 01005 NP0-C0G C1491 27PF 16V 5% 01005 NP0-C0G 27PF C1490 27PF 16V 5% 01005 NP0-C0G C1492 NP0-C0G 01005 5% 16V 27PF C1494 27PF NP0-C0G 01005 5% 16V C1493 10UF 6.3V CERM-X5R 0402-2 20% C1402 20% CERM-X5R 6.3V 0402-2 10UF C1401 6.3V 20% 10UF CERM-X5R 0402-2 C1400 20% 0402-2 CERM-X5R 6.3V 10UF C1480 1UF 20% C1406 6.3V X5R 0201 SYNC_DATE=05/04/2012 NAND STORAGE SYNC_MASTER=MLB =PP3V3_NAND FMI1_AD<3> FMI1_AD<4> FMI0_AD<4> FMI0_CE0_L NC_U1400_RE0 FMI1_CE0_L FMI_ZQ_U1400 FMI0_AD<5> FMI0_RE_L PPVREF_FMI_NAND =PP1V8_NAND FMI1_AD<0> FMI1_AD<7> FMI1_AD<6> FMI1_AD<5> FMI1_AD<1> FMI0_AD<7> FMI0_AD<6> FMI0_AD<2> FMI0_AD<3> FMI0_AD<1> FMI0_AD<0> FMI1_CLE FMI0_CLE FMI0_WE_L FMI0_ALE FMI0_DQS FMI1_ALE FMI1_WE_L NC_U1400_RE1 FMI1_RE_L FMI1_DQS NC_U1400_DQS1 TP_TMSC_U1400 TP_TCKC_U1400 TP_U1400_RB0 NC_U1400_DQS0 TP_U1400_RB1 =PP1V8_NAND PPVDDI_NAND FMI1_AD<2> 051-0886 A.0.0 14 OF 121 12 OF 54 2 1 2 1 2 1 2 12 1 2 1 2 1 1 2 2 1 G1 G7 J7 N3 N5 L7 J1 L1 H6 K6 J5 L5 J3 K2 H2 G3 F2 M6 B6 C3 C5 A3 A5 E3 C1 B4 C7 F4 E5 H4 D2 E1 D4 D6 M4 K4 E7 A1 G5 OA8 OF8 G0 OE0 OD8 OC8 N7 OE8 OD0 OC0 A7 M2 L3 F6 B2 OF0 G8 N1 OB8 OB0 OA0 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 12 1 2 1 2 1 2 1 2 1 54 12 48 54 53 53 53 53 12 48 54
- 14. CAP ON S D VDD GND Apple Inc. THEINFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TOUCH SUBSYSTEM (PLUG - FLEX 998-4527) RCPT - MLB 998-4526 -> 516S1054 LAYOUT NOTE: PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION 0.38 DCR 1/32W MF R1752 0.000% 01005 J1700 503304-2010 CRITICAL F-ST-SM-1 MF R1790 1/32W 1.00K 1% 01005 R1753 0.00 01005 MF 0% 1/32W NOSTUFF C1761 27PF 5% NP0-C0G 16V 01005 0201 C1702 X7R-CERM 16V 1000PF 10% X5R 10V 10% 1UF 402 C1701 27PF 01005 16V NP0-C0G 5% C1700 L1700 0201 240OHM-350MA 1000PF 16V X7R-CERM 0201 C1705 10% C1704 0201 X5R 6.3V 20% 1UF 0201 10% 1000PF X7R-CERM C1708 16V X5R 6.3V 20% 1UF 0201 C1707 5% 27PF NP0-C0G C1703 16V 01005 240OHM-350MA 0201 L1701 0201-2 240-OHM-0.2A-0.8-OHM L1702 01005 5% 27PF NP0-C0G 16V C1706 6.3V X5R 1UF 20% 0201 C1752 CRITICAL SLG5AP302 U1700 TDFN CRITICAL C1750 0201 10% 0.1UF X5R-CERM 16V CRITICAL C1751 10% X7R 10V 4700PF 201 CRITICAL 1% 100K R1751 MF 1/32W 01005 X5R-CERM 10UF C1753 20% 0402-2 10V CRITICAL 01005 150OHM-25%-200MA-0.7DCR L1760 C1760 27PF 5% NP0-C0G 16V 01005 TOUCH: SUPPORT CKT & CONN SYNC_MASTER=N/A SYNC_DATE=06/21/2010 PP1V8_GRAPE_SW GPIO_BTN_HOME_L GPIO_BTN_HOME_FILT_LGPIO_BTN_HOME_R_L PP3V0_S2R_HALL_FILT DISPLAY_SYNC_R SPI1_GRAPE_MOSI SPI1_GRAPE_MISO GPIO_GRAPE_IRQ_L CLK_32K_SOC2CUMULUS SPI1_GRAPE_CS_L PP1V8_GRAPE_FILT GPIO_GRAPE_RST_L GPIO_BTN_HOME_FILT_L NC_PMU_GPIO_HALL_IRQ_4 PMU_GPIO_MB_HALL3_IRQ PMU_GPIO_MB_HALL2_IRQ PMU_GPIO_MB_HALL1_IRQ PP5V25_GRAPE_FILT SPI1_GRAPE_SCLK_RSPI1_GRAPE_SCLK DISPLAY_SYNC =PP3V0_S2R_HALL PP3V0_S2R_HALL_FILT VCC_MAIN_GRAPE_RAMP =PP1V8_GRAPE =PPVCC_MAIN_GRAPE =PP1V8_S2R_GRAPE =PP5V25_GRAPE PP5V25_GRAPE_FILT PP1V8_GRAPE_FILT 051-0886 A.0.0 17 OF 121 13 OF 54 1 2 13 17 24 23 19 11 15 9 7 5 1 3 18 20 12 14 16 8 10 6 4 2 22 21 1 2 1 2 2 1 2 1 2 1 2 1 21 2 1 2 1 2 1 2 1 2 1 21 21 2 1 2 1 7 2 5 3 18 2 1 2 11 2 2 1 21 2 1 52 548 13 52 1352 52 552 552 552 552 552 1352 552 13 52 48 48 48 13 52 525 5 54 13 52 54 54 54 54 13 52 13 52
- 15. Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (P/N 510S0761 - FLEX) P/N 510S0760 - MLB AUDIO_JACK_FLEX RET1 AUDIO_JACK_FLEX MIC2 AUDIO_JACK_FLEX MIC1 AUDIO_JACK_FLEX RET2 PER DAVE BREECE J1800 CRITICAL AA07A-S016VA1 F-ST-SM-COMBO 0201-2 L1800 240-OHM-0.2A-0.8-OHM C1800 NP0-C0G 16V 27PF 5% 01005 0.1UF 10% 6.3V C1801 CERM-X5R 0201 NP0-C0G 16V 27PF 5% 01005 C1802 R1850 0% 0.00 MF 1/32W 01005 NOSTUFF NP0-C0G 16V 5% C1850 01005 27PF 01005 5% 16V NP0-C0G 56PF C1821 5% 16V NP0-C0G 56PF C1820 01005 01005 C1822 56PF NP0-C0G 16V 5%5% 16V NP0-C0G 56PF 01005 C1830 AUDIO: HP FLEX CONN SYNC_DATE=03/31/2011SYNC_MASTER=N/A MIN_NECK_WIDTH=0.06 MMVOLTAGE=2.65VPP_LDO14_2V65 LAT_SW2_CTL GPIO_SOC2AJ_HS3_SHUNT_EN PP1V8_DMIC_FILT LAT_SW1_CTL CONN_HP_LEFT_FILT CONN_HP_RIGHT_FILT CONN_HP_HS3_FILT CONN_HP_HEADSET_DET_FILT CONN_HP_HS3_REF_FILT GPIO_SOC2AJ_HS4_SHUNT_EN DMIC1_FF_SCLK_FILT DMIC1_FF_SD CONN_HP_HS4_REF_FILT CONN_HP_HS4_FILT DMIC1_FF_SCLK =PP1V8_DMIC 051-0886 A.0.0 18 OF 121 14 OF 54 20 19 18 17 15 13 11 9 7 1 16 14 12 10 8 6 4 2 5 3 21 2 1 2 1 2 1 1 2 2 1 2 1 2 1 2 1 2 1 2532333940 2852 5 242852 15 15 15 15 15 5 15 15 15 15 54
- 16. IN IN IN IN IN IN IN IN IN IN IN OUT OUT IN OUT IN OUT OUT IN IN IN IN BI BI OUT OUT SYM 2 OF2 DMIC1_SCLK DMIC2_SD MCLK GND13 GND0 TSTI2 TSTI1 TSTI0 GND18 GND17 GND16 GND15 GND14 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 RESET* WAKE* INT* CDOUT CDIN CCLK XSP_SDOUT XSP_SDIN_DAC2_MUTE XSP_LRCK_FSYNC XSP_SCLK ASP_SDOUT ASP_SDIN ASP_LRCK ASP_SCLK DMIC2_SCLK DMIC1_SD CS* MBUS_REF SYM 1 OF 2 FLYP MIC4_BIAS_FILT AIN3+ AIN1- FLYN GNDA MIC1_BIAS MIC2_BIAS_FILT_IN MIC2_BIAS_FILT MIC2_BIAS AIN2+ AIN2M MIC2_BIAS_IN AIN3- MIC3_BIAS MIC3_BIAS_FILT AIN4+ AIN4- MIC4_BIAS GNDP GNDD GNDHS +VCP_FILT FILT- FILT+ LINEOUT_REF LINEOUTB LINEOUTA HPDETECT HS4_REF HS3_REF HS4 HS3 HPOUTB HPOUTA DN DP AOUT2- AOUT2+ AOUT1_M AOUT1+ GNDCP -VCP_FILT VA VCP1 VD VP0 VL VP1 VPROG_CP VPROG_MB SPEAKER_VQ AIN1+ MIC1_BIAS_FILT GNDHS FLYC VCP0 IN IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEADDIGITAL MIC TO HEADPHONE JACK TO THE HP CONNECTOR U1900 DECAPS CHANGED ON 5/24/12 PER RADAR #11485846 NOTE: PLACE R1930 & R1931 CLOSE TO U3600 MIKEY BUS FILTER PLACE L1900 TO 1905 CLOSE 14 0402 10UF CERM-X5R CRITICAL 20% 6.3V C1910 XW1900 SHORT-8L-0.25MM-SM NOSTUFF CRITICAL 20% X5R 4.7UF C1907 402 6.3V CRITICAL 4.7UF X5R 20% 402 6.3V C1908 22 010055%1/32W MF R1912 22 MF1/32W 5% 01005 R1913 14 14 5 5 22 01005MF5%1/32W R1910 MF 010055% 22R19111/32W 5 5 5 553 553 5 5 553 553 553 553 552 4852 48 C1912 X5R 6.3V 402 20% 4.7UF MF 1/20W 2.21K 1% R1901 201 0201-1 20% 1.0UF C1911 X5R 6.3V 1.00K 5% 1/32W MF 01005 NOSTUFF R1940 14 14 11 XW1902 NOSTUFF SHORT-8L-0.25MM-SM 0201 CERM-X5R 0.1UF 10%6.3V C1916 0201 CERM-X5R 0.1UF 10%6.3V C1917 SHORT-8L-0.25MM-SM XW1903 NOSTUFF R1931 5% MF 12 201 1/20W R1930 5% MF 201 1/20W 12 C1932 5% 25V 0201 NP0-CERM 100PF SIGNAL_MODEL=EMPTY C1931 5% 100PF 0201 NP0-CERM 25V NOSTUFF C1930 5% NP0-CERM 25V 100PF 0201 SIGNAL_MODEL=EMPTY 11 52 11 52 L1900 FERR-33-OHM-0.8A-0.09-OHM 0201 L1901 FERR-33-OHM-0.8A-0.09-OHM 0201 L1902 FERR-33-OHM-0.8A-0.09-OHM 0201 L1903 FERR-33-OHM-0.8A-0.09-OHM 0201 L1904 01005 120-OHM-210MA L1905 120-OHM-210MA 01005 14 14 C1990 01005 16V NP0-C0G 100PF 5% C1991 5% 100PF NP0-C0G 16V 01005 0201 R1950 1.00 1% 1/20W MF-LF 0201-1 1.0UF 20% 6.3V CRITICAL X5R C1951 X5R C1950 4.7UF CRITICAL 20% 402 6.3V 0201 R1951 1/20W 1% 1.00 MF-LF MF 1/20W 1% R1952 255K 201 C1913 0.1UF 10% 0201 X5R-CERM 10V 5% 1/20W MF 0 R1953 201 U1900 WLCSP CS42L81-CWZR-A1 CRITICAL WLCSP U1900 CS42L81-CWZR-A1 0.1UF 0201 X5R-CERM 10V C1914 10% CRITICAL X5R-CERM 4.7UF 20% 10V 0402 C1909C1904 10V X5R-CERM 0201 10% 0.1UF 20% 6.3V X5R-CERM 01005 C1915 0.1UF 20% 01005 X5R-CERM 6.3V 0.1UF C1902 0201 10% 0.1UF X5R-CERM 10V CRITICAL C1903 4.7UF CRITICAL 6.3V C1901 X5R 402 20% 4.7UF C1905 X5R 6.3V 20% 402 C1906 20% 4.7UF 6.3V 402 X5R 14 L1920 240-OHM-0.2A-0.8-OHM 0201-2 C1920 4700PF 10% 10V X7R 201 NOSTUFF R1920 01005 3.3K 1/32W 5% MF 14 SYNC_DATE=01/18/2012 AUDIO: L81 CODEC SYNC_MASTER=KAVITHA 338S1213 338S1116 RADAR:13373870 SSMC FABU1900 155S0773 155S0453 L1904,L1905 RADAR:11100717 =PP1V7_VA_VCP NO_TEST=TRUENC_MIC4_BIAS MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM CODEC_HP_HS4_REF =PP1V8_AUDIO L81_FLYP 0.15MM 0.3MM L81_FLYC 0.15MM 0.3MM GND_AUDIO_CODEC MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM PP1V7_VCP VOLTAGE=1.7V NO_TEST=TRUEAIN1P NO_TEST=TRUEAIN1N L81_MIC2_BIAS L81_MIC2_BIAS_FILT_IN HP_MIC_POS MIC1_BIAS_FILT NO_TEST=TRUE SPI2_CODEC_MISO SPI2_CODEC_MOSI SPI2_CODEC_SCLK SPI2_CODEC_CS_L L81_MBUS_REF I2S2_CODEC_XSP_DOUT L81_FILT 0.30MML81_PVCP 0.15MM GND_AUDIO_CODEC L81_NVCP 0.30MM0.15MM NO_TEST=TRUE NC_RIGHT_CH_OUT_N NO_TEST=TRUE NC_RIGHT_CH_OUT_P L81_AIN2_POS VOLTAGE=4.2V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.15MM PPVCC_VPROG_CP =PPVCC_MAIN_AUDIO GND_AUDIO_CODEC MIC4_BIAS_FILT NO_TEST=TRUE MIN_NECK_WIDTH=0.15MM PPVCC_VPROG_MB VOLTAGE=4.2V MIN_LINE_WIDTH=0.3MM L81_FLYN 0.15MM 0.3MM PPVCC_VPROG_MB_F MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.3MM VOLTAGE=4.2V 0.15MM 0.20MM GND_AUDIO_CODEC VOLTAGE=0V I2S2_CODEC_XSP_SDOUTI2S2_CODEC_XSP_DIN DMIC1_FF_SCLK DMIC1_FF_SD I2S0_CODEC_ASP_SDOUTI2S0_CODEC_ASP_DIN L81_DMIC1_FF_SD NC_DMIC2_SCLK NO_TEST=TRUE I2S0_CODEC_ASP_BCLK I2S0_CODEC_ASP_LRCK I2S0_CODEC_ASP_DOUT I2S2_CODEC_XSP_BCLK I2S2_CODEC_XSP_LRCK GPIO_CODEC_IRQ_L PMU_GPIO_CODEC_HS_INT_L I2S0_CODEC_ASP_MCK L81_DMIC1_FF_SCLK PMU_GPIO_CODEC_RST_L =PP1V8_AUDIO CODEC_MIC_BIAS_FILT MAKE_BASE=TRUE NC_MIC3_BIAS NO_TEST=TRUE NO_TEST=TRUENC_MIC1_BIAS AIN4P AIN4N MAKE_BASE=TRUE CODEC_AIN AIN3P AIN3N AIN1N AIN1P MIC1_BIAS_FILT MIC4_BIAS_FILT MIC3_BIAS_FILT L81_MIC2_BIAS_IN L81_AIN2_NEG CODEC_HP_HS3 CODEC_HP_RIGHT MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MMCODEC_HP_HS3 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MMCODEC_HP_HS4 MIN_NECK_WIDTH=0.15MMCODEC_HP_LEFT MIN_LINE_WIDTH=0.20MM L81_MBUS_P CONN_HP_HS3_FILT MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.20MM CONN_HP_RIGHT_FILT MIN_LINE_WIDTH=0.20MM CONN_HP_LEFT_FILT MIN_NECK_WIDTH=0.15MM CODEC_HP_DET_R MIN_LINE_WIDTH=0.50MM CONN_HP_HS4_FILT MIN_NECK_WIDTH=0.20MM L81_MBUS_N AIN4N NO_TEST=TRUE MIC3_BIAS_FILT NO_TEST=TRUE NO_TEST=TRUEAIN3N NO_TEST=TRUEAIN3P CONN_HP_HEADSET_DET_FILTCODEC_HP_DET NO_TEST=TRUE NC_LEFT_CH_OUT_N CODEC_HP_DET CODEC_HP_HS4 HP_MIC_NEG NO_TEST=TRUEAIN4P NO_TEST=TRUE NC_LEFT_CH_OUT_P NO_TEST=TRUE NC_CODEC_LINE_OUT_R NC_CODEC_LINE_OUT_LNO_TEST=TRUE MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM CONN_HP_HS3_REF_FILT MIN_NECK_WIDTH=0.1MM CONN_HP_HS4_REF_FILT MIN_LINE_WIDTH=0.15MM L81_MIC2_BIAS_FILT CODEC_HP_HS3_REF MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.15MM L81_MBUS_N L81_MBUS_P MIKEY_TS_P MIKEY_TS_N NC_SPEAKER_VQ 051-0886 A.0.0 19 OF 121 15 OF 54 2 1 21 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 1 2 2 1 1 2 1 22 1 1 2 1 2 2 1 2 1 2 1 21 21 21 21 21 21 2 1 2 1 1 2 2 1 2 1 1 2 1 2 2 1 1 2 B2 B7 C8 G5 C6 D4 C7 C4 J5 H7 H5 G7 G6 F8 F7 F6 F5 E7 E6 E5 D8 D7 D6 D5 D3 C9 B10 B9 A7 B8 A6 A4 A5 B5 B4 A1 A2 B3 A3 B6 B1 C5 K5 H10 F2 C3 E4 K10 G2 H2 K3 F3 G4 C1 D1 J3 C2 H4 G3 D2 E2 F4 E10 A10 J2 H9 F1 E1 H6 J6 K6 H8 J7 K7 K1 J1 K8 J8 K4 J4 D9 D10 F9 F10 J9 K9 G1 G9 A9 E8 A8 E9 G10 H1 C10 E3 H3 K2 J10 G8 2 1 2 1 2 1 2 1 2 1 2 1 2 1 12 12 21 2 1 1 2 1654 52 1554 1552 15 15 15 15 52 1654 1552 15 15 52 1554 15 15 15 15 15 15 15 15 15 1552 52 1552 1552 52 15 52 15 15 15 15 15 15 15 1552 15 52 15 15
- 17. FILT+ SCL VP SDA VA ADO VBST SW GNDA IREF+ OUT+ OUT- ISENSE+ ISENSE- VSENSE+ VSENSE- LDO_FILT GNDP INT* RESET* ALIVE MCLK SCLK LRCK/FSYNC SDIN SDOUT VER1 FILT+ SCL VP SDA VA ADO VBST SW GNDA IREF+ OUT+ OUT- ISENSE+ ISENSE- VSENSE+ VSENSE- LDO_FILT GNDP INT* RESET* ALIVE MCLK SCLK LRCK/FSYNC SDIN SDOUT VER1 Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT SPEAKER CONNECTOR UPDATED: DEC 13 BY MARCH 2013. C0 FIXES PROCESS ISSUES. 2. THE CURRENT VERSION OF L19 IS B0 AND WILL CHANGE TO C0 REMOVED BASED ON PERFORMANCE ON J65 1. ALL THE EMI/DESSENSE FILTER COMPONENTS HAVE BEEN I2C ADDRESS: 1000000X PLACE XWS CLOSE TO CONNECTOR LEFT SPEAKER AMP I2C ADDRESS: 1000001X RIGHT SPEAKER AMP TFA302610A-SM 2.2UH-20%-3.3A-0.115OHM L2050 U2040 WLCSP CS35L19B-CWZR/C0 WLCSP U2050 CS35L19B-CWZR/C0 CRITICAL 0402-1 X5R-CERM 20% 10V 10UF C2094C2092 0.1UF 10% 10V X5R-CERM 0201 C2093 10V 10% 0.1UF X5R-CERM 0201 X5R-CERM 10UF CRITICAL C2095 10V 20% 0402-1 CRITICAL X5R-CERM 0402-1 20% 10V 10UF C2091 CRITICAL C2090 10V 20% 0402-1 X5R-CERM 10UF 10V C2042 CRITICAL X5R-CERM 4.7UF 0402 20% SIGNAL_MODEL=EMPTY SM XW2051 SIGNAL_MODEL=EMPTY SM XW2050 SIGNAL_MODEL=EMPTY SM XW2040 SIGNAL_MODEL=EMPTY SM XW2041 C2054 10V 0201 10% 0.1UF X5R-CERM C2055 603 X5R 10V 20% 10UF CRITICAL R2051 201 MF 1% 44.2K 1/20W 6.3V CERM-X5R 0.1UF 10% C2056 0201 4.7UF X5R-CERM1 CRITICAL C2058 6.3V 20% 402 402 C2057 20% CRITICAL 4.7UF X5R-CERM1 6.3V R2041 201 MF 1% 1/20W 44.2K X5R-CERM1 4.7UF C2048 402 20% 6.3V CRITICAL 20% 0402 10V X5R-CERM C2041 CRITICAL 4.7UF CRITICAL C2051 0402 10V 20% 4.7UF X5R-CERM C2043 0402 X5R-CERM 10V CRITICAL 4.7UF 20% CRITICAL TFA302610A-SM L2040 2.2UH-20%-3.3A-0.115OHM 10% C2044 X5R-CERM 0.1UF 10V 0201 CRITICAL 10UF C2045 20% 10V X5R 603 CERM-X5R 10% 6.3V 0.1UF C2046 0201 X5R-CERM1 CRITICAL C2047 20% 6.3V 4.7UF 402 MF 1% 1/4W 0.100 R2050 CRITICAL 0402 1% MF 1/4W CRITICAL 0.100 R2040 0402 CRITICAL C2052 X5R-CERM 4.7UF 0402 10V 20% CRITICAL C2053 20% 10V 0402 4.7UF X5R-CERM SIGNAL_MODEL=EMPTY XW2077 SM XW2076 SM SIGNAL_MODEL=EMPTY XW2075 SIGNAL_MODEL=EMPTY SM SIGNAL_MODEL=EMPTY SM XW2074 SYNC_MASTER=KAVITHA AUDIO: CS35L19A AMPS SYNC_DATE=01/18/2012 GPIO_SPKAMP_KEEPALIVE I2C2_SDA_1V8 I2S1_SPKAMP_MCK SPKR_L_CONN_P SPKR_L_CONN_P MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM I2S1_SPKAMP_DIN SPKR_R_VSENSE_N SPKR_R_VSENSE_N SPKR_R_CONN_P SPKR_R_CONN_PMIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM =PP1V7_VA_VCP SPKR_R_SES_P SPKR_L_SES_P SPKR_L_VSENSE_N SPKR_L_VSENSE_N =PPVCC_MAIN_AUDIO SPKR_L_VSENSE_P SPKR_L_VSENSE_P SPKR_R_VSENSE_P SPKR_R_VSENSE_P L19_R_SWITCH PP1V7_VA_VCP I2S1_SPKAMP_BCLK I2S1_SPKAMP_LRCK GPIO_SPKAMP_RIGHT_IRQ_L L19_L_LDO_FILT L19_R_LDO_FILT GPIO_SPKAMP_RST_L NET_SPACING_TYPE=PWRL19_L_VBOOST L19_R_IREF L19_L_FILTL19_L_SWITCH L19_L_IREF GPIO_SPKAMP_LEFT_IRQ_L I2S1_SPKAMP_BCLK I2S1_SPKAMP_LRCK I2S1_SPKAMP_DOUT I2C2_SDA_1V8 GPIO_SPKAMP_KEEPALIVE I2C2_SCL_1V8 GPIO_SPKAMP_RST_L I2S1_SPKAMP_MCK MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM SPKR_L_CONN_N SPKR_L_CONN_N SPKR_L_P MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM SPKR_L_SES_N MIN_LINE_WIDTH=0.5 MM SPKR_R_CONN_N MIN_NECK_WIDTH=0.2 MM SPKR_R_CONN_N SPKR_R_P MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM L19_R_FILT I2C2_SCL_1V8 I2S1_SPKAMP_DIN I2S1_SPKAMP_DOUT NET_SPACING_TYPE=PWR L19_R_VBOOST =PPVCC_MAIN_AUDIO SPKR_R_SES_N =PP1V7_VA_VCP 20 OF 121 A.0.0 051-0886 4 OF 416 OF 54 21 F2 D1 D6 A4 B1 C1 D5 F5 C7 A5 A1 A2 D4 F4 F3 B5 B6 C6 E4 C4 C3 B4 B3 B7 D2 C2 E1 F1 E2 E3 C5 D3 A3 A7 A6 D7 E7 E6 F6 F7 E5 B2 F2 D1 D6 A4 B1 C1 D5 F5 C7 A5 A1 A2 D4 F4 F3 B5 B6 C6 E4 C4 C3 B4 B3 B7 D2 C2 E1 F1 E2 E3 C5 D3 A3 A7 A6 D7 E7 E6 F6 F7 E5 B2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 1 2 1 2 1 2 1 2 2 1 2 1 2 1 21 2 1 2 1 2 1 1 2 1 2 1 2 2 1 2 1 1 2 1 2 1 2 1 2 51652 51652 51653 16 43 5216 43 52 51653 16 16 16 43 5216 43 52 15 16 54 16 16 151654 16 16 16 16 475254 51653 51653 5 516 5 51653 51653 51653 51652 51652 51652 516 51653 16 43 5216 43 52 16 43 52 16 43 52 51652 51653 51653 151654 15 16 54
- 18. Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT BUTTON CONNECTOR (MOVED HERE TO SUPPORT COST FORMAT) (REF DES PRESERVED FOR LAYOUT) 516S0828 01005 MF 1% 1/32W 1.00K R2900 01005 MF 1/32W 1% 1.00K R2901 01005 MF 1% 1/32W 1.00K R2902 01005 1/32W MF 1% 1.00K R2903 12.8V-100PF 201-1 DZ2960 12.8V-100PF 201-1 DZ2961 201-1 12.8V-100PF DZ2962 12.8V-100PF 201-1 DZ2963 CRITICAL J2960 F-ST-SM 503548-1010 25V 0201 CERM 82PF 5% C2963 0201-2 240-OHM-0.2A-0.8-OHM L2963 82PF 5% 25V 0201 CERM C2962 0201-2 240-OHM-0.2A-0.8-OHM L2962 82PF 25V 0201 CERM 5% C2961 0201-2 240-OHM-0.2A-0.8-OHM L2961 CERM 0201 25V 82PF 5% C2960 0201-2 240-OHM-0.2A-0.8-OHM L2960 BUTTON: CONN SYNC_DATE=N/ASYNC_MASTER=N/A GPIO_BTN_ONOFF_R_L GPIO_BTN_VOL_UP_R_L GPIO_BTN_VOL_DOWN_R_L GPIO_BTN_SRL_R_L GPIO_BTN_VOL_DOWN_L GPIO_BTN_VOL_UP_L GPIO_BTN_ONOFF_L GPIO_BTN_SRL_L GPIO_BTN_ONOFF_L_FILT GPIO_BTN_VOL_UP_L_FILT GPIO_BTN_SRL_L_FILT GPIO_BTN_VOL_DOWN_L_FILT 051-0886 A.0.0 21 OF 121 17 OF 54 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 5 3 10 8 6 4 9 7 2 13 11 12 14 2 1 21 2 1 21 2 1 21 2 1 215 5 548 548 52 52 52 52
- 19. OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN NCIN OUT SYM_VER-2 SYM_VER-2 SYM_VER-2 SYM_VER-2 SYM_VER-2 IN IN IN IN IN IN IN IN IN IN IN GND VDD D SON CAP Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM REVIEW: 4700PF 0201 132S0187 EDP CONNECTOR SUPPORT LAYOUT NOTE: PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION REVIEW: CAN/SHOULD WE USE 132S0316, 0.1UF 20%, 01005 RDAR://PROBLEM/12579948 RDAR://PROBLEM/12579963 TO REDUCE THE 2.5V FROM THE TCON TO 1.8V TO THE AP? REVIEW: WILL THE DISPLAY INCLUDE A VOLTAGE DIVIDER RDAR://PROBLEM/12579981 P/N 516S1056 NOTE: HOWEVER TO BE CONSERVATIVE, DIVIDER CKT IS NOT REMOVED PER GREG DE MERCEY, EDP_HPD PIN IS 2.5V TOLERANT BACK-UP DELAYED PWREN CKT 7 C2221 NP0-C0G-CERM 50V 56PF 2% 0201 18 18 18 53 18 53 18 53 18 53 18 53 18 53 18 53 18 53 L2240 01005 240-OHM-25%-0.20A-1.0DCR C2260 27PF NP0-C0G 16V 5% 01005 5% R2243 MF 1/32W 01005 100K 18 53 18 53 18 53 18 53 18 53 18 53 18 53 18 53 18 18 C2232 16V 01005 NP0-C0G-CERM 15PF 5% F-ST-SM-1 CRITICAL AA07A-S032-VA1 J2201 L2201 0402A CRITICAL FERR-120-OHM-1.5A 47 47 47 47 47 1852 47 CERM C2230 82PF 0201 5% 25V 1852 1/32W MF 01005 R2250 7.5K 5% U2201 CRITICAL SOT891 74LVC1G32 LCM_PWR_EN_OR_GATE LCM_PWR_EN_OR_GATE 0.1UF 6.3V 20% 01005 X5R-CERM C2270 518 01005 0.000% R2290 MF 1/32W LCM_PWR_EN_OR_GATE CRITICAL C2202 20% 10UF 0402 6.3V CERM-X5R 518 1/32W MF 0% 0.00 R2291 01005 LCM_PWR_EN_RES 0.1UF X5R-CERM C2203 0201 16V 10% R2242 1/32W 01005 MF 5% 20.0K +/-0.5PF C2233 50V C0G-CERM 8.2PF 201 0402 220-OHM-1A L2200 CRITICAL 3.25-OHM-0.1A-2.4GHZ L2242 CRITICAL TAM0605-4SM 5% R2241 100K MF 01005 1/32W 3.25-OHM-0.1A-2.4GHZ L2212 CRITICAL TAM0605-4SM 3.25-OHM-0.1A-2.4GHZ L2222 CRITICAL TAM0605-4SM 3.25-OHM-0.1A-2.4GHZ CRITICAL L2232 TAM0605-4SM C2250 01005 0.1UF 6.3V X5R-CERM20% C2251 6.3V 0.1UF X5R-CERM20%01005 C2242 0.1UF 6.3V X5R-CERM20%01005 20% 0.1UFC2243 6.3V X5R-CERM01005 0.1UFC2244 X5R-CERM20%01005 6.3V 0.1UFC2245 6.3V X5R-CERM20%01005 0.1UFC2246 6.3V X5R-CERM20%01005 0.1UFC2247 6.3V X5R-CERM20%01005 0.1UFC2248 6.3V X5R-CERM20%01005 3.25-OHM-0.1A-2.4GHZ L2202 CRITICAL TAM0605-4SM C2249 0.1UF 6.3V X5R-CERM20%01005 0201 16V 0.1UF X5R-CERM C2239 10% 518 7 7 MF 100K 5% 1/32W 01005 R2205 753 753 753 753 753 753 753 753 TDFN CRITICAL U2200 SLG5AP304V OMIT C2240 0201 0.1UF X5R-CERM 16V 10% 0402 10% X7R 3900PF C2241 50V VIDEO: EDP SUPPORT & CONN SYNC_MASTER=J85 MLB_C SYNC_DATE=12/05/2012 155S0667 155S0583 RDAR://PROBLEM/8616060, RADAR://PROBLEM/9015335 L2242,L2810,L2811,L2812,L2813,L2814,L2710,L2711,L2712,L6030,L6031 EDP_DATA_EMI_CONN_P<0> EDP_DATA_EMI_CONN_N<0> EDP_DATA_EMI_CONN_P<1> EDP_DATA_EMI_N<1> EDP_DATA_EMI_P<1> EDP_AUX_EMI_N EDP_AUX_EMI_PEDP_AUX_P LCM_OFF_L EDP_DATA_N<1> EDP_DATA_N<0> EDP_DATA_P<0> EDP_DATA_N<2> PPVCC_MAIN_LCD_SW_CONN =PPLED_REG_A PPLED_BACK_REG_A GPIO_SOC2LCD_PWREN LCD_RAMP EDP_AUX_EMI_CONN_N EDP_AUX_EMI_CONN_P EDP_DATA_EMI_CONN_N<1> EDP_DATA_EMI_CONN_P<2> EDP_DATA_EMI_CONN_N<2> EDP_DATA_EMI_CONN_P<3> EDP_DATA_EMI_CONN_N<3> EDP_AUX_N EDP_DATA_EMI_P<0> EDP_DATA_EMI_N<0> EDP_DATA_EMI_N<2> EDP_DATA_P<1> EDP_DATA_EMI_P<2> EDP_DATA_EMI_P<3> EDP_DATA_P<2> EDP_DATA_N<3> EDP_DATA_P<3> PPVCC_MAIN_LCD_SW EDP_HPDEDP_HPD_2P5EDP_HPD_EMI PPVCC_MAIN_LCD_SW_CONN EDP_DATA_EMI_CONN_N<2> EDP_DATA_EMI_CONN_P<2> EDP_DATA_EMI_CONN_N<1> EDP_DATA_EMI_CONN_P<1> EDP_DATA_EMI_CONN_N<3>EDP_HPD_EMI EDP_AUX_EMI_CONN_P EDP_DATA_EMI_CONN_N<0> EDP_DATA_EMI_CONN_P<0> EDP_AUX_EMI_CONN_N EDP_DATA_EMI_CONN_P<3> LED_IO_5_A LED_IO_6_A LED_IO_4_A LED_IO_2_A LED_IO_3_A LED_IO_1_A PPLED_BACK_REG_A =PPVCC_MAIN_LCD GPIO_SOC2LCD_PWREN NC_U2201_5 GPIO_SOC2LCD_PWREN GATE2LCD_PWREN =PP1V8_SOC EDP_DATA_EMI_N<3> 051-0886 A.0.0 22 OF 121 18 OF 54 2 1 21 2 1 1 2 2 1 9 11 13 15 17 3 7 14 16 18 12 10 8 4 6 2 31 29 19 21 23 25 27 32 30 26 28 24 22 20 5 1 3334 3536 21 2 1 1 2 2 6 1 4 35 2 1 1 2 2 1 1 2 2 1 1 2 2 1 21 4 32 1 1 2 4 32 1 4 32 1 4 32 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 4 32 11 2 2 1 1 2 81 3 52 7 2 1 2 1 53 53 18 52 54 18 52 53 53 53 53 53 18 18 54 4571054 53
- 20. OUT OUT OUT IN IN IN VSS VSS RESET* P0_10 P0_9 P0_8 P0_7 P0_4 P0_5 P0_3 P0_2 P0_1 P0_0 DBGEN P0_20 P0_21 P0_22 P0_18 P0_19 P0_15 P0_17 P0_16 P0_14 P0_12 P0_11 VDDC VDDIO VDDC P0_13 P0_6 OUT IN IN BI IN IN OUT OUT OUT IN IN IN IN IN OUT OUT Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT RDAR://PROBLEM/12580012 COMPARE SENSOR CONNECTIONS WITH N51, IDENTIFY AND UNDERSTAND DIFFERENCES REVIEW: N51 HAS OSCAR I2C CONNECTED TO RF CAM I2C OSCAR CORE = 1.2V HIBERNATE (NEED TO RUN IN S2R) APN 337S4416 NOTE: I2C1 IS ASSUMED TO USE PUSH-PULL INSTEAD OF OPEN-DRAIN OSCAR REVIEW:NEED PU ON CS? RDAR://PROBLEM/12579997 OSCAR VDDIO = 1.8V HIBERNATE (NEED TO WAKE HOST) 28 44 52 28 44 52 21 21 MF 5% 15.0 01005 1/32W R2405 R2406 MF 1/32W 5% 15.0 01005 21 5 MF 1/32W 0.00 0% R2450 01005 CRITICAL WLCSP U2400 LPC18A1UK-CPA1 0201-1 6.3V X5R 20% 1.0UF C2400 X5R 6.3V 1.0UF 20% 0201-1 C2401 5% 100K R2400 01005 1/32W MF 5 53 5 53 5 5 48 52 5 548 5 21 21 21 21 21 21 21 21 SENSOR: OSCAR SYNC_MASTER=J72_MLB_C SYNC_DATE=11/26/2012 GPIO_OSCAR_RESET_L GPIO_SOC2OSCAR_DBGEN TP_OSCAR_P0_22 GPIO_SOC2OSCAR_DBGEN_R SPI_OSCAR_MISO SPI_OSCAR2ACCEL_CS_L SPI_OSCAR2GYRO_CS_L =PP1V2_S2R_OSCAR UART4_OSCAR2SOC_RXD I2C1_SOC2OSCAR_SWDCLK_1V8 OSCAR2RADIO_CONTEXT_A OSCAR2RADIO_CONTEXT_B SPI_OSCAR_SCLK SPI_OSCAR_MOSI I2C1_SOC2OSCAR_SWDIO_1V8 PMU_GPIO_OSCAR2PMU_HOST_WAKE OSCAR_TIME_SYNC_HOST_INT SPI_OSCAR2COMPASS_CS_L COMPASS2OSCAR_INT ACCEL2OSCAR_INT2 GYRO2OSCAR_INT1 GYRO2OSCAR_INT2 ACCEL2OSCAR_INT1 =PP1V8_S2R_OSCAR SPI_OSCAR_MOSI_R =PP1V8_S2R_OSCAR SPI_OSCAR_SCLK_R UART4_SOC2OSCAR_TXD PMU_GPIO_CLK_32K_OSCARNC_ISP0_CAM_REAR_SDA NC_ISP0_CAM_REAR_SCL 051-0886 A.0.0 24 OF 121 19 OF 54 1 2 1 2 1 2 D6 B1 E4 A2 A3 E1 D4 D5 E2 C5 E6 E5 E3 D2 B6 D1 A6 C3 C4 B4 B5 A5 B3 B2 A1 C1 C2 C6 A4 D3 2 1 2 1 1 2 54 19 54 1954
- 21. IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND IN1 IN2 IN4 IN3 OUT1 OUT2 OUT3 OUT4 GND OUT IN BI IN BI OUT IN IN OUT OUT OUT SYM_VER-2 SYM_VER-2 Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT ISP1_CAM_FRONT_SHUTDOWN_L HIGH = TURN ON CAMERA LOW = SHUT DOWN CAMERA VGA FRONT CAMERA CONNECTOR 516S0876 RCPT MLB 516S0869 PLUG FLEX F-ST-SM 503548-1820 CRITICAL J2601 10% 01005 6.3V X5R-CERM 1000PF C2602 X5R 1UF 6.3V 0201 20% C2601 0201 240OHM-350MA L2600 C2600 5% 16V 56PF 01005 NP0-C0GSM XW2600 R2601 1/32W MF 01005 1% 100K 1208 U2601400MHZ-0.1A-27PF X5R-CERM 1000PF 01005 10% 6.3V C2605 0201 20% 6.3V 1UF X5R C2604 56PF C2603 5% NP0-C0G 16V 01005 6.3V 10% 1000PF 01005 X5R-CERM C2608 1UF 0201 20% 6.3V X5R C2607 5% 16V 56PF C2606 01005 NP0-C0G 1208 400MHZ-0.1A-27PF U2600 7 53 0201 240OHM-350MA L2601 240-OHM-0.2A-0.8-OHM 0201-2 L2602 752 752 752 522 5 522 752 7 53 7 53 7 53 90-OHM-50MA TCM0605-1 L2610 90-OHM-50MA TCM0605-1 L2611 150OHM-25%-200MA-0.7DCR 01005 L2660 SYNC_DATE=12/03/2012SYNC_MASTER=J85 MLB_C CAMERA: FF-ALS CONN & FILTERS ISP1_CAM_FRONT_SHUTDOWN_L_F I2C3_SCL_1V8_F GPIO_ALS_IRQ_L_F PP1V8_CAM_FRONT_FILT ISP1_CAM_FRONT_SHUTDOWN_L I2C3_SCL_1V8 GPIO_ALS_IRQ_L I2C3_SDA_1V8 ISP1_CAM_FRONT_CLK ISP1_CAM_FRONT_SDA ISP1_CAM_FRONT_SCL =PP3V0_ALS =PP1V8_CAM_FRONT ISP1_CAM_FRONT_CLK_F I2C3_SDA_1V8_F ISP1_CAM_FRONT_SCL_F ISP1_CAM_FRONT_SDA_F =PP2V9_CAM_FRONT MIPI1C_CAM_FRONT_CLK_FILT_N MIPI1C_CAM_FRONT_CLK_FILT_P MIPI1C_CAM_FRONT_DATA_FILT_N<0> MIPI1C_CAM_FRONT_DATA_FILT_P<0> GPIO_ALS_IRQ_L_F I2C3_SCL_1V8_F I2C3_SDA_1V8_F ISP1_CAM_FRONT_CLK_F_R ISP1_CAM_FRONT_SHUTDOWN_L_F ISP1_CAM_FRONT_SDA_F ISP1_CAM_FRONT_SCL_F PP2V9_AVDD_CAM_FRONT_FILT GND_AVDD_CAM_FRONT PP1V8_CAM_FRONT_FILT PP3V0_ALS_FILT ISP1_CAM_FRONT_CLK_F_R ISP1_CAM_FRONT_CLK_F MIPI1C_CAM_FRONT_DATA_FILT_N<0> MIPI1C_CAM_FRONT_DATA_FILT_P<0> MIPI1C_CAM_FRONT_DATA_P<0> MIPI1C_CAM_FRONT_DATA_N<0> MIPI1C_CAM_FRONT_CLK_FILT_N MIPI1C_CAM_FRONT_CLK_FILT_P MIPI1C_CAM_FRONT_CLK_P MIPI1C_CAM_FRONT_CLK_N NC_U2601_5NC_U2601_1 PP3V0_ALS_FILT GND_AVDD_CAM_FRONT VOLTAGE=0V NET_SPACING_TYPE=GND MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.15 MM PP2V9_AVDD_CAM_FRONT_FILT MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR VOLTAGE=2.9V 051-0886 A.0.0 26 OF 121 20 OF 54 6 21 17 15 13 11 9 7 5 3 12 4 8 10 12 14 16 18 1920 22 2 1 2 1 21 2 1 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 21 21 4 32 1 4 32 1 21 20 20 20 20 54 54 20 20 20 20 54 2053 2053 2053 2053 20 20 20 20 20 20 20 20 20 20 20 20 20 2053 2053 2053 2053 20 20 20
- 22. OUT IN IN IN IN OUT OUT IN OUT IN IN IN OUTDRDY SCL/SK SDA/SI VDD RSV SO VSS TST1 TRG VID CAD0 CAD1 RST* CSB* INT2 DEN INT1 GND CS SDO/SA0 SDA/SDI/SDO SCL/SPC VDD_IO DRDY/ RES2 RES1 RES0 VDD RES/VDD CAP GND INT2 INT1 RES RES RES CS RES RES SDO/SA0 SCL/SPC SDA/SDI/SDO VDDVDD_IO GND OUT IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 11V CHARGE PUMP COMPASS TO VID WHEN NOT USED APN 338S1014 TIE CSB* TO VID FOR I2C MODE GYRO ACCELEROMETER MF 1/32W 01005 0.00 0% R2727 19 0% 0.00 MF 1/32W 01005 R2757 19 21 19 21 C2701 20% 6.3V 01005 0.1UF X5R-CERM C2700 CERM-X5R 6.3V 20% 10UF 0402-2 19 21 120-OHM-25%-250MA-0.5DCR 01005 L2700 19 19 19 20% 6.3V C2725 0.1UF X5R-CERM 010050402-2 10UF CERM-X5R 6.3V 20% C2723 19 21 20% 6.3V C2721 0.1UF X5R-CERM 01005 01005 120-OHM-25%-250MA-0.5DCR L2702 19 21 01005 MF 1/32W 15.0 5% R2747 01005 L2741 120-OHM-25%-250MA-0.5DCR 19 21 19 21 C2726 0.1UF 0201 10% 16V X5R-CERM OMIT 19 19 C2711 6.3V 01005 20% X5R-CERM 0.1UF C2710 6.3V 20% X5R 0201-1 1.0UF XW2700 SHORT-10L-0.25MM-SM CSP U2710 AK8963C CRITICAL 01005 120-OHM-25%-250MA-0.5DCR L2701 CKPLUS_WAIVE=PWRTERM2GND CRITICAL AP3GDL20HAB18TR U2720 LGA OMIT MF 1/32W 0.00 0% R2750 01005 SHORT-10L-0.25MM-SM XW2701 X5R-CERM 0.1UF 01005 6.3V 20% C2750 OMIT AP2DHAB26TR CRITICAL U2700 LGA 19 19 SYNC_DATE=N/ASYNC_MASTER=N/A SENSOR: ACCEL, COMPASS, GYRO NO_TEST=TRUENC_COMPASS_TST1 GND_COMP GYRO_DEN SPI_OSCAR_MISO_GYRO PP3V0_COMP GYRO_RES_VDD GYRO2OSCAR_INT1 SPI_OSCAR2GYRO_CS_L SPI_OSCAR_MOSI SPI_OSCAR_SCLK =PP1V8_S2R_GYRO GYRO2OSCAR_INT2 PP3V0_GYRO GYRO_PUMP SPI_OSCAR_MISO =PP3V0_S2R_ACCEL SPI_OSCAR_MISO =PP3V0_S2R_GYRO =PP3V0_S2R_COMP SPI_OSCAR2COMPASS_CS_L PP1V8_COMP NO_TEST=TRUENC_COMPASS_TRG SPI_OSCAR_MISO_COMP1NC_COMPASS_RSV NO_TEST=TRUE SPI_OSCAR_MOSI SPI_OSCAR_SCLK COMPASS2OSCAR_INT =PP1V8_S2R_COMP SPI_OSCAR_MISO PP1V8_COMP GND_COMP GND_COMP =PP1V8_S2R_ACCELPP3V0_ACCEL SPI_OSCAR_MOSI SPI_OSCAR_SCLK SPI_OSCAR_MISO_ACCEL SPI_OSCAR2ACCEL_CS_L ACCEL2OSCAR_INT2 ACCEL2OSCAR_INT1 051-0886 A.0.0 27 OF 121 21 OF 54 1 2 1 2 2 1 2 1 21 2 1 2 1 2 1 21 1 2 21 2 1 2 1 2 1 21 A1 A3 A4 B1 B3 B4 C1 C2 C3 C4 D1 D2 D4 A2 21 8 7 13 5 4 3 2 1 6 11 10 9 16 15 14 12 1 2 2 1 5 6 13 14 12 4 11 10 3 1 2 8 7 9 21 54 19 21 54 19 21 54 54 21 5421 21 21 54
- 23. ADD0 SCLK CIN1 CIN3 CIN4 CIN12 CIN11 CIN6 CIN9 CIN8 CIN10 CIN2 CIN5 CIN0 ACSHIELD GND BIAS SDA VDRIVEVCC ADD1 INT* GPIO CIN7 TPNC NC NC NC NC NC NC NC NC NC BI IN OUT Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 516S0872 PROX SENSOR CHOSE CIN NUMBERS FOR LAYOUT EASE PCB: ENSURE ACSHIELD PLANE UNDER VDRIVERAIL READ: 0X59, WRITE: 0X58 353S2964 CONNECTED TO MLB INTERCONNECT. THEREFORE,PROX GPIO IS NOT PROX GPIO WILL NOT BE USED. INT IS 1.8V LEVEL. 1.8 MA MAX 0.5 PF REF CAP TO MEASURE NEED EXTERNAL JUST IN CASE U3200, NO GND PLANE NEAR PROX_CIN NETS.. INT* IS OPEN DRAIN PU RAIL MATCH VDRIVE VDRIVE FOR: I2C AND GPIO CIN9 SENSOR ELECTRODE CIN7 DUMMY AND ALSO TIE TO CONNECTOR. A PLANE UNDER PROX_CIN NETS PCB: ACSHIELD NEEDS TO BE I2C ADDRESS: 0101100+R/W PROX C2804 6.3V 0.1UF X5R-CERM 20% 01005 PROX C2805 68PF 5% 6.3V NP0-C0G 01005 PROX R2800 MF 2.0K 1/32W 1% 01005 PROX R2801 MF 100K 1% 1/32W 01005 PROX 0201 0.01UF C2802 10% 10V X5R-CERM PROX C2800 X5R 402 10% 6.3V 2.2UF PROX C2803 +/-0.05PF 201 CERM 25V 0.5PF PROX C2801 0.1UF 6.3V X5R-CERM 20% 01005 PROX C2806 5% 68PF 6.3V NP0-C0G 01005 PROX C2807 NP0-C0G 201 25V 27PF 1% PROX U2800 WLCSP AD7149 CRITICAL PROX L2801 68NH-2%-320MA-1.0OHM 0402 CRITICAL PROX CRITICAL L2807 68NH-2%-320MA-1.0OHM 0402 PROX CRITICAL 0603 L2808 390NH-2%-170MA-4.0OHM PROX 0603 L2802 CRITICAL 390NH-2%-170MA-4.0OHM PROX L2803 68NH-2%-320MA-1.0OHM 0402 CRITICAL PROX 0603 L2804 CRITICAL 390NH-2%-170MA-4.0OHM 520 PROX 0201-2 240-OHM-0.2A-0.8-OHM L2800 520 PROX J2800 503548-0620 CRITICAL F-ST-SM 5 SENSOR: PROX SYNC_MASTER=J85 MLB_C SYNC_DATE=12/05/12 ACSHIELD_SB NC_J2800_6 NC_J2800_2 NC_J2800_4 PROX_CIN9_CONN PROX_ACSHIELD_CONN =PP1V8_PROX PP3V0_SENSOR_PROX_FILT I2C3_SCL_1V8 PROX_GPIO PROX_CIN9 CIN9 ACSH_SB PROX_CIN1 TP_PROX_CIN2 PROX_CIN7 CIN7 GPIO_PROX_IRQ_L =PP3V0_PROX I2C3_SDA_1V8 PROX_CIN7_CONN PROX_BIAS =PP1V8_PROX 051-0886 A.0.0 28 OF 121 22 OF 54 2 1 2 1 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 D1 C1 A3 A4 C3 E5 D5 B4 C5 C4 D4 B3 A5 D3 E4 E2 E3 E1 C2 D2 B1 A1 A2 B5 B2 2 1 2 12 1 2 1 2 12 1 2 1 8 21 109 3 4 5 6 7 2254 54 2254
- 24. BI IN IN SYM_VER-2 SYM_VER-2 SYM_VER-2 OUT OUT OUT OUT OUT OUT IN Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT REAR CAMERA CONNECTOR APN: 516S0973 PLUG: 516S0974 X5R-CERM 10% 01005 6.3V 1000PF C2902C2901 402 1UF 10% 10V X5R 5% 16V C2900 56PF 01005 NP0-C0G L2900 240OHM-350MA 0201 752 6.3V X5R-CERM 10% 1000PF 01005 C2905C2904 10% 402 1UF 10V X5R 16V 5% 56PF NP0-C0G 01005 C2903 240OHM-350MA 0201 L2901 C2908 10% 01005 X5R-CERM 6.3V 1000PF C2907 X5R 10V 1UF 402 10%5% 16V 56PF NP0-C0G C2906 01005 240OHM-350MA 0201 L2902 10% C2911 X5R-CERM 6.3V 1000PF 01005 1UF 10V 402 10% X5R C2910 16V 5% 56PF NP0-C0G 01005 C2909 240OHM-350MA 0201 L2903 752 C2970 5% 56PF NP0-C0G 16V 01005 5% 16V 56PF 01005 NP0-C0G C2971 16V 5% NP0-C0G C2972 56PF 01005 C2973 16V 5% NP0-C0G 56PF 01005 F-ST-SM AA07-S022VA1 J2950 CRITICAL 7 52 90-OHM-50MA TCM0605-1 L2910 TCM0605-1 L2911 90-OHM-50MA 90-OHM-50MA TCM0605-1 L2912 7 53 7 53 7 53 7 53 7 53 7 53 XW2950SM XW2951SM 150OHM-25%-200MA-0.7DCR 01005 L2950 752 1000PF 6.3V 01005 10% X5R-CERM C2980R2950 01005 1/32W MF 100K 1% CAMERA: REAR CONN & FILTERS SYNC_MASTER=N/A SYNC_DATE=N/A =PP2V9_CAM_REAR CAM_REAR_VSYNC VOLTAGE=2.9V PP2V9_AVDD_CAM_REAR_FILT MIN_NECK_WIDTH=0.2 mm MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.6 mm NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=5 MM NET_SPACING_TYPE=GND MIN_NECK_WIDTH=0.1 MM VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm GND_CAM_AVDD =PP1V3_CAM_REAR =PP2V6_CAM_REAR_AF =PP1V8_CAM_REAR ISP0_CAM_REAR_CLK_F MIPI0C_CAM_REAR_CLK_FILT_P MIPI0C_CAM_REAR_DATA_FILT_P<0> MIPI0C_CAM_REAR_DATA_FILT_N<0> MIPI0C_CAM_REAR_DATA_FILT_P<1> MIPI0C_CAM_REAR_CLK_FILT_N MIPI0C_CAM_REAR_DATA_FILT_N<1> ISP0_CAM_REAR_CLK MIPI0C_CAM_REAR_DATA_N<0> MIPI0C_CAM_REAR_DATA_P<0> MIPI0C_CAM_REAR_CLK_N MIPI0C_CAM_REAR_CLK_P MIPI0C_CAM_REAR_DATA_N<1> MIPI0C_CAM_REAR_DATA_P<1> MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM PP2V6_CAM_REAR_AF_FILT VOLTAGE=2.6V GND_AF_AVDD MAX_NECK_LENGTH=5 MM NET_SPACING_TYPE=GND MIN_NECK_WIDTH=0.1 MM VOLTAGE=0V MIN_LINE_WIDTH=0.6 mm PP1V8_CAM_REAR_FILT ISP0_CAM_REAR_SDA ISP0_CAM_REAR_SCL ISP0_CAM_REAR_SHUTDOWN_L PP1V3_CAM_REAR_FILT 051-0886 A.0.0 29 OF 121 23 OF 54 2 1 2 1 2 1 21 2 1 2 1 2 1 21 2 1 2 1 2 1 21 2 1 2 1 2 1 21 2 1 2 1 2 1 2 1 25 26 24 23 22 20 18 16 10 14 12 8 6 4 2 21 19 17 15 7 9 11 13 5 3 1 4 32 1 4 32 1 4 32 1 1 2 1 2 21 2 1 1 254 54 54 54 53 53 53 53 53 53
- 25. PP PP PP PP PP PP PP PP PP PP OUT OUT IN OUT OUT OUT OUT IN OUT OUT OUT OUT BI BI IN OUT IN IN IN OUT OUT IN OUT IN IN OUT OUT OUT IN IN OUT BI BI Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST GPIO53/BOOT_CONFIG_1 SIM CARD ESD PROTECTION 48 PROBE POINTS GPIO48/BOOT_CONFIG_6 DEBUG CONNECTOR BOOT_HSIC_OPTION BOOT_NAND_OPTION SW REGISTER GPIO53/BOOT_CONFIG_1 GPIO48/BOOT_CONFIG_6 ENABLE SAHARA PROTOCOL BOOT_USB_OPTION 0X03 BOOT_DEFAULT_OPTION BOOT OPTIONS 0X00 0X01 0X08 47 X 0X02 VALUE X X X 6 GPIO/BOOT_CONFIG CONFIGURATION 0 1 1 1 1 0 0 1 0 X X X 0 0 0 0 000 0 0 5 49 0 34 0 50 0 51 1 0 100 1 10 0 52 2 53 0 54 0 1 0 X X X X 55 0 BOOT_CONFIG X AP INTERFACE & DEBUG CONNECTORS GPIO51/BOOT_CONFIG_3 GPIO54/BOOT_CONFIG_0 SM P4MM PP3002 P4MM SM PP3001 SM P4MM PP3000 NOSTUFF F-ST-SM MM4829-2702 J3001 NOSTUFF F-ST-SM MM4829-2702 J3002 P4MM SM PP3009 SM P4MM PP3008 SM P4MM PP3010 P4MM SM PP3011 SM P4MM PP3012 SM P4MM PP3013 SM P4MM PP3003 NOSTUFF 10K MF 01005 5% 1/32W R3002 NOSTUFF 5% 10K 1/32W MF 01005 R3003 28 2428333940 284852 283940 14242852 2752 52752 52752 52752 52752 52752 2752 27 27 2627 264852 NOSTUFF M-ST-SM AXE654124 J3003 5 28 5 28 5 28 27 48 52 5 28 5 28 5 11 28 52 28 5 11 28 52 4 8 10 11 48 52 52652 2652 25 33 34 35 36 37 38 54 24 25 27 28 30 52 5 26 52 115253 NOSTUFF SHORT-10L-0.25MM-SM XW3002 NOSTUFF SHORT-10L-0.25MM-SM XW3003 115253 CELL 12V-33PF01005-1 C3000 CELL ESD0P2RF-02LS TSSLP-2-1 U3001 CELL TSSLP-2-1 ESD0P2RF-02LS U3000 CELL TSSLP-2-1 ESD0P2RF-02LS U3003 CELL TSSLP-2-1 ESD0P2RF-02LS U3002 CELL:AP INTERFACE & DEBUG CONNECTORS UART3_BB2SOC_RTS_L PMU_GPIO_BB_VBUS_DET PMU_GPIO_BB2PMU_HOST_WAKE GPIO_51 ANT_SEL_1 ANT_SEL_2 LAT_SW1_CTL BB_JTAG_RTCLK BB_JTAG_TDI BB_JTAG_TDO BB_JTAG_TCK BB_JTAG_TRST_L BB_JTAG_TMS DEBUG_RST_L USB_BB_DEBUG_P USB_BB_DEBUG_N PMIC_RESOUT_L PMU_GPIO_PMU2BBPMU_RST_L HSIC2_SOC2BB_HOST_RDY GPIO_BB2SOC_RESET_DET_L HSIC2_BB2SOC_DEVICE_RDY UART3_SOC2BB_RTS_L UART3_SOC2BB_TX UART3_BB2SOC_TX RESET_SOC_L CKPLUS_WAIVE=SINGLE_NODENET GPIO_SOC2BB_RADIO_ON_L PS_HOLD_PMIC =PPBATT_VCC_BB PP_SMPS3_MSME_1V8 GPIO_SOC2BB_RST_L USB_BB_N USB_BB_P GPIO_DEBUG_LED SIM_TRAY_DETECT SIMCRD_CLK_CONN SIMCRD_IO_CONN SIMCRD_RST_CONN PP_LDO6_RUIM_1V8 UART_BB2WLAN_LTE_COEX SLEEP_CLK_32K WTR_SSBI_PRX_DRX WTR_RF_ON 19P2M_MDM PMIC_SSBI BB_ERROR_FLAG LAT_SW1_CTL PP_SMPS3_MSME_1V8 WTR_SSBI_TX_GPS WTR_RX_ON HSIC2_BB_DATA HSIC2_BB_STB UART_WLAN2BB_LTE_COEX ANT_SEL_1 051-0886 A.0.0 30 OF 121 24 OF 54 1 1 1 4 2 3 1 4 2 3 1 1 1 1 1 1 1 1 1 2 1 2 50 42 44 46 48 32 34 36 38 40 26 22 24 28 30 16 14 12 18 20 2 10 8 6 4 49 47 45 43 41 33 31 29 27 25 23 21 35 37 39 7 5 3 1 19 17 15 9 11 13 52 54 51 53 55 58 57 56 21 21 1 2 21 21 2 1 2 1 10 28 52 10 28 52 102852 102852 10 25 27 52 28 44 26 27 28 29 28 29 26 27 26 27 28 14242852 24 25 27 28 30 52 28 29 28 29 4 27 53 4 27 53 28 44 2428333940
- 26. IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN VDD_S4 VSW_S5 VSW_S3 VSW_S2 VREG_XO VREG_S5 VREG_S4 VREG_RFCLK VREG_L9 VREG_L8 VREG_L7 VREG_L6 VREG_L5 VREG_L4 VREG_L3 VREG_L2 VREG_L14 VREG_L13 VREG_L12 VREG_L11 VREG_L10 VOUT_LVS1 VDD_XO VDD_S5 VDD_S2 VDD_S1 VDD_L9 VDD_L8 VDD_L7 VDD_L5_L6_L13_L14 VDD_L4 VDD_L2_L3 VDD_L12 VDD_L10_L11 REF_GND REF_BYP VSW_S5_2 VREG_S3 VSW_S4 VDD_S3 VSW_S1 VREG_S1 VREG_S2 VREG (SYM 5 OF5) OUT OUT OUT OUT OUT OUT OUT OUT OUT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT INTERNAL USE ONLY INTERNAL USE ONLY PMU (1 OF 2) 2433343536373854 4.7UF 20% 0402 10V X5R-CERM C3204 X5R-CERM 0402 10V 20% 4.7UF C3205 4.7UF 20% 10V 0402 X5R-CERM C3206 X5R-CERM 4.7UF 10V 20% 0402 C3207 0402 X5R-CERM 10V 20% 4.7UF C3208 SHORT-10L-0.1MM-SM XW3200 X5R-CERM 6.3V 20% 0.1UF 01005 C3209 41 27 0402-2 20% 6.3V CERM-X5R 10UF C3200 26 27 2.2UH-20%-2.34A-0.113OHM 2520-SM CRITICAL L3204 2.2UH-20%-1.2A-0.15OHM 0806 CRITICAL L3203 22UF 6.3V X5R-CERM-1 603 20% C3224 22UF 20% 6.3V X5R-CERM-1 603 C3225 2.2UH-20%-1.2A-0.15OHM CRITICAL 0806 L3202 0806 2.2UH-20%-1.2A-0.15OHM CRITICAL L3201 X5R-CERM-1 22UF 603 20% 6.3V C3226 22UF X5R-CERM-1 603 20% 6.3V C3228 X5R-CERM-1 603 20% 22UF 6.3V C3229 25 52 27 25 30 52 NOSTUFF 4V X5R 01005 20% 0.1UF C3227 24 25 27 28 30 52 27 30 0806 2.2UH-20%-1.2A-0.15OHM CRITICAL L3200 1.0UF 6.3V X5R 20% 0201-1 C3230 27 52 27 2552 253052 242527283052 BGA PM8018-0 CRITICAL U3300 27 27 27 27 0402-2 6.3V CERM-X5R 20% 10UF C3201 27 27 14 32 33 39 40 27 10 24 27 52 6.3V X5R 1.0UF 20% 0201-1 C3210 6.3V 20% X5R 1.0UF 0201-1 C3212 1.0UF X5R 20% 6.3V 0201-1 C3214 20% 6.3V X5R 1.0UF 0201-1 C3217 X5R 20% 6.3V 1.0UF 0201-1 C3211 1.0UF X5R 6.3V 20% 0201-1 C3213 6.3V 20% X5R 1.0UF 0201-1 C3215 20% X5R 1.0UF 6.3V 0201-1 C3216 0402-2 CERM-X5R 20% 6.3V 10UF C3202 1.0UF X5R 6.3V 20% 0201-1 C3219 10UF 0402-2 CERM-X5R 20% 6.3V C3221 0402-2 CERM-X5R 10UF 6.3V 20% C3223 0402-2 6.3V 20% 10UF CERM-X5R C3218 0402-2 CERM-X5R 10UF 6.3V 20% C3220 10UF 20% 6.3V CERM-X5R 0402-2 C3222 1.0UF 6.3V X5R 20% 0201-1 C3231 01005 5% 56PF NP0-C0G 16V C3203 CELL: BASEBAND PMU (1 0F 2) S1_GND S2_GND S3_GND S4_GND S5_GND PP_LDO4_VDDA_3V3 PP_LDO5_GPS_LNA_2V5 PP_LDO1 REF_BYP PP_LDO3_AMUX_1V8 PP_LDO2_XO_HS_1V8 S5_GND PP_SMPS5_DSP_1V05 S4_GND S3_GND S2_GND S1_GND PP_LVS1 PP_VREG PP_SMPS4_RF2_2V05 PP_SMPS3_MSME_1V8 PP_SMPS5_DSP_1V05 PP_LDO6_RUIM_1V8 PP_LDO14_2V65 PP_LDO13_VDDPX_2V95 PP_LDO7_DAC_1V8 PP_LDO8_VDDPX_1V2 PP_LDO12_MDSP_SW_1V05 PP_LDO9_PLL_1V05 PP_LDO11_MDSP_FW_1V05 PP_LDO10_ADSP_1V05 PP_SMPS1_MSMC_1V05 PP_VSW_S1 REF_GND PP_VSW_S2 PP_SMPS2_RF1_1V3 PP_VSW_S3 =PPBATT_VCC_BB PP_SMPS4_RF2_2V05 PP_SMPS3_MSME_1V8 PP_VSW_S5 PP_VSW_S4 051-0886 A.0.0 32 OF 121 25 OF 54 2 1 2 1 2 1 2 1 2 1 21 2 1 2 1 1 2 21 2 1 2 1 21 21 2 1 2 1 2 1 2 1 21 2 1 98 24 88 82 87 48 42 90 20 76 105 13 77 54 63 17 11 84 32 31 29 23 43 55 65 53 8 101 89 95 104 70 58 75 5 78 44 64 59 34 28 100 12 81 18 6 92 97 79 83 1022 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 25 26 25 26 25 26 25 26 25 26 52 25 26 25 26 25 26 25 26 25 26
- 27. IN OUT MPP_06 MPP_05 MPP_04 MPP_03 MPP_02 MPP_01 GPIO_06 GPIO_05 GPIO_04 GPIO_03 GPIO_02 GPIO_01 (SYM 4 OF5) MPP MISC NC NC NC NC NC NC NC NC BI IN IN IN IN GND_S3 GND_S2 GND_S1 GND_S4 GND_S5 GND VCOIN (SYM 3 OF 5) INPUT PWR NC OPT_1 PM_RESIN_N KPD_PWR* BAT_ID LED_DRV_N OPT_2 PM_MDM_INT_N PM_USR_INT_N PON_RESET* PON_TRIG SSBI PS_HOLD (SYM 1 OF 5) CONTROL NC NC OUT OUT NC OUT IN NC NC OUT IN OUT OUT GND0 XTAL_32K_OUT XTAL_32K_IN XTAL_19M_OUT XTAL_19M_IN XOADC_GND XO_THERM XO_OUT_D0_EN XO_OUT_D0 XO_OUT_A1 XO_OUT_A0 SLEEP_CLK RSVD GND1 (SYM 2 OF 5) CLOCKS IN CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PMU (2 OF 2) 1 (1.8V) 0 (NC, PD) BB GPIO_29 JXX NXX BOARD_ID 1.3V 1.1V PRODUCT_ID PROTO1 PA_ID 0.3V 0.5V 1.1V 7.5 7.6 7.7 8.7 8.6 8.5 TO MINIMIZE THERMAL DRIFT GND NEEDS TO BE CLEARED UNDER THIS CRYSTAL 1.3V 0.1V AP SECTION NEEDS ITS OWN THERMISTOR PLACED NEAR THE PA’S. PVT DVT PROTO2 PROTO2 MAV VER 1.7V 1.5V EVT2 EVT1 0.7V 0.9V REVISION 1.5V1.5V 28 27 BGA CRITICAL PM8018-0 U3300 1% MF 01005 1/32W 100K R3304 1/32W 100K MF 1% 01005 R3305 2427 52452 28 244852 52452 20.0K 5% 01005 MF 1/32W R3301 1.00K 1/32W 01005 5% MF R3300 PM8018-0 BGA U3300 SM XW3304 SHORT-10L-0.25MM-SM XW3303 SM XW3302 SHORT-10L-0.25MM-SM XW3301 SM XW3300 PM8018-0 BGA U3300 28 28 24 27 252627 19.200MHZ 2.0X1.6-SM CRITICAL Y3300 24 27 27 24 27 29 SHORT-10L-0.1MM-SM XW3305 100K MF 1/32W 1% 01005 R3303 X5R-CERM 01005 10% 6.3V 1000PF C3300 PM8018-0 BGA U3300 MF 1/32W 1% 499K 01005 R3307 1% MF 1/32W 01005 100K R3306 252627 CELL: BASEBAND PMU (2 OF 2) VREF_DAC_BIAS VDDPX_BIAS GPIO_SOC2BB_RST_L S3_GND S4_GND S5_GND S1_GND S2_GND PMIC_SSBI PS_HOLD_PMIC PMU_GPIO_PMU2BBPMU_RST_L GPIO_SOC2BB_RADIO_ON_L PM_USR_IRQ_L PM_MDM_IRQ_L PMIC_RESOUT_L PP_LDO3_AMUX_1V8 19P2M_XTAL_OUT 19P2M_MDM 19P2M_CLK_EN SLEEP_CLK_32K 19P2M_XTAL_IN 19P2M_WTR XO_THERM_Y1 XO_GND PS_HOLD BOARD_ID PA_ID PP_LDO3_AMUX_1V8 051-0886 A.0.0 33 OF 121 26 OF 54 80 73 72 66 67 85 49 71 60 50 38 33 1 2 1 2 1 2 1 2 56 30 96 103 91 36 93 99 94 39 51 61 46 52 40 57 1 2 21 1 2 21 1 2 62 16 69 35 86 74 14 21 4 41 68 47 3 24 1 2 1 1 2 2 1 27 15 3 2 1 22 10 9 25 37 19 26 7 45 1 2 1 2 25 25 25 25 25 2452
- 28. IN NC EBI2_AD_0 EBI2_AD_1 EBI2_AD_6 EBI2_AD_5 EBI2_AD_7 EBI1_CAL EBI2_CLE* EBI2_ALE* EBI2_AD_2 EBI2_AD_3 EBI2_AD_4 EBI2_NAND_CS* EBI2_BUSY* EBI2_OE* EBI2_WE* (2 OF 6) EBI1_EBI2 NC NC NC NC NC NC NC NC IN NC NC NC NC IN IN IN IN VDD_MDSP_SW GND VDD_A1 VDD_A1 GND GND VDD_A2 VDD_A2 VDD_ADSP VDD_CORE VDD_DDR VDD_MDSP_FW VDD_MEM VDD_P1 VDD_P3 VDD_PLL1 VDD_P7 VDD_P4 VDD_P5 VDD_P6 VDD_QFUSE_PRG VDD_USB_3P3 VDD_USB_1P8 VDD_HVPAD_BIAS VDD_P2 VDD_PLL2 PWR (5OF 6) IN IN IN IN IN IN BI BI NC TCK RTCK MODE_1 MODE_0 CXO CXO_EN SDC1_DATA3 SDC1_DATA2 SDC1_CLK SDC1_DATA1 SDC1_DATA0 SDC1_CMD USB_HS_DM USB_HS_ID USB_HS_VBUS USB_HS_SYSCLK TDI HSIC_CAL USB_HS_REXT DNC TMS USB_HS_DP DNC TDO RESIN* TRST* RESOUT* HSIC_DATA HSIC_STB SRST* SLEEP_CLK SSBI_PMIC DIGITAL (1 OF 6) NC NC NC NC NC NC NC IN NC NC NC NC NC NC NC IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN BI OUT IN IN IN IN IN IN IN IN IN GND GND GND_ANA GND (6 OF 6) NC BI BI OUT OUT NC CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT BASEBAND (1 OF 2) CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST. 2527 BGA MDM9615M U3400 25 0201-1 1.0UF X5R 6.3V 20% C3420 1.0UF X5R 6.3V 20% 0201-1 C3433 2527 25 26 0201 0.22UF 20% 6.3V X5R C3434 MF 1/32W 01005 1% 240 R3403 25 242527283052 BGA MDM9615M U3400 24 25 27 28 30 52 1.0UF 20% 6.3V X5R 0201-1 C3426 0201-1 6.3V X5R 20% 1.0UF C3424 24 25 27 28 30 52 25 27 24 25 27 28 30 52 10 24 25 52 200 1% MF 01005 1/32W R3401 24 48 52 24 24 MDM9615M BGA U3400 25 27 25 27 X5R 0.1UF 01005 4V 20% NOSTUFF C3423 0201-1 20% X5R 1.0UF 6.3V C3425 25 30 252752 26 6.3V 20% X5R 1.0UF 0201-1 C3422 0201-1 1.0UF 6.3V X5R 20% C3411 0201-1 X5R 6.3V 1.0UF 20% C3412 0201-1 X5R 20% 1.0UF 6.3V C3415 252752 25 27 25 27 MF 1/32W 5% 470K 01005 R3400 25 25 27 24 25 27 28 30 52 0201-1 X5R 6.3V 20% 1.0UF C3416 0201-1 1.0UF X5R 6.3V 20% C3417 0201-1 6.3V X5R 1.0UF 20% C3421 242527283052 2527 252752 0201-1 X5R 20% 6.3V 1.0UF C3405 242527 283052 0201-1 1.0UF 6.3V 20% X5R C3406 0201-1 6.3V X5R 1.0UF 20% C3400 0201-1 20% X5R 6.3V 1.0UF C3401 0201-1 1.0UF 6.3V X5R 20% C3407 0201-1 1.0UF X5R 6.3V 20% C3408 X5R 0201-1 1.0UF 6.3V 20% C3402 0201-1 1.0UF 6.3V 20% X5R C3403 X5R 0201-1 6.3V 20% 1.0UF C3409 0201-1 1.0UF 6.3V X5R 20% C3404 2527 2527 0201-1 20% X5R 6.3V 1.0UF C3413 0201-1 20% 1.0UF 6.3V X5R C3414 2527 2527 20% 6.3V X5R 1.0UF 0201-1 C3431 0201-1 20% 6.3V 1.0UF X5R C3418 0201-1 6.3V 20% X5R 1.0UF C3419 20% 0.22UF 6.3V X5R 01005 C3432 2426 26 2426 52452 25 52452 52452 52452 2426 2452 2426 0201-1 20% 6.3V X5R 1.0UF C3410 CRITICAL BGA MDM9615M U3400 4 24 53 4 24 53 24 52 5 24 52 01005 240 1% 1/32W MF R3402 CELL: BASEBAND (1 OF 2) PP_SMPS1_MSMC_1V05 PP_SMPS1_MSMC_1V05 PP_LDO7_DAC_1V8 PP_LDO9_PLL_1V05 PP_LDO3_AMUX_1V8 PP_LDO4_VDDA_3V3 VDDPX_BIAS PP_LDO2_XO_HS_1V8 PP_SMPS2_RF1_1V3 PP_LDO12_MDSP_SW_1V05 PP_LDO11_MDSP_FW_1V05 PP_LDO10_ADSP_1V05 PP_SMPS3_MSME_1V8 PP_LVS1 PP_SMPS3_MSME_1V8 PP_SMPS3_MSME_1V8 PP_LDO9_PLL_1V05 PP_SMPS1_MSMC_1V05 PP_LDO10_ADSP_1V05 PP_LDO12_MDSP_SW_1V05 PP_LDO8_VDDPX_1V2 PP_LDO11_MDSP_FW_1V05 SLEEP_CLK_32K BB_JTAG_TDI BB_JTAG_TRST_L DEBUG_RST_L PMIC_RESOUT_L PMIC_SSBI TP_BB_TEST_MODE_1 BB_JTAG_TCK BB_JTAG_TMS 19P2M_CLK_EN TP_BB_TEST_MODE_0 HSIC2_BB_STB BB_JTAG_RTCLK BB_JTAG_TDO HSIC2_BB_DATA 50_HSIC_CAL PP_LDO4_VDDA_3V3 EBI1_CAL PP_LDO13_VDDPX_2V95 PP_SMPS3_MSME_1V8 PP_LDO9_PLL_1V05 PP_SMPS3_MSME_1V8 PP_LDO6_RUIM_1V8 PP_SMPS3_MSME_1V8 PP_LDO8_VDDPX_1V2 PP_SMPS3_MSME_1V8 RREFEXT USB_BB_DEBUG_N USB_BB_DEBUG_P PMU_GPIO_BB_VBUS_DET 19P2M_MDM 051-0886 A.0.0 34 OF 121 27 OF 54 J20 J19 H21 H19 E21 C21 C20 E20 G19 H20 J21 D21 D19 E19 D20 2 1 2 1 2 1 1 2 F20 N17 N16 N15 T19 F13 J8 AA15 AA7 W9 AA11 AA18 U6 U7 C5 C6 E6 E7 F5 F12 F14 F8 F9 G12 G9 H12 H9 J12 J13 J9 K12 K13 K8 K9 L12 L13 L8 L9 M12 M13 M8 M9 N12 N13 N8 N9 P12 P9 R12 R9 T8 T9 AA20 B19 M20 T15 T16 T17 U14 U15 U16 U17 U19 N19 P15 P16 P17 P19 C17 C18 E17 F17 G13 G14 G7 G8 H13 H14 H7 H8 P13 P14 P7 P8 R13 R14 R7 R8 A14 A19 F21 M1 M21 A15 G1 G21 L1 U1 W19 K17 L17 A11 A2 A3 A7 B13 E10 E12 E16 K21 W12 2 1 2 1 1 2 Y3 Y2 Y19 W20 V20 U21 N21 N20 L21 L20 L19 K19 E11 C12 C10 B12 AA2 A8 A12 E9 C9 B9 B10 A10 E8 C8 W4 C11 A9 AA3 Y20 AA4 U20 C7 B8 Y4 AA19 Y21 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 T11 T7 L16 K16 U2 V19 A21 AA1 L15 M15 M16 R16 R15 N14 P6 P11 F7 F6 U13 AA21 B11 B14 B15 B2 B7 C19 F10 F15 F16 F19 G10 G11 G15 G16 G17 G2 G20 G6 H10 H11 H15 H16 H6 J10 J11 J14 J15 J6 J7 K10 K11 K14 K15 K20 K6 K7 L10 L11 L14 L2 L6 L7 M10 M11 M14 M17 M19 M6 M7 N10 N11 N6 N7 P10 R10 R11 R17 R19 R6 T10 T12 T13 T14 F11 J16 T6 U12 U9 W14 W7 Y11 Y15 Y18 Y7 W13 1 2 52 52
- 29. IN OUT IN IN OUT OUT OUT OUT IN OUT OUT OUT OUT OUT OUT OUT OUT OUT BI OUT OUT BI OUT OUT OUT IN IN IN OUT OUT IN OUT OUT IN OUT OUT OUT IN IN OUT IN OUT OUT IN IN GND VCC SI/SIO0 WP*/SIO2 SCLK CS* NC/SIO3 NC SO/SIO1 OUT IN OUT IN OUT OUT BBRX_QP_CH1 BBRX_QP_CH0 TX_DAC0_QP BBRX_IP_CH1 BBRX_IM_CH0 TX_DAC0_IREF DAC0_VREF GNSS_BB_QP GNSS_BB_IP BBRX_IP_CH0 GNSS_BB_QM GNSS_BB_IM BBRX_QM_CH1 BBRX_QM_CH0 TX_DAC0_IMBBRX_IM_CH1 TX_DAC1_IP TX_DAC1_IM DNC BBRX_QP_CH2 BBRX_QM_CH2 BBRX_IM_CH2 TX_DAC0_QM TX_DAC0_IP TX_DAC1_QM TX_DAC1_QP BBRX_IP_CH2 ANALOG (4 OF 6) (3OF 6) GPIO GPIO_9 GPIO_8 GPIO_20 GPIO_15 GPIO_23 GPIO_7 GPIO_2 GPIO_1 GPIO_85 GPIO_17 GPIO_24 GPIO_18 GPIO_22 GPIO_21 GPIO_5 GPIO_6 GPIO_3 GPIO_0 GPIO_84 GPIO_13 GPIO_12 GPIO_16 GPIO_19 GPIO_86 GPIO_87 GPIO_4 GPIO_80 GPIO_82 GPIO_83 GPIO_81 GPIO_11 GPIO_10 GPIO_14 GPIO_78 GPIO_79 GPIO_70 GPIO_77 GPIO_69 GPIO_71 GPIO_66 GPIO_67 GPIO_68 GPIO_64 GPIO_65 GPIO_62 GPIO_60 GPIO_63 GPIO_61 GPIO_56 GPIO_59 GPIO_58 GPIO_57 GPIO_53 GPIO_55 GPIO_49 GPIO_52 GPIO_54 GPIO_50 GPIO_51 GPIO_47 GPIO_46 GPIO_43 GPIO_48 GPIO_27 GPIO_25 GPIO_44 GPIO_42 GPIO_45 GPIO_41 GPIO_28 GPIO_26 GPIO_39 GPIO_38 GPIO_36 GPIO_40 GPIO_29 GPIO_30 GPIO_35 GPIO_37 GPIO_34 GPIO_31 GPIO_33 GPIO_32 GPIO_72 GPIO_75 GPIO_74 GPIO_73 GPIO_76 NC IN NC NC NC NC NC NC NC NC IN NC NC NC NC NC NC NC NC NC NC IN NC NC NCNC NC NC NC NC NC NC IN NC NC NC NC NC NC NC NC NC NC IN NC NC IN IN NC NC NC OUT NC NC NC NC IN OUT BI OUT OUT OUT OUT OUT OUT OUT BI OUT OUT OUT OUT BI OUT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PRODUCT_ID JXX NXX0 (NC, PD) 1 (1.8V) GPIO_29 RESERVED FOR FUTURE PRODUCT ID USE GRFC_0 GRFC_39 GRFC_38 GRFC_10 GRFC_13 GRFC_9 GRFC_5 GRFC_6 GRFC_2 GRFC_37 GRFC_28 GRFC_21 GRFC_22 GRFC_24 GRFC_26 GRFC_36 GRFC_35 GRFC_4 GRFC_8 GRFC_18 GRFC_3 GRFC_11 GRFC_25 LAT_SW3_CTL BOOT_CONFIG_0 GRFC_7 GRFC_1 GRFC_20 GRFC_19 GRFC_15 GRFC_14 BOOT_CONFIG_6 BOOT_CONFIG_4 GRFC_33 GRFC_27 BASEBAND (2 OF 2) BOOT_CONFIG_5 GRFC_34 BOOT_CONFIG_3 BOOT_CONFIG_2 WLAN_TX_BLANK NEEDS TO CONNECT TO AP BOOT_CONFIG_1 GRFC_23 GRFC_29 GRFC_30 GRFC_31 GRFC_32 01005 20% X5R 4V 0.1UF C3520 5 24 524 524 5112452 5112452 5 24 34 38 01005 20% 0.1UF 4V X5R C3500 102452 2429 2429 26 26 38 5 33 34 35 36 37 36 3233 24 29 5 5 24 29 26 29 24 48 52 24 44 52 29 33343536 33 24 44 24 44 38 29 14 24 52 37 37 29 552 24 29 5 24 24 29 242527283052 CRITICAL WLCSP MX25U1635EBAI-10G SERIAL-SPI-2MX8-1.8V U3520 5 29 35 29 33 33 CRITICAL MDM9615M BGA U3400 MDM9615M CRITICAL BGA U3400 01005-1 70-OHM-300MA L3520 29 29 29 29 29 0.00 0% 01005 MF 1/32W R3530 1/32W MF 0% 0.00 01005 R3531 19 44 52 194452 39 242527283052 01005 10K 5% 1/32W MF R3502 14 52 102452 102452 102452 29 29 29 29 29 29 24 39 40 24 33 39 40 33 39 40 26 39 40 39 CELL: BASEBAND (2 OF 2) GPIO_BB2SOC_RESET_DET_L PM_MDM_IRQ_L HSIC2_SOC2BB_HOST_RDY HSIC2_BB2SOC_DEVICE_RDY OSCAR_CONTEXT_B_MDM WLAN_TX_BLANK WTR_GP_DATA1 GPH GPHWTR_GP_DATA0 BB_ERROR_FLAG PP_SMPS3_MSME_1V8_FILT OSCAR_CONTEXT_A_MDM ANT_SEL_2 TX_BB_I_P TX_BB_I_N TX_BB_Q_P SIMCRD_CLK_CONN SIMCRD_RST_CONN SPI_CS_L PP_SMPS3_MSME_1V8 SPI_DATA_MOSI OSCAR2RADIO_CONTEXT_B PRX_BB_I_P PRX_BB_I_N PRX_BB_Q_P PRX_BB_Q_N DRX_BB_I_P 3P4T_SEL_0 DRX_BB_I_N PA_ON_B7_B20 DRX_BB_Q_P BB_IPC_GPIO PP_SMPS3_MSME_1V8 DRX_BB_Q_N GPS_BB_I_P GPIO_DEBUG_LED GPIO_SOC2BB_WAKE_MODEM GPS_BB_I_N GSM_PA_HB_EN GSM_PA_LB_EN GPS_BB_Q_P BB_PDM UART_BB2WLAN_LTE_COEX UART_WLAN2BB_LTE_COEX PA_MB_CTL1 PA_BS GPS_BB_Q_N PMU_GPIO_BB2PMU_HOST_WAKE WTR_BB_TX_DAC_IREF VREF_DAC_BIAS WTR_SSBI_PRX_DRX HSIC2_BB2SOC_REMOTE_WAKE GPIO_BB2SOC_GPS_SYNC WTR_SSBI_TX_GPS SPI_CLK PA_MB_CTL0 PA_ON_B5_B8 PS_HOLD PM_USR_IRQ_L WTR_RX_ON WTR_RF_ON SIM_TRAY_DETECT SPI_CS_L PA_ON_B2_B3 SPI_DATA_MISO UART3_SOC2BB_TX UART3_BB2SOC_TX UART3_SOC2BB_RTS_L UART3_BB2SOC_RTS_L SPI_DATA_MOSI OSCAR2RADIO_CONTEXT_A ANT_SEL_1 SPI_CLK B40_FILT_SELECT LAT_SW1_CTL ANT_SEL_3 GPIO_BB2SOC_GSM_TXBURST PA_R1 DCDC_MODE ANT_SEL_0 GPIO_51 DCDC_EN 3P4T_SEL_1 ANT_SEL_4 LAT_SW2_CTL TX_BB_Q_N SPI_DATA_MISO SIMCRD_IO_CONN PP_SMPS3_MSME_1V8 051-0886 A.0.0 35 OF 121 28 OF 54 2 1 2 1 E3B2 E2 D3 D2 A4 B3 C2 F1 F4 C3 Y9 Y8 Y5 Y10 W8 W6 W5 W11 W10 U8 U11 U10 AA9 AA8 AA6AA10 Y14 AA14 Y17 V21 H17 AA17 AA16 AA12 W15 W16 W18 AA5 Y6 AA13 Y13 W21 Y12 Y16 J17 W17 A13 A16 A17 A18 A20 A4 A5 A6 B1 B16 B17 B18 B20 B21 B3 B4 B5 B6 C1 C13 C14 C15 C16 C2 C3 C4 D1 D2 D3 E1 E13 E14 E15 E2 E3 F1 F2 F3 G3 G5 H1 H2 H3 H5 J1 J2 J3 J5 K1 K2 K3 K5 L3 L5 M2 M3 M5 N1 N2 N3 N5 P1 P2 P20 P21 P3 P5 R1 R2 R20 R21 R3 R5 T1 T2 T20 T21 T3 T5 U3 U5 V1 V2 V3 W1 W2 W3 Y1 21 1 2 1 2 1 2 28 28 28 28 28 28 28 28 242527283052
- 30. IN IN IN IN OUT GP_DATA0 GP_DATA1 GP_DATA2 DNC DNC XO_IN SSBI_TX_GNSS SSBI_PRX_DRX RF_ON RX_ON RBIAS VTUNE_PRX PDET_IN DNC TX_HB TX_MB4 TX_MB3 TX_MB2 TX_MB1 TX_BB_IM TX_BB_IP TX_LB4 TX_LB2 TX_LB3 TX_LB1 GND DNC DAC_REF TX_BB_QM TX_BB_QP SYM 2 OF5 TX NC NC NC NC NC NC NC PRX_LB1_INP PRX_LB1_INM PRX_LB2_INM PRX_LB3_INP PRX_LB3_INM PRX_MB1_INP PRX_BB_IP PRX_BB_QP PRX_BB_IM DNC PRX_BB_QM PRX_HB_INM PRX_MB3_INM PRX_HB_INP PRX_MB3_INP PRX_MB2_INM PRX_MB2_INP PRX_MB1_INM PRX_LB2_INP SYM 3 OF 5 PRX IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT IN OUT OUT OUT OUT GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND SYM 5 OF 5 GND IN BI BI IN OUT OUT IN OUT OUT IN IN IN IN IN IN IN IN IN DRX_LB1_INM DRX_LB1_INP GNSS_INM GNSS_INP DRX_HB_INM DRX_HB_INP DRX_MB_INM DRX_MB_INP DRX_LB2_INM DRX_LB2_INP DRX_BB_IM DRX_BB_IP DRX_BB_QM DRX_BB_QP GNSS_BB_QP GND GNSS_BB_QM GNSS_BB_IP GNSS_BB_IM DRX_GPS SYM 1 OF 5 OUT OUT OUT OUT OUT OUT OUTIN IN OUT IN IN IN IN IN IN IN Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST 9.0 DB ATTENUATOR RF TRANSCEIVER (1 OF 2) TRANSCEIVER GROUND CONNECTIONS TRANSCEIVER PHASE CONTROL, TX RF & IQ PORTS DRX TRANSCEIVER RF AND IQ PORTS PRX TRANSCEIVER RF AND IQ PORTS 40 31 31 26 100PF 16V 5% NP0-C0G 01005 C3600 01005 0% 1/32W 0.00 MF R3604 10PF 16V CERM 01005 5% NOSTUFF C3601 32 WTR1605 SM CRITICAL U3600 NP0-C0G 5% 01005 56PF 16V C3602 1% MF 105 1/32W 01005 R3603 01005 105 1% 1/32W MF R3601 1/32W 1% 61.9 MF 01005 R3602 WTR1605 SM CRITICAL U3600 31 31 31 40 31 31 31 31 31 28 28 28 28 40 28 28 28 28 WTR1605 SM CRITICAL U3600 40 2428 2428 2428 28 28 40 28 28 2428 28 40 28 28 28 28 28 28 SM WTR1605 CRITICAL U3600 37 32 32 32 32 37 3231 31 32 1% 4.75K 01005 MF 1/32W R3600 35 40 40 40 40 31 31 CELL: RF TRANSCEIVER (1 0F 2) 100_XCVR_B2_PRX_N 50_XCVR_B1_B3_TX 50_XCVR_B34_B39_TX 50_XCVR_2G_HB_TX 50_XCVR_B7_B38_B40_TX 50_PDET_IN 100_XCVR_GPS_RX_N 100_XCVR_B1_B34_B39_DCS_PRX_N 100_XCVR_B1_B34_B39_DCS_PRX_P 19P2M_WTR 100_XCVR_B3_PRX_N 100_XCVR_B3_PRX_P 100_XCVR_GPS_RX_P 100_XCVR_B5_B18_PRX_N 100_XCVR_B2_PRX_P 100_XCVR_B5_B18_PRX_P 100_XCVR_B8_PRX_P 100_XCVR_B8_PRX_N GPS_BB_Q_N GPS_BB_Q_P GPS_BB_I_N GPS_BB_I_P 100_XCVR_B7_B38_B40_DRX_N DRX_BB_Q_P DRX_BB_Q_N DRX_BB_I_N DRX_BB_I_P 100_XCVR_B7_B38_B40_DRX_P WTR_SSBI_PRX_DRX WTR_SSBI_TX_GPS WTR_RF_ON PRX_BB_Q_N PRX_BB_Q_P 100_XCVR_B1_B2_B3_B34_B39_DRX_N PRX_BB_I_N PRX_BB_I_P WTR_RX_ON GPHWTR_GP_DATA1 100_XCVR_B1_B2_B3_B34_B39_DRX_P WTR_BB_TX_DAC_IREF GPHWTR_GP_DATA0 TX_BB_Q_P TX_BB_Q_N TX_BB_I_N TX_BB_I_P 50_XCVR_B2_TX 50_XCVR_B20_TX100_XCVR_B20_PRX_N 100_XCVR_B20_PRX_P 50_PDET_PAD_IN 100_XCVR_B8_B20_DRX_P 100_XCVR_B8_B20_DRX_N 100_XCVR_B5_B18_DRX_P 100_XCVR_B5_B18_DRX_N 100_XCVR_B7_B38_B40_PRX_P 100_XCVR_B7_B38_B40_PRX_N 50_XCVR_B5_B18_TX 50_XCVR_B8_TX 50_XCVR_2G_LB_TX 50_PDET_PAD_OUT 19P2M_WTR_FILT_IN 19P2M_WTR_IN WTR_RBIAS 051-0886 A.0.0 36 OF 121 29 OF 54 1 2 1 2 2 1 105 121 88 114 96 120 89 80 100 45 60 79 101 93 103 95 112 119 126 138 130 133 132 141 140 134 90 109 139 131 1 2 1 2 1 2 1 2 78 69 54 48 43 36 84 91 92 86 82 15 16 7 8 17 23 30 61 21 20 33 75 9 49 32 19 113 128 104 107 135 106 137 122 94 115 102 129 99 110 123 125 124 52 39 68 47 77 46 142 35 81 64 34 73 59 74 58 41 38 6 27 29 22 14 5 18 10 11 2 12 3 13 4 72 63 57 50 70 1 71 56 62 1 2
- 31. ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS ALIAS VDD_RF1_P_FELO VDD_RF1_P_FELO VDD_RF1_D_LBLO VDD_RF1_D_FE VDD_RF2_P_BB VDD_DIO VDD_RF1_T_SYN VDD_RF2_T_VCO VDD_RF2_XO VDD_RF1_T_LO VDD_RF2_T_BB VDD_RF1_T_DA VDD_RF1_T_UPC VDD_RF2_T_DA VDD_RF2_D_BB VDD_RF1_S_PLL VDD_RF1_S_VCO VDD_RF1_P_VCO VDD_RF1_P_PLL VDD_RF2_S_VCO VDD_RF2_P_VCO VDD_RF1_G_BB VDD_RF1_G_PLL VDD_RF1_G_VCO VDD_RF1_G_LNA VDD_RF2_T_PLL VDD_RF1_D_MBLO VDD_RF1_JDET SRM 4 OF5 PWR Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST PLACE NEAR U3.117 PLACE NEAR U3.118 RF2_2V05 STAR ROUTING PLACE NEAR U3.76 PLACE NEAR U3.66 RF1_1V8 STAR ROUTING STAR ROUTING PLACE NEAR U3.37 AND U3.55 PLACE NEAR U3.25 AND U3.28 STAR ROUTING PLACE NEAR U3.53 AND U3.26 PLACE NEAR U3.42 STAR ROUTING PLACE NEAR U3.98 TRANSCEIVER POWER CONNECTIONS PLACE NEAR U3.111 PLACE NEAR U3.67 PLACE NEAR U3.51 STAR ROUTING STAR ROUTING PLACE NEAR U3.127 PLACE NEAR U3.136 STAR ROUTINGSTAR ROUTING STAR ROUTING PLACE NEAR U3.116 PLACE NEAR U3.65 PLACE NEAR U3.24 AND U3.31 RF1_1V3 PLACE NEAR U3.40 STAR ROUTING STAR ROUTING RF1_1V3 RF TRANSCEIVER (2 OF 2) PLACE NEAR U3.87 X5R-CERM 6.3V 0.1UF 01005 20% C3702 20% 0.1UF 01005 6.3V X5R-CERM C3703 20% 6.3V 01005 X5R-CERM 0.1UF C3704 0.1UF X5R-CERM 6.3V 01005 20% C3705 NOSTUFF 6.3V 0.1UF 01005 X5R-CERM 20% C3706 20% 01005 6.3V 0.1UF X5R-CERM C3707 0.1UF X5R-CERM 20% 6.3V 01005 C3708 100PF NP0-C0G 01005 5% 16V C3709 20% 01005 6.3V 0.1UF X5R-CERM C3710 20% 6.3V 0.1UF X5R-CERM 01005 C3711 6.3V X5R-CERM 20% 01005 0.1UF C3712 01005 20% 6.3V X5R-CERM 0.1UF C3713 01005 6.3V 20% X5R-CERM 0.1UF C3714 10UF 20% 0402-1 X5R-CERM 10V C3715 10V 1.0UF 0201-1 X5R-CERM 20% C3700 X5R-CERM 10UF 10V 20% 0402-1 C3701 20% 0.1UF X5R-CERM 01005 6.3V C3717 20% X5R-CERM 0.1UF 6.3V 01005 C3718 0.1UF 20% 6.3V 01005 X5R-CERM C3719 20% X5R-CERM 0.1UF 01005 6.3V C3720 NOSTUFF 16V NP0-C0G 100PF 5% 01005 C3716 MF 1/20W 201 0 5% R3702 16V NP0-C0G 5% 56PF 01005 C3721 22-OHM-25%-1800MA 0201 R3700 CRITICAL SM WTR1605 U3600 CELL: RF TRANSCEIVER (2 OF 2) PP_RF1_1V3_TX_UPCONVERTER PP_SMPS4_RF2_2V05_FILTPP_SMPS4_RF2_2V05 PP_RF2_2V05_TX_PLL PP_RF1_1V3_JAM_DET PP_RF1_1V3_TX_SYNTH PP_RF2_2V05_TX_PLL PP_RF1_1V3_GPS_LNA PP_RF1_1V3_GPS_VCO PP_RF1_1V3_GPS_PLL PP_RF1_1V3_GPS_DIG PP_RF2_2V05_PRX_VCO PP_RF2_2V05_SHDR_VCO PP_RF1_1V3_PRX_PLL PP_RF1_1V3_PRX_VCO PP_RF1_1V3_SHDR_VCO PP_RF1_1V3_SHDR_PLL PP_RF2_2V05_DRX_BB PP_RF2_2V05_TX_DA PP_RF1_1V3_TX_UPCONVERTER PP_RF1_1V3_TX_DA PP_RF2_2V05_TX_BB PP_RF1_1V3_TX_LO PP_RF2_2V05_XO_FILT PP_RF2_2V05_TX_VCO PP_RF1_1V3_TX_SYNTH PP_RF1_1V8_DIG PP_RF1_1V3_PRX_FELO1 PP_RF1_1V3_DRX_FE PP_RF1_1V3_JAM_DET PP_RF2_2V05_PRX_BB PP_RF1_1V3_DRX_LBLO PP_RF1_1V3_DRX_MBLO PP_RF2_2V05_XO_FILT PP_RF2_2V05_TX_VCO PP_RF2_2V05_SHDR_VCO PP_RF2_2V05_PRX_VCO PP_RF2_2V05_PRX_BB PP_RF2_2V05_TX_DA PP_RF2_2V05_DRX_BB PP_RF1_1V3_GPS_DIG PP_RF1_1V3_GPS_PLL PP_SMPS2_RF1_1V3_FILT PP_RF1_1V8_DIGPP_SMPS3_MSME_1V8 PP_RF1_1V3_PRX_PLL PP_RF1_1V3_SHDR_PLL PP_RF1_1V3_PRX_VCO PP_RF1_1V3_SHDR_VCO PP_RF1_1V3_TX_LO PP_RF1_1V3_PRX_FELO1 PP_RF1_1V3_DRX_FE PP_RF1_1V3_PRX_FELO2 PP_RF1_1V3_DRX_LBLO PP_RF1_1V3_DRX_MBLO PP_RF1_1V3_GPS_VCO PP_RF1_1V3_TX_DA PP_RF1_1V3_GPS_LNA PP_RF2_2V05_TX_BB PP_RF1_1V3_PRX_FELO2 PP_SMPS2_RF1_1V3 PP_SMPS2_RF1_1V3_FILT 051-0886 A.0.0 37 OF 121 30 OF 54 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 21 53 42 28 26 83 87 98 136 127 116 108 118 117 111 44 65 40 76 66 51 67 31 55 37 24 97 25 85 30 2552 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 2425272852 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 25 27 30
- 32. OUT OUT BAL_PORT2 GND BAL_PORT1 UNBAL_PORT IN BIANTB40 B38 GND OUT BI BI BI OUT BI GND UNB_PORT2 UNB_PORT1 IN OUT OUT IN IN OUT OUT OUT OUT IN IN IN IN IN OUT OUT IN IN OUT OUT Apple Inc. THEINFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST RX MATCHING 29 NO_XNET_CONNECTION=TRUE +/-0.05PF 01005 CERM 16V 0.6PF C3800 01005 22NH-5%-0.1A NOSTUFF L3823 0201 3.6NH+/-0.1NH-400MA L3814 29 LLP 2.3-2.69GHZ CRITICAL U3803 NO_XNET_CONNECTION=TRUE 5% NP0-C0G 01005 16V 27PF C3801 33 39 ACFM-2043-AP1 LGA FIL_DIPLEXER_B38_B40 CRITICAL U3801 29 33 33 201 5% 0 MF 1/20W L3817 33 29 39 201 0 5% 1/20W MF L3821 01005 NP0-C0G 16V 56PF 5% NOSTUFF C3811 0201 0.6NH+/-0.1NH-0.85A L3813 0.6NH+/-0.1NH-0.85A 0201 L3815 18NH-3%-140MA 01005 L3822 01005 18NH-3%-140MA L3824 0201 5.6NH-3%-0.35A CRITICAL C3810 0201DS 13NH-5%-0.28A CRITICAL L3800 0201DS 6.8NH-5%-0.5A CRITICAL L3801 0201DS 8.7NH-5%-0.29A CRITICAL L3802 0201DS 5.6NH-5%-0.33A CRITICAL L3803 TX-BAND40-LTE SAFEA2G35MB0F57 LGA CRITICAL U3802 0201 8.2NH+/-3%-0.25A-0.7OHM L3808 8.2NH+/-3%-0.25A-0.7OHM 0201 L3809 10NH-3%-140MA 01005 L3810 10NH-3%-140MA 01005 L3812 01005 18NH-3%-140MA L3811 22NH-5%-0.1A 01005 L3807 9.1NH-3%-220MA 0201 CRITICAL C3808 6.8NH-3%-0.3A 0201 CRITICAL C3809 0.7NH-0.8A 0201 CRITICAL L3805 0.7NH-0.8A 0201 CRITICAL L3806 5.6NH-3%-0.35A 0201 CRITICAL L3804 0201 3.3NH+/-0.1NH-0.45A CRITICAL L3820 01005 2.7NH+/-0.1NH-200MA CRITICAL L3819 25V +/-0.1PF 0.4PF C0G-CERM 201 CRITICAL L3825 0201 2.0NH+/-0.1NH-0.6A CRITICAL L3840 34 29 29 35 35 29 29 29 29 36 36 36 36 33 29 29 33 34 29 01005 NO_XNET_CONNECTION=TRUE 5% 16V NP0-C0G 27PF C3804 16V 5% 01005 27PF NP0-C0G C3806 27PF 5% 16V NP0-C0G 01005 C3807 29 +/-0.05PF CERM 01005 16V 0.9PF C3802 16V 01005 1.2PF NP0-C0G-CERM +/-0.05PF C3805 +/-0.05PF 1.2PF NO_XNET_CONNECTION=TRUE NP0-C0G-CERM 16V 01005 C3803 CELL: RX MATCHING 50_B3_DUPLX_RX 100_XCVR_B2_PRX_N 50_3P4T_PRX_OUT 50_B38_B40_SPDT 100_XCVR_B3_PRX_N 50_B38_FILTER 50_B40_FILTER 50_FULL_B40_FILTER 100_XCVR_B3_PRX_P 50_FULL_B40_SPDT 50_B2_DUPLX_RX 100_XCVR_B20_PRX_N 100_XCVR_B20_PRX_P 100_B20_DUPLX_RX_N 100_B20_DUPLX_RX_P 100_XCVR_B8_PRX_N 100_XCVR_B5_B18_PRX_P 100_B8_DUPLX_RX_N 100_B8_DUPLX_RX_P 100_B5_DUPLX_RX_N 100_RX_MODULE_OUT_P 100_XCVR_B7_B38_B40_PRX_N 100_XCVR_B7_B38_B40_PRX_P 100_RX_MODULE_OUT_N 100_XCVR_B1_B34_B39_DCS_PRX_N 100_XCVR_B1_B34_B39_DCS_PRX_P 100_B5_DUPLX_RX_P 100_XCVR_B8_PRX_P 100_XCVR_B5_B18_PRX_N 100_XCVR_B2_PRX_P 50_B7_B38_B40_PRX_BALUN_IN 100_B7_B38_B40_PRX_BALUN_OUT_N 50_FULL_B40_FILTER_MATCH 50_FULL_B40_SPDT_MATCH 50_B40_FILTER_MATCH 100_B7_B38_B40_PRX_MATCH_N 100_B7_B38_B40_PRX_MATCH_P 50_B3_RX_BALUN 50_B2_RX_BALUN 100_B7_B38_B40_PRX_BALUN_OUT_P 051-0886 A.0.0 38 OF 121 31 OF 54 1 2 1 2 1 24 1 3 2 1 2 6 9 8 7 5 2 4 3 1 1 2 1 2 2 1 21 21 21 21 1 2 1 2 1 2 1 2 1 2 2 3 5 4 1 21 21 21 21 1 2 1 2 1 2 1 2 21 21 1 2 1 2 21 2 1 21 1 2 1 2 1 2 2 1 2 1 1 2
- 33. IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUTIN OUT B3 OUT B1 INB34/B39 IN B1/B3 GND OUT B34 OUT B39OUTPUT BAND2 OUTPUT BAND5+18 OUTPUT BAND8 INPUT BAND2 GND INPUT BAND5+18 THRM INPUT BAND8 PAD CTRL RFIN GND RF2 RF1 VDD Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST TX INTERSTAGE FILTERS NOSTUFF 01005 16V 5% 56PF NP0-C0G C3911 29 1425333940 2833 29 29 29 29 29 33 10% X5R 6.3V 0.01UF 01005 C3909 34 36 36 35 34 33 33 33 16V 5% 01005 NP0-C0G 56PF C3908 3529 NOSTUFF 56PF NP0-C0G 01005 16V 5% C3902 CRITICAL AF48 LGA SAW-BAND-TX-B1-B3-B34-B39 FL3902 NOSTUFF 10NH-3%-140MA 01005 L3907 NOSTUFF 01005 5.1NH-3%-0.16A L3908 1.5NH+/-0.1NH-220MA 01005 L3909 CRITICAL LGA SATGR832MBM0F57 FL3901 CRITICAL 01005 2.0NH+/-0.1NH-0.2A-1.35OHM C3901 0.00 MF 01005 1/32W 0% C3903 0.00 MF 1/32W 0% 01005 C3904 01005 0.00 0% 1/32W MF C3905 0.00 0% MF 01005 1/32W C3910 CRITICAL 01005 10NH-5%-140MA L3901 CRITICAL 01005 10NH-5%-140MA L3902 01005 10NH-5%-140MA L3903 MF 1/32W 0% 01005 0.00 C3914 1/32W 0% 0.00 01005 MF C3913 NOSTUFF 01005 1.2NH+/-0.1NH-220MA L3904 CRITICAL TSLP6-2 BGS12SL6 U3901 01005 2.0NH+/-0.1NH-0.2A-1.35OHM L3906 01005 1.5NH+/-0.1NH-220MA R3901 CRITICAL 2.7NH+/-0.1NH-200MA 01005 L3905 3.3PF 16V 01005 +/-0.1PF NP0-C0G C3906 01005 1.5NH+/-0.1NH-220MA C3907 NP0-C0G 01005 100PF 5% 16V C3912 CELL: RF TRANSCEIVER (3 OF 4) 50_XCVR_B7_B38_B40_TX PP_LDO14_2V65 PA_MB_CTL0 50_XCVR_B8_TX 50_XCVR_B5_B18_TX 50_XCVR_B2_TX 50_XCVR_B1_B3_TX 50_XCVR_B34_B39_TX 50_B38_B40_TX_SPDT_MATCH 50_B2_TX_SAW_OUT 50_B5_TX_SAW_OUT 50_B8_TX_SAW_OUT 50_B7_TX_FILT_IN 50_B3_TX_SAW_OUT 50_B1_TX_SAW_OUT 50_B34_TX_SAW_OUT 50_B39_TX_SAW_OUT 50_B20_TX_SAW_IN50_XCVR_B20_TX 50_B7_TX_SPDT_OUT 50_B8_TX_SAW_IN 50_B5_B18_TX_SAW_IN 50_B2_TX_SAW_IN 50_B3_TX_SAW_MATCH 50_B1_TX_SAW_MATCH 50_B34_B39_TX_FILT_IN 50_B1_B3_TX_SAW_IN 50_XCVR_B7_B38_B40_TX_MATCH 50_B38_B40_TX_SPDT_OUT 051-0886 A.0.0 39 OF 121 32 OF 54 2 1 2 1 2 1 2 1 6 7 1 4 10 5 3 2 9 8 1 2 1 2 21 11 9 7 4 6 8 10 12 1 2 3 13 5 21 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 6 5 2 1 3 4 1 2 21 1 2 1 2 1 2 1 2
- 34. OUT IN IN IN IN IN IN IN IN OUT BI IN IN IN IN IN OUT OUT IN IN VC1 VC2 DCSRXIN BAND1ANT BAND1_TX GND VDD THRM BAND34_39_RXIN BAND1_34_39_DCSRXOUT1 BAND1_34_39_DCSRXOUT0 PAD BI BI BI OUT IN IN IN IN IN IN VC2 DGND RF1 GND2 GND1 VC3 VC4 RF7 RF6 RF5 RF2 RF3 VDD RF4 VC1 IN/OUT GND OUT/IN RFIN_B1 GND THRM CPL_IN CPL_OUT RFOUT_B1 RFIN_B34 RFIN_B39 RFOUT_B34/B39 RFIN_B38/B40 RFOUT_B38 RFOUT_B40 VBATT VBS_2 VCC VBS_1 VBS_0 VMODE PAD IN AppleInc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST BAND 1/34/39/38/40 TX B34 HPM 1 0 1 0 B34 LPM 1 0 1 1 B40 LPM 0 1 1 1 B39 HPM 0 0 1 0 B40 HPM 0 1 1 0 B38 LPM 1 1 1 1 B38 HPM 1 1 1 0 B39 LPM 0 0 1 1 B1 LPM X 1 0 1 B1 HPM X 1 0 0 OFF X X 0 0 0 ======================================================= BAND PA POWER MODE PA_BS PA_CTL1 PA_CTL0 PA_R1 34 2425343536373854 3435363738 6.3V 20% 0201-1 X5R 1.0UF C4002 0.1UF 01005 6.3V X5R-CERM 20% C4001 36 28343536 2832 32 39 39 39 39 142532333940 32 0.1UF 01005 20% 6.3V X5R-CERM C4074 NOSTUFF 01005 +/-0.1PF 1.2PF NP0-C0G 16V C4038 32 28 2834353637 31 31 01005 16V 56PF 5% NP0-C0G C4034 56PF 5% 16V NP0-C0G 01005 C4033 28 33 28 33 CRITICAL LGA LMSWFKJM U4027 NP0-C0G 01005 16V 56PF 5% C4053 5% 01005 NP0-C0G 16V 56PF C4052 56PF 5% 16V 01005 NP0-C0G C4042 56PF 5% 01005 NP0-C0G 16V C4041 100PF 5% 16V 01005 NP0-C0G C4054 NP0-C0G 100PF 01005 5% 16V C4043 1/32W 0.00 MF 0% 01005 R4065 5% NP0-C0G 01005 56PF 16V C4073 NOSTUFF 01005 NP0-C0G +/-0.05PF 0.5PF 16V C4055 NOSTUFF NP0-C0G 25V 56PF 5% 201 C4060 CRITICAL 01005 0% MF 1/32W 0.00 L4070 31 31 31 31 35 0.00 01005 0% 1/32W MF L4012 NOSTUFF 16V 56PF NP0-C0G 01005 5% C4023 01005 NP0-C0G 16V 5% 56PF C4072 0% 01005 1/32W MF 0.00 R4064 NP0-C0G 56PF 01005 16V 5% C4012 142532333940 5% 56PF NP0-C0G 16V 01005 C4008 24283940 283940 NP0-C0G 01005 5% 16V 56PF C4075 16V 5% NP0-C0G 56PF 01005 C4076 2833 2833 0.00 01005 0% MF 1/32W L4029 01005 1/32W MF 0.00 0% L4030 01005 0.00 MF 1/32W 0% L4044 0 MF 201 5% 1/20W C4058 0 5% 201 1/20W MF C4048 MF 0 1/20W 5% 201 C4049 CRITICAL 7.5NH-0.30A 0201 L4097 CRITICAL 2.9NH+/-0.1NH-0.5A-0.2OHM 0201 L4083 CRITICAL 0.6PF CERM 25V +/-0.05PF 0201 C4063 CRITICAL 0201 8.2NH+/-3%-0.25A-0.7OHM C4071 CRITICAL BGA SKY13477 U4000 CRITICAL LGA DEA162025LT-5046B1SJ 1880-2025MHZ FL4012 0201 25V +/-0.05PF C0G-CERM 3.0PF C4047 10NH-3%-250MA 0201 C4064 15NH+/-3%-0.25A-0.7OHM 0201 C4046 CRITICAL 0201 100PF NP0-CERM 25V 5% L4072 0201 12NH+/-3%-0.25A-0.7OHM C4061 18NH-3%-140MA 01005 C4040 01005 5% 16V NP0-C0G 100PF L4020 7.5NH-3%-0.140A 01005 C4037 +/-0.1PF NP0-C0G 01005 16V 4.0PF L4045 CRITICAL 0201 5.6NH-3%-0.35A C4056 CRITICAL LLP ACPM-7900-AP1 U4025 CRITICAL 4.0PF 0201 COG-CERM 25V +/-0.1PF L4071 NOSTUFF NP0-C0G 1.2PF 01005 16V +/-0.1PF C4039 32 CELL: PENTABAND PA 50_3P4T_PRX_OUT 50_B40_PA_MATCH 50_B38_PA_MATCH PP_PA 50_B38_B40_PA_IN 50_B1_PA_OUT 50_RX_MOD_B34_B39_IN 50_B34_B39_RX_ASM 3P4T_SEL_0 3P4T_SEL_1 50_B1_RX_MOD_ANT 50_B1_PA_OUT_MATCH 50_RX_MOD_DCS_IN PP_LDO14_RX_MOD 50_B7_RX_SP3T_IN 50_B34_B39_PA_FILT_IN 50_B34_B39_PA_FILT_OUT PP_LDO14_3P4T 50_B40_PA_OUT 50_B38_PA_OUT 50_B34_B39_PA_OUT 50_B39_PA_IN 50_B34_PA_IN 50_B1_PA_IN 50_MBPA_CPL_IN 50_B34_TX_SAW_OUT 3P4T_SEL_1 3P4T_SEL_0 ANT_SEL_0 ANT_SEL_1 PP_LDO14_2V65 50_B7_DUPLX_RX 50_B38_FILTER 50_B40_FILTER 50_FULL_B40_FILTER 100_RX_MODULE_OUT_N 100_RX_MODULE_OUT_P PA_R1 PA_MB_CTL1 50_B1_TX_SAW_OUT 50_B39_TX_SAW_OUT PP_LDO14_2V65 50_B1_ANT 50_B34_B39_TX_ASM 50_DCS_RX_ASM 50_B38_B40_TX_SPDT_MATCH PA_MB_CTL0 PA_BS =PPBATT_VCC_BB 50_B2_B3_CPL_IN 50_B38_B40_TX_MATCH 051-0886 A.0.0 40 OF 121 33 OF 54 2 1 2 1 2 1 2 1 2 1 2 1 8 7 1 17 15 13 9 10 3 2 6 5 4 14 16 19 20 18 12 11 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 2 1 2 1 1 2 1 2 2 1 2 1 1 2 2 1 2 1 2 1 2 1 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 1 2 C1 B2 C5 B3 B4 A2 C2 A3 A5 A4 C4 C3 A1 B5 B1 1 2 4 3 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 9 1 14 13 16 18 20 23 22 25 27 28 29 30 31 32 12 24 21 5 4 19 6 17 15 26 8 10 7 3 11 1 2 2 1
- 35. THRM_PAD VEN_B2_B3 CPL_OUT GNDGND RX_B2 GND RX_B3 RFIN_B2 RFIN_B3 VBATT VCC CPL_IN BS ANT_B2 ANT_B3 VMODE BI BI OUT IN IN IN IN IN IN IN OUT IN OUT Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST BAND 2/3 PAD B3 LPM 0 1 1 OFF X X 0 X ===================================================== B2 LPM 1 1 1 B3 HPM 0 1 0 B2 HPM 1 1 0 BAND PA POWER MODE PA_BS PA_ON_B2_B3 PA_R1 0.00 0201 MF 1/20W 1% R4139 CRITICAL +/-0.05PF CERM 25V 0.6PF 0201 C4155 CRITICAL TQM6M6224 LGA U4123 X5R 0.22UF 20% 6.3V 01005 C4100 6.3V 20% 0.22UF X5R 01005 C4101 5% CERM 6.3V 100PF 01005 C4102 CERM 100PF 5% 01005 6.3V C4103 NOSTUFF 01005 16V C0G-CERM +/-0.05PF 0.5PF C4104 CRITICAL 0201 3.0NH+/-0.1NH-0.45A L4136 CRITICAL 3.0NH+/-0.1NH-0.45A 0201 L4138 CRITICAL 0201 COG-CERM 0.5PF +/-0.05PF 25V C4154 39 39 35 28 33 35 36 37 28 33 35 36 28 X5R 6.3V 20% 1.0UF 0201-1 C4149 3335363738 6.3V 20% 01005 X5R-CERM 0.1UF C4148 2425333536373854 0% 01005 MF 1/32W 0.00 C4146 32 32 31 33 31 NOSTUFF 25V CERM 201 +/-0.05PF 0.5PF C4151 NOSTUFF 0.5PF 25V CERM +/-0.05PF 201 C4150 NOSTUFF 9.1NH-3%-140MA 01005 L4122 NOSTUFF 01005 2.2NH+/-0.1NH-200MA L4182 01005 2.7NH+/-0.1NH-200MA L4123 C0G-CERM 16V +/-0.05PF 0.5PF 01005 C4147 CELL: BAND 2/3 PAD 50_B2_DPLX_ANT_MATCH 50_B2_DPLX_ANT 50_B3_TX_PAD_IN 50_B3_DPLX_ANT 50_B3_DUPLX_RX 50_B2_B3_CPL_IN 50_B2_DUPLX_RX 50_B2_TX_SAW_OUT 50_B3_TX_SAW_OUT =PPBATT_VCC_BB PP_PA PA_ON_B2_B3 PA_BS PA_R1 50_B7_B20_CPL_IN 50_B3_ANT 50_B2_ANT 50_B2_TX_PAD_IN 051-0886 A.0.0 41 OF 121 34 OF 54 1 2 2 1 31 30 20 27 23 1 3 7 6 5 12 9 15 17 18 19 21 22 10 11 14 13 28 26 25 2 4 29 8 16 24 2 1 2 1 2 1 2 1 2 1 21 21 2 1 2 1 2 1 1 2 2 1 2 1 1 2 1 2 21 2 1
- 36. VMODE BS VEN_B7_B20 VCC VBATT RFIN_B20 RFIN_B7 RX_P_B20 GND RX_N_B20 RX_B7 GND THRM_PAD CPL_IN CPL_OUT ANT_B7 ANT_B20 BI IN BI IN IN IN IN IN OUT OUT OUT OUT IN IN INPUT_BAND7 INPUT_BAND20 OUTPUT_BAND20 OUTPUT_BAND7 GND CONFIDENTIALAND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT BAND PA POWER MODE PA_BS PA_ON_B20_B7 PA_R1 BAND 20/7 PAD B7 HPM 1 1 0 ===================================================== OFF X X 0 X B20 HPM 0 1 0 B20 LPM 0 1 1 B7 LPM 1 1 1 CRITICAL LGA AFEM-790720 U4215 39 NOSTUFF 0201 10NH-3%-250MA L4257 CRITICAL CELL 01005 NP0-C0G 16V +/-0.1PF 1.0PF C4207 2425333436373854 39 6.3V 01005 20% 0.22UF X5R C4235 01005 6.3V 20% 0.22UF X5R C4232 CERM 100PF 5% 6.3V 01005 C4233 01005 5% 6.3V 100PF CERM C4234 3334363738 CERM 100PF 5% 6.3V 01005 C4239 CRITICAL CELL 6.2NH-0.30A 0201 L4200 CRITICAL CELL 25V +/-0.1PF 3.9PF C0G-CERM 0201 C4208 5% 16V CERM 01005 22PF C4231 NOSTUFF 0.8PF 01005 16V NP0-C0G +/-0.1PF CRITICAL C4228 2.2NH+/-0.1NH-0.6A 0201 C4236 CRITICAL 25V +/-0.05PF 0.5PF 0201 COG-CERM L4229 34 01005 3.3NH+/-0.1NH-180MA CRITICAL L4254 20% 6.3V 01005 X5R-CERM 0.1UF C4229 20% X5R 6.3V 0201-1 1.0UF C4230 28 33 34 36 37 28 33 34 36 28 29 33 16V NOSTUFF 01005 NP0-C0G +/-0.1PF 1.2PF C4227 31 31 32 01005 NP0-C0G 16V 56PF 5% C4218 32 NOSTUFF NP0-C0G 5% 01005 16V 56PF C4219 CRITICAL SAWFD847MGA0F57 LGA FL4211 01005 CRITICAL 2.7NH+/-0.1NH-200MA L4253 NOSTUFF 01005 2.2NH+/-0.1NH-200MA C4216 NOSTUFF 25V +/-0.05PF CERM 0.5PF 201 L4228 CELL: BAND 7/20 PAD 50_B7_DPLX_ANT 50_B7_TX_FILT_MATCH 50_B20_TX_SAW_MATCH 50_B20_TX_PAD_IN 50_B20_DPLX_ANT 50_B7_B20_CPL_IN 50_PDET_PAD_IN PA_R1 50_B20_TX_SAW_IN 50_B7_TX_FILT_IN 100_B20_DUPLX_RX_P 100_B20_DUPLX_RX_N PA_BS 50_B20_ANT 50_B7_ANT PA_ON_B7_B20 PP_PA 50_B7_DUPLX_RX =PPBATT_VCC_BB 50_B7_TX_FILT_OUT 50_B7_TX_PAD_IN 50_B20_TX_SAW_OUT 051-0886 A.0.0 42 OF 121 35 OF 54 24 29 30 2 25 26 28 12 10 13 11 22 21 19 18 17 15 9 14 5 6 7 3 1 23 27 42 40 39 41 37 38 36 34 35 31 32 33 4 20 8 16 1 2 1 2 2 1 2 1 2 1 2 1 2 1 21 2 1 1 2 2 1 21 2 1 21 2 1 2 1 2 1 1 2 2 1 4 1 9 6 5 3 2 10 8 7 211 2 2 1
- 37. IN IN IN IN IN IN OUT BI BI OUT OUT OUT OUT ANT_B5 RFIN_B8 BS VEN_B5_B8 CPL_OUT CPL_IN THRM_PADGND VBATT VCC VMODE ANT_B8 RX_P_B5 RX_N_B5 RX_P_B8 RX_N_B8 RFIN_B5 IN CONFIDENTIAL AND PROPRIETARYAPPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT BAND PA POWER MODE PA_BS PA_ON_B5_B8 PA_R1 B5 HPM 0 1 0 B8 HPM 1 1 0 B8 LPM 1 1 1 B5 LPM 0 1 1 OFF X X 0 X ===================================================== BAND 5/8 PAD 32 3334353738 0.1UF 20% 6.3V X5R-CERM 01005 C4318 32 6.3V 20% X5R 1.0UF 0201-1 C4319 28 33 34 35 37 28 33 34 35 28 33 39 39 31 31 31 31 NP0-C0G 01005 16V 1.2PF +/-0.1PF NOSTUFF C4316 2.2NH+/-0.1NH-200MA 01005 CRITICAL L4314 01005 2.2NH+/-0.1NH-200MA CRITICAL L4315 2.7NH+/-0.1NH-0.50A 0201 CRITICAL C4320 SKY77493LGA CRITICAL U4358 01005 6.3V 20% 0.22UF X5R C4322 01005 6.3V 20% 0.22UF X5R C4323 5% 6.3V CERM 01005 100PF C4324 5% 100PF CERM 6.3V 01005 C4325 NP0-C0G 01005 16V 1.2PF +/-0.1PF NOSTUFF C4327 +/-0.1PF NP0-C0G 01005 16V 1.2PF NOSTUFF C4326 22NH-100MA NOSTUFF L4317 0201 01005 MF 1/32W 1% 49.9 R4300 25V +/-0.05PF 0.5PF 0201 CRITICAL L4316 COG-CERM 16V +/-0.1PF 2.2PF NP0-C0G 01005-1 CRITICAL C4317 2% 25V 0201 C0H-CERM C4321 18PF 2425333435373854 CELL: BAND 5/8 PAD 50_B8_TX_PAD_IN 50_PA_ISO 50_B5_TX_PAD_IN 50_B5_DPLX_ANT 50_B8_DPLX_ANT =PPBATT_VCC_BB 100_B5_DUPLX_RX_P 100_B5_DUPLX_RX_N 100_B8_DUPLX_RX_P 50_MBPA_CPL_IN PA_ON_B5_B8 PA_BS PA_R1 50_B5_TX_SAW_OUT PP_PA 50_B8_TX_SAW_OUT 50_B5_ANT 100_B8_DUPLX_RX_N 50_B8_ANT 051-0886 A.0.0 43 OF 121 36 OF 54 2 1 2 1 2 1 21 21 21 16 28 25 24 20 4 33 32 31 35 34 36 38 37 41 39 40 42 27 23 1 3 7 6 5 12 9 15 17 18 19 21 22 29 2 30 8 13 14 11 10 26 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 2 2 1 2 1 1 2
- 38. IN IN OUT IN IN IN IN IN V2G VBATT HB_GSM_RF_OUT LB_GSM_RF_OUT HB_GSM_RF_IN LB_GSM_RF_IN VMODE0 PA_ON2 PA_ON3 THRM_PAD THRM_PAD THRM_PAD THRM_PAD THRM_PAD THRM_PAD THRM_PAD THRM_PAD THRM_PAD GND GND GND GND GND OUT CONFIDENTIAL AND PROPRIETARYAPPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT HIGH BAND HIGH BAND HIGH BAND BAND LOW BAND LOW BAND LOW BAND LOW BAND LOW BAND HIGH BAND HIGH BAND LOW BAND LOW BAND 2G PA GAIN MODES EDGE EDGE EDGE EDGE GSM GSM GSM GSM GSM GSM GSM LOW MEDIUM MEDIUM HIGH HIGH HIGH LOW HIGH LOW ULTRA LOW LOW HIGH LOW HIGH LOW LOW HIGH LOW HIGH LOW HIGH PA_R1GAIN MODEMODE ======================================================= 14 TO 15 2 TO 8 9 TO 15 8 TO 9 10 TO 14 15 TO 19 0 TO 6 7 TO 9 10 TO 15 5 TO 6 7 TO 13 16 TO 19 PCL RANGE HIGH ULTRA LOW LOW EDGE 2G PACONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST. 01005 5% 56PF NP0-C0G 16V C4489 0201 NOSTUFF 3.6NH+/-0.1NH-400MA L4439 4V 20% X5R 01005 0.1UF C4488 402 4.7UF 20% 6.3V X5R-CERM1 C4485 3334353638 2425333435363854 20% 1.0UF 10V X5R-CERM 0201-1 C4487 16V 01005 5% NP0-C0G 100PF C4486 100PF 5% 01005 16V NP0-C0G C4483 39 2833343536 28 28 01005 16V CERM 5% 12PF C4472 2.7PF +/-0.1PF 01005-1 NP0-C0G 16V C4467 NP0-C0G 33PF 01005 5% 16V C4484 6.0PF NOSTUFF NP0-C0G +/-0.1PF 16V 01005 C4471 2.7NH+/-0.1NH-200MA 01005 L4436 29 0201 NOSTUFF 3.6NH+/-0.1NH-400MA L4438 29 0201 240OHM-350MA L4440 LGA CRITICAL SKY77355 U4410 CRITICAL 0% 01005 MF 1/32W 0.00 L4435 CRITICAL 3.2NH+/-0.1NH-0.45A-025OHM 0201 L4437 0.00 0201 MF 1/20W 1% R4437 39 CELL: 2G PA 50_TX_G_HB_ASM50_TX_G_HB_PAOUT 50_XCVR_2G_LB_TX =PPBATT_VCC_BB 50_TX_G_LB_PAIN PA_R1 PP_BATT_VCC_2G_PA 50_TX_G_HB_PAIN50_TX_G_HB_MCH50_XCVR_2G_HB_TX GSM_PA_HB_EN GSM_PA_LB_EN PP_PA 50_TX_G_LB_MCH 50_TX_G_LB_PAOUT 50_TX_G_LB_ASM 051-0886 A.0.0 44 OF 121 37 OF 54 2 1 1 2 2 1 2 1 2 1 2 1 2 1 1 21 2 1 2 2 1 1 2 1 2 21 14 7 11 8 1 3 6 4 5 23 22 21 20 19 18 17 16 15 13 12 10 9 2 1 2 21 1 2
- 39. IN IN IN IN OUT MODE VCON EN PGND ACB ACB FB SW VDDPVIN SGND BGND BP SW CONFIDENTIAL AND PROPRIETARYAPPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PA DC/DC CONVERTER PLACE NEAR U1.H3 PLACE NEAR U11.D2 28 1.00K 01005 MF 1/32W 1% R4500 2425333435363754 28 28 56PF NP0-C0G 16V 5% 01005 C4502 10% X5R 0.01UF 01005 6.3V C4503 6.3V 10% 01005 X5R-CERM 1000PF C4500 CERM 10UF 20% 6.3V 0402 C4504 MF 1% 1/32W 01005 1.00K R4534 33 34 35 36 37 CRITICAL BGA LM3258 U4500 CRITICAL 6.3V 20% 10UF 0402 CERM-X5R C4507 CRITICAL 3300PF 6.3V 10% 01005 X5R C4508 CRITICAL PIFE20161T-SM 1.5UH-2.0A-0.137OHM L4500 X5R-CERM 01005 1000PF 6.3V 10% C4545 CELL: PA DCDC CONVERTER BB_PDM_FILT DCDC_ADJ DCDC_OUT PP_PA DCDC_MODE DCDC_EN BB_PDM =PPBATT_VCC_BB 051-0886 A.0.0 45 OF 121 38 OF 54 1 2 2 1 2 1 2 1 2 1 1 2 D3 D2 C2 B1 A1 B4 A4 D4 A2 D1 B3 A3 C1 C4 C3 B2 2 1 2 1 1 2 2 1
- 40. BI IN IN BI IN IN BI TRX9 TRX10 TRX8 TRX7 TRX4 TRX5 TRX3 TRX6 TRX2 TRX1 GND GND GND THRM GND HBTX ANT2 ANT1 RF2 RF1 LBTX VC1 VC2 VC3 VC5 VC4 VDD PAD RF3 VDD RF2 GND VC RF1 BI BI BI IN IN IN IN IN BI BI IN BI BI BI BI BI CONFIDENTIAL AND PROPRIETARYAPPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 0 = FULL B40 1 = PARTIAL B40 . PRIMARY ASM 31 5% 01005 6.3V CERM 100PF C4669 142532333940 6.3V 5% CERM 01005 100PF C4668 28 42 37 37 31 MF 1% 1/20W 201 49.9 R4608 49.9 1% MF 1/20W 201 R4607 C0G-CERM 25V +/-0.1PF 0.3PF L4642 201 LGA RF1495 CRITICAL U4617 XFLGA CXA4403GC CRITICAL SW4601 56NH-100MA-3.9OHM 0201 L4613 33 C4640 0201 1.8NH+/-0.1NH-600MA 33 36 142532333940 5% 201 MF 1/20W 0 R4605 24 28 40 24 28 33 40 28 33 40 28 40 01005 100PF 5% 6.3V CERM C4622 01005 20% 4V X5R 0.1UF C4641 5% 01005 CERM 6.3V 100PF C4639 01005 CERM 6.3V 5% 100PF C4664 5% 01005 CERM 6.3V 100PF C4665 6.3V 5% CERM 01005 100PF C4663 01005 100PF 5% 6.3V CERM C4666 35 36 28 33 35 33 34 34 CELL: ASM AND HB LTE FRONT-END 50_ASM_ANT 50_B38_B40_SPDT PP_LDO14_2V65 B40_FILT_SELECT 50_PRI_ANT_COAX 50_TX_G_HB_ASM 50_TX_G_LB_ASM 50_FULL_B40_SPDT 50_DCS_RX_ASM 50_B34_B39_TX_ASM 50_B8_ANT PP_LDO14_2V65 ANT_SEL_2 ANT_SEL_1 ANT_SEL_0 ANT_SEL_3 50_B7_ANT 50_B5_ANT ANT_SEL_4 50_B1_ANT 50_B20_ANT 50_B34_B39_RX_ASM 50_B2_ANT 50_RF2_TERM 50_ANT2_TERM 50_TXRX_B38_B40_SPDT 50_TXRX_B38_B40_ASM 50_B3_ANT 051-0886 A.0.0 46 OF 121 39 OF 54 2 1 2 1 1 2 1 2 2 1 17 18 16 15 7 8 6 14 5 4 11 9 1 27 13 10 20 2 19 3 12 21 22 23 25 24 26 2 5 4 3 1 6 1 2 21 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1
- 41. OUT OUT OUT OUT OUT OUT IN IN IN IN OUT OUT IN OUT OUT B38_ANT B40_ANT GND B38_RX B40_RX GPS OUT GPS OUT GPSIN VC3 VC4 VC1 VC2 GND GND THRM GND GND GND GND GND GND GND GND GND GND VDD ANTENNA AUX1 BAND 38 IN BAND 40 IN AUX2 GND BAND 8,20 OUT BAND 8,20 OUT BAND 5+18 OUT BAND 5+18 OUT BAND 1,2,3,34,39 OUT BAND 1,2,3,34,39 OUT BAND 7,38,40 OUT BAND 7,38,40 OUT PAD IN IN CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT RX DIVERSITY 29 29 29 29 29 29 201 1/20W MF 1% 49.9 R4739 283339 242839 24283339 2839 29 29 NOSTUFF 3.0NH+/-0.1NH-0.45A 0201 L4765 56PF NP0-C0G 5% 16V 01005 C4710 56PF 16V NP0-C0G 5% 01005 C4797 10NH-3%-140MA NOSTUFF 01005 L4740 41 01005 16V 5% 56PF NP0-C0G C4736 16V NP0-C0G 5% 56PF 01005 C4738 NP0-C0G 16V 01005 5% 56PF C4737 56PF NP0-C0G 16V 5% 01005 C4739 29 29 5.6NH-3%-140MA 01005 C4755 5.6NH-3%-140MA 01005 C4756 01005 4.7NH-3%-160MA L4742 BAW-DUAL-RX-B38-B40 LGA 885035 U4722 NOSTUFF 3.0NH+/-0.1NH-0.45A 0201 L4743 5% 201 MF 1/20W 0 R4701 CRITICAL 5% 6.3V NP0-C0G 0201 27PF C4794 0 1/20W MF 201 5% L4747 1/20W 5% 201 MF 0 L4746 CRITICAL 0201 6.8NH-3%-0.3A C4799 2.3NH+/-0.1NH-0.50A-0.2OHM 0201 C4708 0201 5.6NH-3%-0.35A CRITICAL L4701 0201 5.6PF NP0-C0G 25V +/-0.1PF R4711 CRITICAL LGA HFQSWBUUA-239 U4714 1425323339 X5R 6.3V 10% 01005 0.01UF C479841 CELL: RX DIVERSITY 50_B38_B40_DRX_FILT_IN 50_GPS_LNA_OUT 100_XCVR_GPS_RX_N 100_XCVR_GPS_RX_P 50_DRX_ANT 50_B38_DRX_FILT_OUT 50_DRX_ASM_MCH 50_B40_DRX_FILT_OUT 100_XCVR_B7_B38_B40_DRX_N 100_XCVR_B7_B38_B40_DRX_P 100_XCVR_B1_B2_B3_B34_B39_DRX_N 100_XCVR_B1_B2_B3_B34_B39_DRX_P 100_XCVR_B5_B18_DRX_P 100_XCVR_B5_B18_DRX_N 100_XCVR_B8_B20_DRX_P 50_B38_B40_DRX_AUX2_OUT 50_B40_DRX_MOD_IN 50_B38_DRX_MOD_IN 50_DRX_MOD_TERM 50_DIVERSITY_SWITCH_MATCH ANT_SEL_1 ANT_SEL_0 ANT_SEL_3 ANT_SEL_2 50_GPS_DRX_MOD_IN 100_XCVR_GPS_RX_MATCH_P 100_XCVR_GPS_RX_MATCH_N 100_XCVR_B8_B20_DRX_N PP_LDO14_2V65 051-0886 A.0.0 47 OF 121 40 OF 54 1 2 1 2 2 1 1 2 1 2 2 1 2 1 2 1 2 1 21 21 1 2 8 7 10 9 6 5 3 2 1 4 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 17 18 14 4 3 6 5 34 32 35 31 30 36 37 38 2 8 13 15 16 27 28 29 7 1 33 12 11 9 10 24 23 26 25 21 22 19 20 2 1
- 42. OUT CR GND OUT IN GPS/GNSS HB/LBANT GND GND PON A0 VCC GND AI Apple Inc. THEINFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT GPS_DRX_ANT TOP MOUNT TOP MOUNT 900MHZ TRAP GPS 787MHZ TRAP 2400MHZ TRAP CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST. 0201 4.7NH-3%-0.35A CRITICAL CELL L4806 15NH+/-3%-0.25A-0.7OHM 0201 CELL CRITICAL L4805 NOSTUFF 0201 27NH-3%-0.140A-2.3OHM L4802 F-ST-SM MM5829-2700 CELL J4800 25V 0.2PF +/-0.1PF COG-CERM 201 NOSTUFF C4801 CRITICAL CELL 5% MF 201 0 1/20W R4801 201 COG-CERM 25V +/-0.1PF 0.2PF NOSTUFF C4802 NOSTUFF 0201 10NH-3%-250MA L4803 40 25V C0G 0201 CELL +/-0.1PF CRITICAL 5.0PF C4803 F-RT-SM MM8930-2600B CELL J4802 01005 0.9PF CELL 16V CERM +/-0.05PF CRITICAL C4805 40 25 LGA SASLE1G58AB0F57 CELL FL4801 CRITICAL 01005 20% CELL 0.1UF 6.3V X5R-CERM C4809 TSNP6 BGA824N6 CELL CRITICAL U4801 CRITICAL 01005 CELL 150OHM-25%-200MA-0.7DCR FL4802 5% CELL 0 1/20W MF 201 CRITICAL L4801 NOSTUFF 201 25V +/-0.1PF C0G-CERM 1.3PF L4807 +/-0.1PF 1.8PF NP0-C0G 16V CRITICAL 01005-1 CELL C4804 0201 CELL CRITICAL 2.0NH+/-0.1NH-0.6A C4807 8.2NH+/-3%-0.25A-0.7OHM CRITICAL CELL 0201 L4804 CELL: GPS SYNC_DATE=10/29/2013SYNC_MASTER=RADIO_MLB_87 50_GPS_ANT_TEST 50_DRX_ANT 50_GPS_DIV_SW_CONN 50_GPS_DIV_SW_CONN50_GPS_ANT_COAX 50_GPS_LNA_OUT PP_LDO5_GPS_LNA_2V5 50_GPS_FILT1 50_GPS_DIV_TRI_ANT 50_GPS_LNA_IN PP_GPS_LNA_2V5 50_GPS_FILT3 50_GPS_FILT2 50_GPS_FILT4 051-0886 A.0.0 48 OF 121 41 OF 54 21 1 2 1 2 4 2 3 1 2 1 1 2 2 1 1 2 1 2 1 5 6 2 3 4 1 2 9 8 5 4 2 7 1 36 2 1 1 6 3 2 4 5 21 1 2 2 1 2 1 21 21 41 41
- 43. BI Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT ANTENNA FEEDS PRI_ANT COAXCELL F-ST-SM MM5829-2700 J4910 39 CELL: ANTENNA FEEDS SYNC_MASTER=RADIO_MLB_87 SYNC_DATE=10/29/2013 50_PRI_ANT_COAX 051-0886 A.0.0 49 OF 121 42 OF 54 4 2 3 1
- 44. OUT SYM_VER-1 SYM_VER-1 OUT Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT 0.055 OHM DCR 0.055 OHM DCR NOTE: SPKR_L_CONN_N AND SPKR_L_CONN_P WERE SWAPPED ON 5/22/12 PER RADAR #11526818 DZ5700 27V-100PF 0402 C5700 201 NP0-C0G 1% 27PF 25V C5701 10% X7R 0.01UF 25V 402 0603 FERR-70-OHM-4A L5700 R5700 201 100K MF 1/20W 1% C5702 201 NP0-C0G 1% 27PF 25V 201 C5703 CERM 6.8PF +/-0.25PF 25V 25V 201 C5704 CERM 6.8PF +/-0.25PF NOSTUFF R5705 1% 100K MF 1/32W 01005 01005 1% 10K MF 1/32W R5706 48 01005 C5705 NP0-C0G-CERM 8.2PF +/-0.5PF 16V 16V 01005 C5707 8.2PF +/-0.5PF NP0-C0G-CERM 90-OHM-50MA TCM0605-1 L5703 90-OHM-50MA TCM0605-1 L5704 11 0201-1 14.2V-6PF DZ5703 CRITICAL DZ5704 0201-1 14.2V-6PF CRITICAL DZ5702 0201-1 14.2V-6PF CRITICAL DSF01S30SC DZ5710SM-201 CRITICAL 01005 0.00 0% R5791 1/32W MF NOSTUFF 0.00 0% R5790 1/32W MF 01005 CRITICAL D5700 TSSLP-2-1 ESD0P2RF-02LS D5702 ESD0P2RF-02LS TSSLP-2-1 CRITICAL D5703 CRITICAL TSSLP-2-1 ESD0P2RF-02LS D5701 ESD0P2RF-02LS TSSLP-2-1 CRITICAL NOSTUFF J5700 HB-SM MLB-X200 IO: FILTERS & HOTBAR CONN SYNC_DATE=04/18/2011SYNC_MASTER=N/A E75_DPAIR2_CONN_P E75_DPAIR2_CONN_N E75_DPAIR1_CONN_N E75_DPAIR1_CONN_P =PPVBUS_USB_EMI E75_DPAIR1_P E75_DPAIR1_N E75_DPAIR2_P E75_DPAIR2_N =PPVCC_MAIN_DOCK CONN_DET_L PPOUT_E75_ACC_ID1_CONN PPOUT_E75_ACC_ID2_CONN PPOUT_E75_ACC_ID1 PPOUT_E75_ACC_ID2 PPVBUS_E75_USB_CONN TS_CON_DET_L PMU_E75_ACC_DET_L SPKR_L_CONN_P SPKR_L_CONN_N SPKR_L_CONN_N E75_DPAIR1_CONN_P SPKR_R_CONN_N PPOUT_E75_ACC_ID2_CONN PPOUT_E75_ACC_ID1_CONN SPKR_R_CONN_N SPKR_R_CONN_P CONN_DET_L E75_DPAIR2_CONN_N PPVBUS_E75_USB_CONN E75_DPAIR1_CONN_N PPVBUS_E75_USB_CONN E75_DPAIR2_CONN_P SPKR_R_CONN_P SPKR_L_CONN_P FERR-22-OHM-1A-0.055OHM FERR-22-OHM-1A-0.055OHM L5701 L5702 0201 0201 051-0886 A.0.0 57 OF 121 43 OF 54 1 2 2 1 2 1 21 1 2 2 1 2 1 2 1 1 2 1 2 2 1 2 1 4 32 1 4 32 1 21 21 A C A C A C K A 1 2 1 2 1 2 1 2 1 2 1 2 32 4 9 10 14 18 25 23 21 19 17 15 13 11 5 7 3 1 22 20 24 16 12 8 6 2 26 27 28 29 30 31 4352 4352 4352 4352 54 11 11 11 11 54 43 4352 4352 11 11 43 164352 16 43 52 164352 43 52 16 43 52 43 52 43 52 164352 164352 43 4352 43 4352 43 43 52 16 43 52 16 43 52
- 45. NC NC NC NC NC BI NC BI OUT NC NC NC IN IN NC NC NC NC NC NC IN IN OUT IN IN IN IN OUT IN OUT IN IN ANT(COMMON) LOW(2.4GHZ) HIGH(5.0GHZ) GND GND INOUT HI LO COM GND IN OUT OUT IN OUT OUT IN OUT IN JTAG_SEL HSIC_DATA HSIC_STROBE SDIO_CLK SDIO_CMD GPIO0/WL_HOST_WAKE GPIO1/HOST_READY GPIO2/WL_TCK GPIO4/WL_TDI GPIO5/WL_TDO GPIO12/WL_TRST* GPIO11/HSIC_RESUME GPIO15/WLAN_UART_TX GPIO14/WLAN_UART_RX GPIO10/HSIC_DEVICE_READY GPIO9/AGG_CHANNEL GPIO3/WL_TMS SDIO_DATA2 BT_REG_ON RF_G_1 RF_G_0 RF_A_1 RF_A_0 GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL GND_SIGNAL RF_SW_CTRL11 CLK_32K VBAT VBAT WL_REG_ON SDIO_DATA3 SDIO_DATA1 SDIO_DATA0 RF_VCC_FEM RF_VCC_FEM I2SCLK I2SDI I2SDO I2SWS BT_PCM_OUT BT_PCM_IN BT_UART_CTS* BT_UART_RTS* BT_UART_TXD BT_PCM_CLK BT_PCM_SYNC BT_GPIO1/HOSTWAKE BT_GPIO0/BTWAKE BT_UART_RXD BT_GPIO5/LTE_COEX_UART_TX BT_GPIO4/LTE_COEX_UART_RX GPIO8 GPIO7 VIO DUMMY GPIO6 Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT WIFI/BT: MODULEMODULE ISOLATION 453 453 J5820 CRITICAL MM4829-2702 F-ST-SM 5 53 19 28 52 19 28 52 C5827 0.2PF +/-0.1PF 25V COG-CERM NOSTUFF 201 C5826 0.2PF 25V COG-CERM 201 +/-0.1PF NOSTUFF C5825 25V +/-0.1PF 0.2PF 201 NOSTUFF COG-CERM R5820 0.00 CRITICAL 0201 1% 1/20W MF 10 10 R5801 1/32W MF 0.00 0% 01005 R5802 0% 0.00 MF 01005 1/32W R5800 01005 MF 1/32W 5% 10K R5803 01005 MF 10K 1/32W 5% 5 53 C5800 4.7UF X5R-CERM1 6.3V 20% 402 C5801 20% 6.3V X5R-CERM1 4.7UF 402 R5804 0.00 01005 MF 0% 1/32W 28 52 C5880 0402-2 10UF 20% 6.3V CERM-X5R C5881 0402-2 10UF 20% 6.3V CERM-X5R C5882 0402-2 10UF 20% 6.3V CERM-X5R XW5890 SHORT-10L-0.25MM-SM 4852 4852 4852 2428 2428 553 553 553 XW5891 SHORT-10L-0.25MM-SM XW5892 SHORT-10L-0.25MM-SM XW5893 SHORT-10L-0.25MM-SM XW5894 SHORT-10L-0.25MM-SM XW5895 SHORT-10L-0.25MM-SM XW5896 SHORT-10L-0.25MM-SM XW5897 SHORT-10L-0.25MM-SM C5822 NOSTUFF 0.2PF +/-0.1PF 25V COG-CERM 201 C5821 1.1NH+/-0.1NH 0201 CRITICAL C5815 25V 0.2PF +/-0.1PF COG-CERM 201 NOSTUFF R5830 MF 0201 1% 1/20W CRITICAL 0.00 C5816 201 +/-0.1PF 0.2PF 25V NOSTUFF COG-CERM R5810 0201 1% 1/20W MF CRITICAL 0.00 C5817 201 NOSTUFF 0.2PF 25V +/-0.1PF COG-CERM U5810 CRITICAL 2.4-5.0GHZ SM J5810 F-ST-SM CRITICAL MM4829-2702 U5811 LGA CRITICAL BAW-2436MHZ 885061 L5811 0201 CRITICAL 10NH-3%-250MA C5810 CRITICAL 0.5PF +/-0.05PF 25V CERM 201 C5820 CRITICAL +/-0.05PF 201 25V 0.5PF CERM C5811 0201 2.0NH+/-0.1NH-0.6A CRITICAL C5814 CRITICAL 0201 1.0NH+/-0.1NH-0.75A C5824 0201 CRITICAL 1.0NH+/-0.1NH-0.75A C5813 +/-0.05PF 0201 CRITICAL 25V 0.2PF COG-CERM C5823 CRITICAL 25V +/-0.05PF 0.2PF COG-CERM 0201 U5820 SM DPX205850DT-9038A1SJ CRITICAL L5810 8.2NH+/-3%-0.25A-0.7OHM 0201 CRITICAL R5805 5% NOSTUFF 10K MF 1/32W 01005 10 48 53 10 5 5 53 5 5 53 48 52 5 53 U5800 CRITICAL WIFI-BT-DOPPELBOCK LGA WIFI/BT: MODULE SYNC_DATE=05/20/2013SYNC_MASTER=WIFI_DEV UART2_WLAN2SOC_TX HSIC1_SOC2WLAN_HOST_RDY RF_G_0_DIPLEXER RF_0_ANT_MATCH_T RF_A_0_DIPLEXER UART2_WLAN2SOC_TX_R HSIC1_SOC2WLAN_HOST_RDY_R RF_G_0_BAW_MODRF_G_0_BAW_ANT HSIC1_WLAN_STB JTAG_WLAN_SEL =PP1V8_S2R_VDDIO_WLAN_BT PMU_GPIO_CLK_32K_WLAN UART_WLAN2BB_LTE_COEX_R PMU_GPIO_BT_REG_ON UART_BB2WLAN_LTE_COEX =PP1V8_S2R_VDDIO_WLAN_BT HSIC1_WLAN_DATA PMU_GPIO_BT_REG_ON_R UART2_SOC2WLAN_TX_R RF_A_0_MATCH RF_G_1_MATCH_MOD RF_1_ANT_MATCH_T RF_0_ANT =PPVCC_MAIN_WLAN UART2_SOC2WLAN_TX UART_BB2WLAN_LTE_COEX_R UART_WLAN2BB_LTE_COEX PMU_GPIO_WLAN_REG_ON PMU_GPIO_CLK_32K_WLAN_R PMU_GPIO_WLAN_REG_ON_R OSCAR2RADIO_CONTEXT_A WLAN_TX_BLANK OSCAR2RADIO_CONTEXT_B =PP1V8_S2R_VDDIO_WLAN_BT WLAN_GPIO7 UART_BB2WLAN_LTE_COEX_R UART_WLAN2BB_LTE_COEX_R UART1_SOC2BT_TX GPIO_BT_WAKE PMU_GPIO_BT_HOST_WAKE I2S4_SOC2BT_LRCK I2S4_SOC2BT_BCLK UART1_BT2SOC_TX UART1_BT2SOC_RTS_L UART1_SOC2BT_RTS_L I2S4_SOC2BT_DATA I2S4_BT2SOC_DATA =PP3V3_S2R_WIFI_PA PMU_GPIO_CLK_32K_WLAN_R JTAG_WLAN_TMS_TX_BLANK HSIC1_WLAN2SOC_DEVICE_RDY UART2_SOC2WLAN_TX_R UART2_WLAN2SOC_TX_R HSIC1_WLAN2SOC_REMOTE_WAKE TP_JTAG_WLAN_TRST_L JTAG_WLAN_TDO_OSCAR_B JTAG_WLAN_TDI_OSCAR_A TP_JTAG_WLAN_TCK HSIC1_SOC2WLAN_HOST_RDY_R PMU_GPIO_WLAN_HOST_WAKE PMU_GPIO_WLAN_REG_ON_R PMU_GPIO_BT_REG_ON_R RF_A_1_MATCHRF_A_1_DIPLEXER RF_1_ANT RF_G_1_DIPLEXER RF_G_0_MATCH_MOD 051-0886 A.0.0 58 OF 121 44 OF 54 4 2 3 1 2 1 2 1 2 1 1 2 1 2 1 2 1 2 1 2 2 1 2 1 1 2 2 1 2 1 2 1 21 21 21 21 21 21 21 21 2 1 21 2 1 1 2 2 1 1 2 2 1 6 4 2 5 3 1 4 2 3 1 14 2 3 5 1 2 2 1 2 1 21 21 21 2 1 2 1 1 3 5 2 4 6 1 2 1 2 23 13 14 7 6 22 20 27 26 24 25 2 52 53 1 19 28 10 3 74 62 79 67 5 12 18 15 21 32 34 40 45 54 58 59 60 61 63 64 65 66 68 69 73 72 75 76 78 80 81 82 83 84 85 86 87 88 77 33 17 16 4 11 9 8 71 70 49 48 46 47 43 44 39 36 38 41 42 55 56 37 51 50 31 29 35 57 30 44 44 52 44 54 44 44 54 44 44 54 44 44 44 44 54 44 44 54 44 44 44 52 52 44 44 44
- 46. BI BI A A A Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM P/N 516S0906 C7522 33PF 5% NP0-C0G 16V 01005 10% 16V C7524 X7R-CERM 0201 1000PF XW7520 SM C7523 01005 16V 5% 33PF NP0-C0G 240-OHM-0.2A-0.8-OHM FL7500 0201-2 548 C7525 16V 5% 01005 27PF NP0-C0G 454852 TP7500 NOSTUFF TP-P55 TP7501 NOSTUFF TP-P55 TP7503 TP-P55 NOSTUFF CRITICAL J7500 CPB2304-0101F F-ST-SM C7526 01005 16V NP0-C0G 4.7PF +/-0.1PF POWER: BATTERY CONNECTOR SYNC_DATE=N/ASYNC_MASTER=N/A 155S0823 RADAR:8391945155S0644 FL7500,L1702,L1800,L1920,L2602,L2700,L2701,L2702,L2800,L2960,L2961,L2962,L2963,L38014_RF BATT_NTC NET_SPACING_TYPE=ANLG BATT_SNS NET_SPACING_TYPE=ANLG MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM =PPBATT_POS_CONN BATT_SWI_CONN BATT_NTC UART5_BATT_RTXD =PPBATT_POS_CONN BATT_SWI_CONN 051-0886 A.0.0 75 OF 121 45 OF 54 2 1 2 1 1 2 2 1 21 2 1 1 1 1 14 13 10 12 9 11 2 1 4 3 6 5 8 7 2 1 46 45 54 45 45 48 52 4554 45
- 47. S D G SYM 1 OF4 USB/BAT BUCK VCC-MAIN SWITCHEDPOWER VBAT IBAT_S IBAT0 IBAT1 IBAT2 IBAT3 VDD_BUCK1_01 VDD_BUCK0_01 VDD_BUCK0_23 BUCK5_FB BUCK4_LX0 BUCK3_FB BUCK3_LX0 BUCK2_FB BUCK2_LX0 BUCK1_FB BUCK6_FB ACT_DIO BUCK0_FB BUCK0_LX0 BUCK0_LX1 BUCK0_LX2 BUCK0_LX3 BUCK1_LX0 BUCK1_LX1 BUCK1_LX2 BUCK3_SW1 BUCK4_SW1 BUCK4_SW2 BUCK6_BYP0 BUCK6_BYP1 BUCK6_BYP2 CHG_LX0 CHG_LX1 CHG_LX2 CHG_LX3 VBUCK3 VBUCK4 VCC_MAIN_S VCC_MAIN VDD_BUCK3 VDD_BUCK6 VPUMP VBUS BUCK6_LX0 BUCK3_SW2 BUCK3_SW3 VDD_BUCK5 VDD_BUCK4 VDD_BUCK2 VDD_BUCK1_2 VBUS_OVP_OFF BUCK4_FB BUCK5_LX0 HV_CHG_DIS VCENTER S G D Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT ANYWHERE BET.TRISTAR R8173- PLACE NEAR PMU NOTE: FOR NO BATTERY SITUATION R8172- PLACE NEAR PMU NOTE: 10V ZENER RDSON=0.0136@VGS=-2.5V C8149- PLACE NEAR PMU LAYOUT NOTE - RIGHT AT THE PIN AT EACH VDD INPUT VCC_MAIN BYPASS 27UF (NO DERATING) ADDITIONAL DISTRIBUTED 27UF (NO DERATING) 64UF (NO DERATING) ADDITIONAL DISTRIBUTED ADDITIONAL DISTRIBUTED ADDITIONAL DISTRIBUTED 64UF (NO DERATING) ADDITIONAL DISTRIBUTED 32UF (NO DERATING) C8137 0201 OKAY IF GRAPE HAS EXT FET RIGHT AT THE PIN LAYOUT NOTE: PLACE LAYOUT NOTE: PLACE LAYOUT NOTE: R8146, C8146 CAN BE AND PMU USB REVERSE VOLTAGE PROTECTION +/- 25V FDMC6676BZ 6.9 A VGS MAX CHANNEL RDS(ON) IMAX PLACE TWO 10UF CAP MOSFET P-TYPE 27 MOHM @-4.5V ID=12.0A ESR MAX=70MOHMESR MAX=70MOHM DCR=54MOHM MAX CRITICAL 0402 4V 15UF X5R 20% C8101 R8100 1% MF 0.5 402 1/16W 0402 4V 15UF CRITICAL X5R 20% C8131 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C81A1 LLP CRITICAL BZT52C10LP DZ8120CRITICAL FDMC6676BZ MLP3.3X3.3 Q8123 1/20W 220K 1% MF 201 R8130 470K 1/20W MF 201 NOSTUFF 1% R8116 4V 0402 15UF CRITICAL X5R 20% C8102 4V 0402 15UF CRITICAL X5R 20% C8103 4V 0402 15UF CRITICAL X5R 20% C8107 4V 0402 15UF CRITICAL X5R 20% C8108 4V 0402 15UF CRITICAL X5R 20% C8100 0201 0.01UF 25V 10% NOSTUFF X5R-CERM C8146 4.7K MF 201 5% 1/20W R8146 PLACE_NEAR=U8100.L18:2MM C8147 X5R-CERM 0603 35V 10% 4.7UF CRITICAL 201 5% 1/20W MF NOSTUFF 4.7K R8170 CRITICAL 0402 15UF 4V X5R 20% C8115 4V 0402 15UF CRITICAL X5R 20% C8105 CRITICAL 15UF 4V 0402 X5R 20% C8114 20% 15UF 4V 0402 CRITICAL X5R C8118 15UF 4V 0402 CRITICAL X5R 20% C8122 0402 4V 15UF CRITICAL X5R 20% C8125 0402 15UF 4V CRITICAL X5R 20% C8121 SM XW8103 15UF 0402 4V CRITICAL X5R 20% C8124 SM XW8104 20% 0.22UF C8196 6.3V X5R 0201 OMIT_TABLE FCBGA D2089A0 U8100 6.3V X5R 0201-1 1.0UF 20% C8137 20% 10UF 0402 CERM-X5R 6.3V C8152 CRITICAL CRITICAL 10UF 0402 CERM-X5R 6.3V C8153 20% CRITICAL 20% 10UF 0402 CERM-X5R 6.3V C8154 C8155 20% 10UF 0402 CERM-X5R 6.3V CRITICAL 10UF 0402 CERM-X5R 6.3V CRITICAL C8156 20% 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8157 C8180 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8179 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8186 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8185 20% 10UF CERM-X5R 6.3V CRITICAL 0402 XW8101 SM C8184 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8151 CERM-X5R 6.3V 20% 10UF 0402 CRITICAL 0402 CERM-X5R 6.3V 10UF C8178 CRITICAL 20% C8177 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8150 6.3V CERM-X5R 0402 10UF 20% CRITICAL C8176 20% 10UF 0402 CERM-X5R 6.3V CRITICAL 10UF CRITICAL 6.3V CERM-X5R 0402 20% C8166 10UF C8165 CRITICAL 6.3V 0402 20% CERM-X5R C8164 CRITICAL 6.3V CERM-X5R 0402 10UF 20% 6.3V 0402 CERM-X5R C8163 CRITICAL 10UF 20% C8162 6.3V CERM-X5R 0402 10UF 20% CRITICAL C8183 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8182 20% 0402 CERM-X5R 6.3V CRITICAL 10UF C8181 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8172 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C8171 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C8170 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C8169 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C8188 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8168 6.3V CERM-X5R 0402 10UF 20% CRITICAL C8187 20% 0402 CRITICAL 10UF 6.3V CERM-X5R C8167 CRITICAL 6.3V CERM-X5R 10UF 20% 0402 C8161 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8160 CRITICAL 6.3V CERM-X5R 0402 10UF 20% CRITICAL 6.3V CERM-X5R 0402 10UF 20% C8159 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C8158 0201 C0G-CERM C8143 5% 25V 18PF C8193 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8194 CRITICAL CERM-X5R 20% 10UF 0402 6.3V 82PF CERM 5% 0201 25V C8142 PLACE_NEAR=U8100.F16:10MM X5R-CERM CRITICAL 25V 10% 2.2UF 603 C8145 0402 15UF 4V CRITICAL X5R 20% C8104 X5R 0402 15UF 4V CRITICAL 20% C8111 15UF 4V 0402 CRITICAL X5R 20% C8110 15UF 0402 4V CRITICAL X5R 20% C8119 20% 1.0UF 0201-1 X5R 6.3V CRITICAL C8144 0402 15UF 4V CRITICAL X5R 20% C8123 15UF 4V 0402 CRITICAL X5R 20% C8126 15UF 4V 0402 CRITICAL X5R 20% C8129 15UF 4V 0402 CRITICAL X5R 20% C8132 4V 0402 15UF CRITICAL X5R 20% C8109 0402 15UF 4V CRITICAL X5R 20% C8116 4V 0402 15UF CRITICAL X5R 20% C8120 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C81A2 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C81A3 6.3V X5R 0201-1 1.0UF 20% C81A9 6.3V X5R 0201-1 1.0UF 20% C81A8 1.0UH-3.33A-66MOHM CRITICAL L8110 PILE20161D-SM CRITICAL 15UF 4V 0402 X5R 20% C8112 PILE25201D 2.2UH-2.35A-0.073OHM L8111 CRITICAL L8100 PILE25201D 1.0UH-3.51A-0.036OHM CRITICAL L8101 PILE25201D CRITICAL 1.0UH-3.51A-0.036OHM L8102 CRITICAL PILE25201D 1.0UH-3.51A-0.036OHM CRITICAL L8103 PILE25201D 1.0UH-3.51A-0.036OHM L8104 PILE25201D 1.0UH-3.51A-0.036OHM CRITICAL L8105 CRITICAL PILE25201D 1.0UH-3.51A-0.036OHM L8106 CRITICAL PILE25201D 1.0UH-3.51A-0.036OHM L8107 1.0UH-3.51A-0.036OHM CRITICAL PILE25201D L8108 1.0UH-3.51A-0.036OHM CRITICAL PILE25201D L8109 PILE25201D 1.0UH-3.51A-0.036OHM CRITICAL CRITICAL 6.3V CERM-X5R 0402 10UF 20% C81A7 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C81A6 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C81A5 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C81A4 0402 4V 15UF CRITICAL X5R 20% C8117 20% 6.3V CRITICAL 100UF TANT-POLY PLACEMENT_NOTE=PLACE NEAR L8225.1 C8190 B1G-1 2.2UH-20%-5.5A-0.054OHM L8112 PIME061D-SM CRITICAL 4V 0402 15UF CRITICAL X5R 20% C8106 15UF 4V 0402 CRITICAL X5R 20% C8127 SM XW8102 SM XW8105 15UF 0402 4V CRITICAL X5R 20% C8130 CRITICAL 6.3V CERM-X5R 0402 10UF 20% C81A0 CRITICAL 15UF X5R 0402 4V 20% C8113 XW8106 SM SM XW8107 402 1UF CERM 10% 6.3V C8139 6.3V X5R 0201-1 1.0UF 20% C8138 402 CERM 10% 1UF 6.3V C8136 6.3V X5R 0201-1 1.0UF 20% C8135 R8173 201 1/20W 1% MF 499 PLACE_NEAR=U8100.R17:10MM C8175 CERM-X5R 6.3V CRITICAL 10UF 0402 20% CRITICAL C8141 TANT-POLY 100UF 6.3V 20% B1G-1 TANT-POLY 100UF C8140 CRITICAL 6.3V 20% PLACEMENT_NOTE=PLACE NEAR L8225.1 B1G-1 PMEG4030ER CRITICAL D8100 SOD-123W PLACE_NEAR=U8100.R17:10MM 0402 C8149 NOSTUFF 25V 10% 0.022UF X7R PLACE_NEAR=U8100.R17:2MM 0 R8172 MF 201 1/20W 5% SHORT-0201 XW8114 C8148 CRITICAL PLACE_NEAR=U8100.F18:2MM 4.7UF 35V X5R-CERM 0603 10% 4V 0402 15UF CRITICAL X5R 20% C8128 CRITICAL Q8104 FDMC6683 MLP3.3X3.3 SYNC_DATE=11/26/2012 PMU: ANYA PAGE 1 SYNC_MASTER=J72_MLB_C SWITCH_NODE=TRUE MIN_NECK_WIDTH=0.20MM BUCK3_LX0 MIN_LINE_WIDTH=0.60MM MAX_NECK_LENGTH=0.5 MM DIDT=TRUE NET_SPACING_TYPE=PWR OVP_SW_EN_L PPVBUS_PROT MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.20MM VOLTAGE=6.0V NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM PPBATT_VCC PPBATT_VCC =PPVCC_MAIN_CPU VBUS_PROT_G MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=ANLG BATT_SNS_RBATT_SNS NET_SPACING_TYPE=ANLG ACT_DIO MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.1 MM MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.60MM PMU_VCENTER VOLTAGE=6.0V MIN_NECK_WIDTH=0.20MM =PPVCC_MAIN_GPU MAX_NECK_LENGTH=0.5 MM MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR BUCK0_LX1 DIDT=TRUE SWITCH_NODE=TRUE BUCK0_LX3 SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=0.5 MM DIDT=TRUE DIDT=TRUE MAX_NECK_LENGTH=0.5 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.60MM BUCK0_LX2 MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE PPBATT_POS_RC VOLTAGE=4.7V NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM BUCK0_FB MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.25MM BUCK5_FB MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.25MM BUCK6_FB MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM BUCK1_FB MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.25MM BUCK2_FB MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM BUCK3_FB MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.20MM BUCK4_FB PPVBUS_USB_DCIN PPVDD_CPU MAX_NECK_LENGTH=0.5 MM NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.60MM BUCK0_LX0 DIDT=TRUE SWITCH_NODE=TRUE PPVDD_GPU PPVDD_SOC PP1V8_S2R PP1V2_S2R PP1V2_S2R_SW2 PP1V8_S2R_SW3 PP1V8_SW2 MAX_NECK_LENGTH=0.5 MM MIN_LINE_WIDTH=0.60MM BUCK1_LX0 MIN_NECK_WIDTH=0.20MM DIDT=TRUE NET_SPACING_TYPE=PWR SWITCH_NODE=TRUE MAX_NECK_LENGTH=0.5 MM MIN_LINE_WIDTH=0.60MM NET_SPACING_TYPE=PWR DIDT=TRUE MIN_NECK_WIDTH=0.20MM BUCK1_LX1 SWITCH_NODE=TRUE BUCK1_LX2 MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20MM NET_SPACING_TYPE=PWR DIDT=TRUE MAX_NECK_LENGTH=0.5 MM SWITCH_NODE=TRUE DIDT=TRUE MAX_NECK_LENGTH=0.5 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.60MM BUCK2_LX0 MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE DIDT=TRUE NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.60MM MAX_NECK_LENGTH=0.5 MM BUCK4_LX0 MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE MAX_NECK_LENGTH=0.5 MM NET_SPACING_TYPE=PWR DIDT=TRUE MIN_LINE_WIDTH=0.60MM BUCK5_LX0 MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE DIDT=TRUE MAX_NECK_LENGTH=0.5 MM MIN_LINE_WIDTH=0.60MM NET_SPACING_TYPE=PWR BUCK6_LX0 MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE PP1V8_SW1 =PPVCC_MAIN_CPU =PPVCC_MAIN_GPU PP1V2_S2R PP1V2_SW1 PP1V8_S2R =PPVCC_MAIN_SOC PPVCC_MAIN MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.30MM PMU_VPUMP NET_SPACING_TYPE=PWR VOLTAGE=4.6V TP_HV_CHG_EN OVP_SW_EN_L USB_VBUS_DETECT VOLTAGE=6.0V MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM =PPVCC_MAIN_SOC PPVCC_MAIN NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.20 MM DIDT=TRUE SWITCH_NODE=TRUE SW_CHGA OVP_SW_EN_L_R PPVCC_MAIN PP3V3_S2R PPVDD_SRAM 46 OF 54 051-0886 A.0.0 81 OF 121 2 1 1 2 2 1 2 1 KA 3 2 1 5 4 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 1 2 2 1 R17 P17 M19 N19 P19 R19 N2 V5 P1 P2 F1 K2 K1 F2 G17 G18 P6 B7 A7 E6 B5 A5 P7 V7 U7 M6 F6 N17 H6 E1 E2 G1 G2 J1 J2 L1 L2 N1 R1 R2 U1 U2 A12 B12 C12 C13 A9 B9 C9 C10 A10 A1 A2 A3 G19 H19 J19 K19 B13 B14 C14 B10 B11 C11 L17 H16 H17 J17 K16 K17 L16 T16 M18 N18 P18 R18 J18 A4 B4 B1 B2 B3 A11 F16 F17 G16 C1 A13 A14 V4 U4 B8 A8 V8 U8 V3 V2 V1 K18 L18 L19 C16 F19 C2 E7 U5 D17 H18 F18 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 21 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 1 2 1 1 2 21 2 1 2 1 1 2 1 2 2 1 2 1 2 1 1 2 1 2 2 1 2 1 2 1 2 1 1 2 2 1 1 2 1 2 K A 2 1 1 2 12 2 1 2 1 1 2 5 3 4 1146 1152 465254 465254 4654 45 4654 5254 52 54 52 54 52 54 46 47 52 54 46 47 52 54 52 54 54 52 54 50 52 54 4654 4654 46 47 52 54 52 54 46 47 52 54 4654 464748495254 1146 4 4654 464748495254 52 46 47 48 49 52 54 52 54 52 54
- 48. LDOINPUT LDO SYM 2 OF4 LCM/GRAPE LCDBACKLIGHT XTAL VDD_LDO9 VDD_LDO10 WLED_LXA0 VDD_LDO13 VDD_LDO11 WLED3_A WLED2_A WLED1_A VOUT_WLED_A WLED_LXA1 WLED2_B VLCM3 LCM2_EN VDD_LDO5 VDD_LDO1_3_4 VDD_LDO7 VDD_LDO6 VOUT_WLED_B VDD_LCM_SW VDD_BOOST_LCM XTAL2 XTAL1 WLED6_B WLED6_A WLED5_B WLED5_A WLED4_B WLED4_A WLED3_B WLED1_B WLED_LXB1 WLED_LXB0 VLDO7 VLDO6 VLDO5 VLDO4 VLDO3 VLDO2 VLDO1 VLCM2 VLCM1 VDD_LDO8 VDD_LCM LCM_FB BOOST_LCM_LX VLDO8 VLDO9 VLDO10 ON_BUF VLDO13 VLDO11 VDD_LDO2 IN IN IN IN IN IN TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (NOTE: 2MHZ) 1 CAP PER PIN LDO INPUTS (300MA; 1.7-3.0V) (300MA; 1.2-3.0V) (150MA; 0.6-1.3V) (300MA; 1.7-3.0V) (300MA; 1.7-3.0V) (5MA; 1.8V; ON_BUFF) LDO OUTPUTS (50MA; 2.5-3.3V) (1000MA; 2.5-3.6V) (50MA; 2.5-3.3V) (50MA; 2.5-3.3V) LDO BYPASS (5MA; 5.0-6.0V) (100MA; 5.0-6.0V) (PPLED_OUT_A) (100MA; 5.0-6.0V) (100MA; 1.65-1.805V; BUCK3) (300MA; 1.7-3.0V) (150MA; 2.5-3.6V) C8230 CRITICAL 402 10% 6.3V X5R 2.2UF C8201 402 CERM 1UF 6.3V 10% CRITICAL D8230 PMEG2005AEL SOD882 VLS201612E-SM 2.2UH-1.05A-0.195OHM L8229 CRITICAL CRITICAL C8211 0402 4.7UF 10V X5R-CERM 20% C8210 20% X5R-CERM 10V 402 2.2UF C8212 25V 10UF 20% 0603 X5R-CERM C8203 1UF CERM 402 6.3V 10% PIME051E-SM 4.7UH-3.2A CRITICAL L8225 C8254 4.7UF 0603 10% 35V X5R-CERM CRITICAL 20% 4.7UF CRITICAL C8235 6.3V X5R 402 50V 56PF C8259 NP0-C0G-CERM 2% 0201 C8290 10V 20% X5R-CERM 4.7UF 0402 CRITICAL 5% C8280 0201 56PF NP0-C0G-CERM 25V 0201 C8281 5% 56PF NP0-C0G-CERM 25V 0201 C8282 5% 56PF NP0-C0G-CERM 25V 0201 5% 25V NP0-C0G-CERM 56PF C8283 0201 C8284 5% 56PF NP0-C0G-CERM 25V 0201 C8285 5% 56PF NP0-C0G-CERM 25V C8239 CRITICAL 402 X5R-CERM1 4.7UF 6.3V 20% 10UF 20% 6.3V CRITICAL CERM-X5R 0402 C8234 0402 10UF CERM-X5R 20% 6.3V CRITICAL C8240 10UF 0402 CERM-X5R 20% 6.3V CRITICAL C8241 6.3V C8237 CRITICAL 10% 2.2UF X5R 402 C8242 0201 6.3V X5R 0.22UF 20% 20% 10UF 0402 CERM-X5R 6.3V CRITICAL C8231 CRITICAL C8215 C0G-CERM 25V 5% 18PF 0201 CRITICAL Y8200 2012-1 32.768K-20PPM-12.5PF C0G-CERM CRITICAL C8216 5% 25V 18PF 0201 FCBGA U8100 OMIT_TABLE D2089A0 R8227 1/32W MF 1% 1.00 01005 0402 10UF CERM-X5R 20% 6.3V CRITICAL C8232 R8232 1.00 1/32W 1% MF 01005 R8239 1/32W 1% MF 01005 1.00 1.00 R8231 1/32W 1% MF 01005 R8235 1/32W 1.00 1% MF 01005 18 18 18 18 18 D8228 CRITICAL PMEG4010BEA SOD-323 C8253 CRITICAL X5R-CERM 0603 4.7UF 10% 35V R8240 1/32W 1% MF 1.00 01005 2.2UF X5R 10% 402 6.3V CRITICAL C8233 18 CRITICAL CERM-X5R 6.3V C8226 0402 20% 10UF C8252 CRITICAL X5R-CERM 35V 10% 0603 4.7UF 0603 35V 4.7UF C8251 CRITICAL 10% X5R-CERM 0603 C8250 CRITICAL X5R-CERM 10% 4.7UF 35V C8238 CRITICAL 6.3V X5R-CERM1 4.7UF 402 20% C8200 402 CERM 1UF 10% 6.3V 197S0399 197S0392 Y8200 RDAR://PROBLEM/9936684 PMU: ANYA PAGE 2 SYNC_MASTER=J85 MLB_C SYNC_DATE=12/03/2012 PP1V3_CAM PP3V0_SPARE1 PMU_EXTAL PP3V0_UVLO PP3V0_ALS PP1V7_VA_VCP PP2V6_CAM_AF PP3V0_S2R_TRISTAR PP3V0_UVLO PP3V3_ACC NC_LDO8 PP6V0_LCM_VBOOST VOLTAGE=6.0V MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2MM MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.4MM NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.4 MM DIDT=TRUE LCM_LX PP2V9_CAM PP1V3_CAM PP1V0_SOC MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4MM VOLTAGE=6.0V MIN_NECK_WIDTH=0.2MM PP6V0_LCM_HI NO_TEST=TRUE NC_VLCM2 NO_TEST=TRUE NC_VLCM3 PP1V8_S2R PPVCC_MAIN PP5V25_GRAPE =PPVCC_MAIN_VDD_LCM NC_WLED_LXB0 NC_WLED4_B NC_WLED_LXB1 NC_VOUT_WLED_B NC_WLED1_B NC_WLED2_B NC_WLED3_B NC_WLED6_B NC_WLED5_B PP1V7_VA_VCP PP3V0_SPARE1 PP1V0_SOC PP2V9_CAM PP2V6_CAM_AF PP3V0_S2R_SENSOR PP1V8_ALWAYS PPVCC_MAIN PP1V2_S2R PPVCC_MAIN PP3V0_ALS PP3V0_S2R_SENSOR LED_IO_5_A LED_IO_3_A LED_IO_4_A LED_IO_2_A LED_IO_1_A LED_IO_6_A LED_IO6_A_R LED_IO2_A_R LED_IO3_A_R LED_IO4_A_R LED_IO5_A_R NC_LCM2_EN PP3V0_S2R_TRISTAR PMU_XTAL PPLED_OUT_A WLED_LX_A NET_SPACING_TYPE=PWR DIDT=TRUE SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.6 MM PP1V8_ALWAYS PP3V3_ACC LED_IO1_A_R =PPVCC_MAIN_LED A.0.0 051-0886 47 OF 54 82 OF 121 2 1 2 1 A K 1 2 2 1 2 1 2 1 2 1 21 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 B15 B17 C18 T17 U16 G14 F14 E14 D16 C19 L14 U12 E8 U9 T18 U14 U10 E16 C17 A18 V17 V18 P14 J16 N14 J14 M16 H14 M14 K14 E19 E18 V14 V10 V9 T19 U18 A16 U19 V12 V11 U15 U11 C15 B19 V15 A15 A17 T10 U17 V16 B16 1 2 2 1 1 2 1 2 1 2 1 2 A K 2 1 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 475254 475254 475254 475254 16475254 47 52 54 47 52 54 47 52 54 47 52 54 54 52 47 52 54 47 52 54 47 52 54 465254 464748495254 54 54 16 47 52 54 47 52 54 475254 475254 475254 475254 475254 464748495254 465254 464748495254 47 52 54 47 52 54 52 52 52 52 52 475254 5254 47 52 54 475254 52 54
- 49. INPUT ANALOG CLK GPIOANALOGMUX TEMPERATUREI2C&DWIRESETWDOG DIGITAL INPUT 32KREFRENCES SYM 3 OF4 GPIO14 IRQ* RESET* RESET_IN1 RESET_IN2 RESET_IN3 TCAL TBAT GPIO16 SHDN KEEPACT TDEV4 GPIO13 GPIO12 GPIO11 BUTTON4 BUTTON3 ADC_IN31 ADC_REF AMUX_A0 DWI_CK DWI_DI DWI_DO GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO15 GPIO17 OUT_32K SCL SDA TDEV1 TDEV2 TDEV3 TDEV5 TDEV6 TDEV7 TDEV8 VDD_REF_A VDD_RTC AMUX_A1 AMUX_A2 AMUX_A3 AMUX_AY AMUX_B0 AMUX_B1 AMUX_BY AMUX_B3 AMUX_B2 BUTTON2 IREF VREF VDD_REF BUTTON1 ADC_IN7 ACC_DET ACC_ID BRICK_ID IN OUT IN IN IN IN IN NC OUT IN OUT IN GND VDD D SON CAP OUT OUT OUT OUT IN IN IN IN IN IN IN IN IN IN OUT OUT IN BI IN IN IN IN IN TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD TABLE_ALT_ITEM TABLE_ALT_ITEM PART NUMBER ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS: TABLE_ALT_HEAD Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT (TEMP8 - BOTTOM SIDE NEAR PMU) SWITCH NEEDED TO GATE POWER TO NAND AND SOC REVIEW: CHECK FOR POWER SEQUENCING VOILATIONS BETWEEN PP1V8 AND PP3V3 BUCK6 POWER IS ON IN HIBERNATE DUE TO WIFI PAS (TEMP3 - TOP SIDE NEAR WIFI) I2C ADDRESS: 0111100X (0X78) (INTERNAL PULL-DOWN) REVIEW: VERIFY NC ON TDEV2 IS OK PLACE XW AND CAP CLOSE TO PMU (INTERNAL PULL-DOWN) (INTERNAL PULL-DOWN) (PULLUP INSIDE SOC) (INTERNAL PULL-DOWN) RESISTOR FOR TEMP CALIBRATION (TEMP1 - NEAR BB) (TEMP7 - BOTTOM SIDE NEAR SOC) (TEMP6 TOP SIDE NEAR REAR CAM) (TEMP4 - TOP SIDE NEAR SIM) (TEMP5 - TOP SIDE NEAR NAND) NOTE: NEW ON J85 R8324 CRITICAL 10KOHM-1%-0.31MA 0201 PLACE_SIDE=TOP PLACE_NEAR=J2800.1:10MM C8324 100PF 01005 5% 16V NP0-C0G PLACE_NEAR=U8100.M4:10MM C8323 100PF 5% 01005 16V NP0-C0G PLACE_NEAR=U8100.L4:10MM R8340 MF 3.92K 0.1% 1/20W 0201 CRITICAL 5% 100PF 01005 NP0-C0G 16V C8340 XW8322 SM PLACE_NEAR=U8100.R14:10MM C8322 01005 5% 100PF 16V NP0-C0G PLACE_NEAR=U8100.R14:10MM PLACE_NEAR=U8100.R13:10MM SM XW8321 PLACE_NEAR=U5800.30:10MM R8321 CRITICAL 0201 10KOHM-1%-0.31MA PLACE_SIDE=TOP C8321 100PF 5% 01005 16V NP0-C0G PLACE_NEAR=U8100.R13:10MM 1.0UF X5R-CERM 10V 20% 0201-1 C8308 PLACE_NEAR=U8100.M17:4MM PLACE_NEAR=U8100.K9:10MM PLACE_SIDE=BOTTOM R8326 CRITICAL 10KOHM-1%-0.31MA 0201 C8326 01005 100PF 5% 16V NP0-C0G PLACE_NEAR=U8100.P4:10MM PLACE_SIDE=BOTTOM R8325 0201 10KOHM-1%-0.31MA CRITICAL PLACE_NEAR=U0600.W19:10MM 01005 C8325 5% 100PF 16V NP0-C0G PLACE_NEAR=U8100.N4:10MM R8303 200K 1% 1/20W MF 201 U8100 OMIT_TABLE FCBGA D2089A0 PLACE_NEAR=UJ000.8:10MM PLACE_SIDE=TOP R8322 CRITICAL 10KOHM-1%-0.31MA 0201 XW8323 SM PLACE_NEAR=U8100.L4:10MM XW8324 SM PLACE_NEAR=U8100.M4:10MM XW8325 SM PLACE_NEAR=U8100.N4:10MM XW8326 SM PLACE_NEAR=U8100.P4:10MM 5 19 24 27 52 5 C8307 X5R 10V 1UF 10% 402-1 PLACE_NEAR=U8100.T11:3MM 13 43 C8305 CERM-X5R 6.3V 10% 0.1UF 0201 11 1/20W MF 0.00 1% 0201 R8399 11 R8327 CRITICAL 10KOHM-1%-0.31MA 0201 PLACE_SIDE=TOP PLACE_NEAR=U4000.1:10MM C8327 01005 5% 100PF 16V NP0-C0G PLACE_NEAR=U8100.R9:10MM 6.3V C8306 CERM-X5R 0.1UF 10% 0201 XW8327 SM PLACE_NEAR=U8100.R9:10MM 5% 1.00K 1/32W 01005 R8330 MF 24 26 52 13 15 13 6.3V X5R 0201-1 1.0UF 20% C8355 CRITICAL 10UF 0402-2 10V X5R-CERM 20% C8356 TDFN SLG5AP1443V CRITICAL U8350 C8352 10V X7R 201 4700PF CRITICAL 10% C8350 0.1UF 0201 10% 16V X5R-CERM 5% 1/32W 01005 MF 100K R8352 44 52 19 52 44 52 44 52 5 45 44 52 44 53 24 28 52 PLACE_SIDE=TOP R8323 CRITICAL 10KOHM-1%-0.31MA 0201 PLACE_NEAR=U1600.A1:10MM 15 52 5 11 C8310 1000PF 6.3V 01005 X5R-CERM 10% 4552 5 10 4810112452 5 51152 51152 553 552 0.01UF 10% 01005 X5R 6.3V C8302C8301 0.01UF 01005 10% X5R 6.3V 01005 10% X5R 6.3V C8300 0.01UF 513 517 517 138S0706138S0739 C8308 RDAR://PROBLEM/8380367 118S0764 118S0717 R8340 R8321,R8322,R8323,R8324,R8325,R8326 107S0208107S0150 RDAR://PROBLEM/8380367 SYNC_MASTER=J72_MLB_C PMU: ANYA PAGE 3 SYNC_DATE=11/26/2012 NET_SPACING_TYPE=BOARD_TEMP BOARD_TEMP3_P BOARD_TEMP7_P NET_SPACING_TYPE=BOARD_TEMP BOARD_TEMP7_N BOARD_TEMP6_N VCC_MAIN_PP3V3SW_RAMP =PP1V8_NAND PPVCC_MAIN PP3V3_SW =PP3V3_S2R_SWITCH BOARD_TEMP4_N NC_ADC_SMPS3_MSME_1V8 NC_ADC_SMPS1_MSMC_1V05 NET_SPACING_TYPE=BOARD_TEMP BOARD_TEMP6_P PMU_TCALNET_SPACING_TYPE=ANLG UART5_BATT_RTXD WDOG_SOC2PMU_RESET_IN PMU_IREFNET_SPACING_TYPE=ANLG PMU_VREFNET_SPACING_TYPE=ANLG PMU_VDD_RTCNET_SPACING_TYPE=ANLG PMU_GPIO_MB_HALL1_IRQ PMU_E75_ACC_DET_L PMU_GPIO_PMU2BBPMU_RST_L PMU_GPIO_CLK_32K_WLAN PMU_GPIO_WLAN_REG_ON PMU_GPIO_BT_HOST_WAKE PMU_GPIO_WLAN_HOST_WAKE GPIO_TS2SOC2PMU_INT GPIO_SOC2PMU_KEEPACT PMU_SHDWN RESET_SOC_L GPIO_PMU2SOC_IRQ_L I2C0_SCL_1V8 I2C0_SDA_1V8 DWI_AP_DO DWI_AP_CLK GPIO_BTN_HOME_L GPIO_BTN_ONOFF_L PMU_GPIO_BT_REG_ON PMU_GPIO_CLK_32K_OSCAR PMU_GPIO_PMU2BBPMU_RST_R_L BOARD_TEMP5_N NC_PMU_OUT_32K_CLK_GPS BOARD_TEMP8_N BOARD_TEMP3_N SOCHOT1_L TS2PMU_RESET_IN PA_NTC_N PMU_GPIO_CODEC_HS_INT_L PMU_GPIO_BB2PMU_HOST_WAKE PMU_GPIO_BB_VBUS_DET PMU_GPIO_OSCAR2PMU_HOST_WAKE NC_PPVDD_SOC_SOC_SENSE NC_PPVDD_GPU_SOC_SENSE NC_PPVDD_CPU_SOC_SENSE NC_AMUX_AY NC_AMUX_BY NC_PPVDD_CPU_RAIL_SENSE NC_PPVDD_GPU_RAIL_SENSE NC_PPVDD_SOC_RAIL_SENSE PMU_GPIO_CODEC_RST_L PMU_GPIO_MB_HALL3_IRQ PMU_GPIO_MB_HALL2_IRQ PMU_ADC_REF MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.1MM NET_SPACING_TYPE=ANLG GPIO_BTN_SRL_L NC_ANYA_BUTTON4 BOARD_TEMP8_P NET_SPACING_TYPE=BOARD_TEMP PMU_USB_BRICKID BOARD_TEMP5_P NET_SPACING_TYPE=BOARD_TEMP PA_NTC_P NET_SPACING_TYPE=BOARD_TEMP PMU_ACC_ID ADC_IN7 PMU_USB_BRICKID_R BATT_NTC NET_SPACING_TYPE=ANLG NET_SPACING_TYPE=BOARD_TEMP BOARD_TEMP4_P NC_DWI_AP_DI NO_TEST=TRUE PMU_VDD_REFNET_SPACING_TYPE=ANLG 48 OF 54 83 OF 121 051-0886 A.0.0 2 1 2 1 2 1 1 2 2 1 1 22 1 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 E3 T15 R8 R5 R6 R7 R15 R16 C3 T9 T8 R14 F3 G3 H3 D8 D7 R11 T13 E4 E11 E10 E9 T6 T5 T4 R3 P3 N3 M3 L3 K3 J3 D3 C4 T14 E12 E13 R9 R10 R13 L4 M4 N4 P4 T11 U13 F4 G6 J6 G4 K4 J4 H4 L6 K6 D6 T12 V13 M17 D5 N16 T7 R12 P16 2 1 1 2 1 2 1 2 1 2 2 1 2 1 1 2 2 1 2 1 2 1 1 2 1 2 2 1 2 1 81 3 52 7 2 1 2 1 1 2 2 1 2 1 2 1 2 1 2 1 52 52 1254 4647495254 52 54 54 52 52 52 52 52
- 50. SYM 4 OF4 VSS_BUCK0_12 VSS_LCM VSS_BUCK25 VSS VSS_WLED VSS_BUCK1_12 VSS_BUCK34 VSS_BUCK06 VSS_BUCK01 VSS G S D VCC REF VEE OUT Apple Inc. THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT THROTTLER ADD A VIA PER PIN FOR ALL VSS_* AND VSSA_* PINS APN 353S4103 U8100 D2089A0 FCBGA OMIT_TABLE DMN2990UFA DFN0806-VML0806-COMBO-N78 Q8440 C8400 X5R-CERM 6.3V 20% 0.1UF 01005 100K 01005 1/32W MF 5% R8435 MAX9039BEBT+ UCSP U8400 255K R8430 01005 MF 1/32W 1% R8410 MF 1/32W 1% 01005 75K 01005 1% 1/32W MF R8411 50K 01005 MF 1.00K 1/32W 1% R8425 SHORT-10L-0.1MM-SM XW8410 01005 MF 1/32W R8420 150K 1% NOSTUFF 150K 1% 1/32W MF R8450 01005 NOSTUFF 01005 R8451 MF 1/32W 4.7K 1% NOSTUFF 5% 100PF CERM 6.3V C8460 01005 5 52 MF 1/32W 0.00 0% R8445 01005 SYNC_MASTER=J72_MLB_C PMU: ANYA PAGE 4 SYNC_DATE=11/26/2012 UVLO_COMP_NEG =PP3V0_UVLO PPVCC_MAIN THROTTLER_OUT UVLO_COMP_REF UVLO_COMP_REF =PP3V0_SPARE1 SOCHOT0_R_L SOCHOT0_L MAIN_UVLO_SENSE_R VCC_MAIN_UVLO_SENSE UVLO_COMP_POS 84 OF 121 49 OF 54 051-0886 A.0.0 D2 H1 F7 D14 B18 U6 H13 H12 H11 H10 F13 F12 F11 E17 D13 D10 D9 C8 C7 C6 C5 D4 V19 D15 A19 D12 D19 D18 D11 V6 H2 T1 T2 A6 B6 D1 F10 F9 F8 G8 G7 G10 G9 G13 G11 G12 H7 H8 H9 M1 M2 J7 J8 J9 J10 J11 J13 J12 K8 K7 K9 K10 K11 K12 K13 L7 L8 L9 L10 L12 L11 L13 M7 M8 M9 M10 M11 M12 N7 N6 M13 N9 N8 N10 N12 N11 P8 N13 P9 P11 P10 P12 P13 R4 U3 T3 3 1 2 2 1 1 2 A3 B3 A1 A2 B1 B2 1 2 1 2 1 2 1 2 21 1 2 1 2 1 2 2 1 1 2 54 4647485254 49 49 54
- 51. GND VOUT ON VIN Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT SWITCH TO GATE POWER TO SOC AND NAND. NEEDED FOR J72 ROUTING. CSP U8550 CRITICAL TPS22924X C8555 01005 0.01UF 6.3V 10% X5R C8550 10V X5R-CERM 0402-2 10UF 20% SYNC_DATE=11/26/2012 POWER: PP1V8_SW SYNC_MASTER=J85 MLB_C PP1V8_EXT_SW=PP1V8_S2R_EXT_SWITCH PP1V8_SW1 051-0886 A.0.0 85 OF 121 50 OF 54 C1 A1 B1 C2 B2 A2 2 1 2 1 52 5454 465254
- 52. SCL SDA VSS VCC A Apple Inc. THEINFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT SEP EEPROM UNPROGRAMMED P/N: 335S0894 DEBUG CRITICAL WLCSP CAT24C08C4A U9000 0201 20% 0.22UF 6.3V X5R C9000 TP9002 TP-P55 SEP: EEPROM & SOC DEBUG SYNC_DATE=11/26/2012SYNC_MASTER=J72_MLB_C SEP_I2C0_SDA =PP1V8_EEPROM SEP_I2C0_SCL =PP1V8_S2R_MISC 051-0886 A.0.0 90 OF 121 51 OF 54 B1 B2 A2A1 2 1 1 5 54 5 554
- 53. A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT STANDOFFS: P/N 860-1657 860-1688 STANDOFF: P/N 860-1683 DRILL SIZE: 1.1MM X 0.4MM PLATED THROUGH HOLES PLATING SIZE: 1.4MM X 0.7MM NEAR BUTTON FLEX CONN RF TEST POINTS SL-1.1X0.4-1.4X0.7 TH-NSP SL9305 SL-1.1X0.4-1.4X0.7 TH-NSP SL9304 TP9303 TP-P5 TP-P5 TP9306 TP-P5 TP9307 TP-P5 TP9308 TP-P5 TP9309 TP-P5 TP9311 TP-P5 TP9310 TP-P5 TP9312 TP-P5 TP9313 TP-P5 TP9314 TP-P5 TP9316 TP-P5 TP9315 TP-P5 TP9317 TP-P5 TP9318 TP-P5 TP9321 TP-P5 TP9320 TP9322 TP-P5 TP-P5 TP9323 TP-P5 TP9324 TP-P5 TP9325 TP-P5 TP9326 TP-P5 TP9327 TP-P5 TP9328 TP-P5 TP9330 TP-P5 TP9329 TP-P5 TP9331 TP-P5 TP9332 TP-P5 TP9334 TP-P5 TP9333 TP-P5 TP9336 TP-P5 TP9335 TP-P5 TP9338 TP-P5 TP9337 TP-P5 TP9339 TP9340 TP-P5 TP-P5 TP9341 TP-P5 TP9342 TP-P5 TP9344 TP-P5 TP9343 TP-P5 TP9346 TP-P5 TP9345 TP-P5 TP9348 TP-P5 TP9347 TP-P5 TP9350 TP-P5 TP9349 TP-P5 TP9352 TP-P5 TP9351 TP-P5 TP9353 TP-P5 TP9354 TP-P5 TP9356 TP-P5 TP9355 TP-P5 TP9357 TP-P5 TP9358 TP-P5 TP9359 TP9360 TP-P5 TP-P5 TP9361 TP-P5 TP9362 TP-P5 TP9363 TP-P5 TP9364 TP-P5 TP9365 TP9366 TP-P5 TP-P5 TP9367 TP9368 TP-P5 TP9369 TP-P5 TP9370 TP-P5 TP9371 TP-P5 TP-P5 TP9373 TP-P5 TP9372 TP-P5 TP9374 TP-P5 TP9375 TP-P5 TP9377 TP-P5 TP9376 TP-P5 TP9378 TP-P5 TP9379 TP9380 TP-P5 TP9381 TP-P5 TP-P5 TP9382 TP-P5 TP9383 TP9384 TP-P5 TP9385 TP-P5 TP9387 TP-P5 TP-P5 TP9388 TP-P5 TP9389 TP-P5 TP9390 TP-P5 TP9391 TP-P5 TP9393 TP-P5 TP9395 TP-P5 TP93A0 TP-P5 TP93A1 TP-P5 TP93A2 TP-P5 TP93A3 TP93A4 TP-P5 TP-P5 TP93A6 TP-P5 TP93A7 TP-P5 TP93A8 TP-P5 TP93B0 TP-P5 TP93A9 TP93B8 TP-P5 TP-P5 TP93C0 TP93C1 TP-P5 TP-P5 TP93C3 TP-P5 TP93C4 TP-P5 TP93C5 TP-P5 TP93C6 TP93C8 TP-P5 TP-P5 TP93C9 TP-P5 TP93D0 TP-P5 TP93D1 TP-P5 TP93D2 TP-P5 TP93D3 TP-P5 TP93D5 TP-P5 TP93D4 TP-P5 TP93D6 TP-P5 TP93D7 TP-P5 TP93D8 TP-P5 TP93D9 TP-P5 TP93E0 TP-P5 TP93E1 TP93F3 TP-P5 TP93G1 TP-P5 TP93G4 TP-P5 TP-P5 TP93G6 TP93G5 TP-P5 TP93H2 TP-P5 TP-P5 TP93H1 TP93G9 TP-P5 TP93H5 TP-P5 TP-P5 TP93H6 TP-P5 TP93H4 TP-P5 TP93H3 TP93H9 TP-P5 TP93I0 TP-P5 TP-P5 TP93H7 TP-P5 TP93H8 TP-P5 TP93I4 TP93I3 TP-P5 TP-P5 TP93I2 TP-P5 TP93I1 TP-P5 TP93I8 TP-P5 TP93I7 TP-P5 TP93I5 TP-P5 TP93I6 TP-P5 TP93I9 TP-P5 TP93J0 TP-P5 TP93J1 SL9303 SL-1.1X0.4-1.4X0.7 TH-NSP MH9300 3P25R2P5 TP-P5 TP9301 TP-P5 TP9302 TP-P5 TP93B9 TP-P5 TP93E7 TP-P5 TP93E8 TP93J2 TP-P5 TP-P5 TP93J3 TP-P5 TP93J4 TP93J5 TP-P5 TP-P5 TP93J6 TP-P5 TP93J7 TP-P5 TP93J8 STD9300 STDOFF-3.3X1.8R1.28H-SM STD9301 STDOFF-3.3X1.8R1.28H-SM STDOFF-3.3X2.2R1.35H-SM-1 STD9302 TP-P5 TP9300 TP-P5 TP9304 TP-P5 TP93J9 TP-P5 TP93JA TP-P5 TP93JB TP-P5 TP93JC TP-P5 TP9305 TP-P5 TP9396 TP-P5 TP9397 TP-P5 TP9398 WASHER-BTN-MLB-X221 MH9302 TH SL9300TH-NSP SL-1.1X0.4-1.4X0.7 SYNC_DATE=12/03/12SYNC_MASTER=J85 MLB_C TEST: TP/HOLES/FIDUCIALS PPLED_BACK_REG_A ISP1_CAM_FRONT_SDA PP2V9_CAM PP_SMPS1_MSMC_1V05 PP_SMPS5_DSP_1V05 TP_BB_TEST_MODE_0 SIMCRD_RST_CONN SOCHOT0_L PP3V0_SPARE1 PPLED_OUT_A BATT_NTC PMU_GPIO_BT_REG_ON PMU_GPIO_BT_HOST_WAKE ISP0_CAM_REAR_SHUTDOWN_L UART6_TS_ACC_RXD PP1V3_CAM PP3V0_ALS PP_SMPS3_MSME_1V8 GPIO_CODEC_IRQ_L PPVDD_CPU PP1V8_GRAPE_SW PP1V8_EXT_SW SIMCRD_CLK_CONN PMU_GPIO_CODEC_HS_INT_L CLK_32K_SOC2CUMULUS PP1V0_SOC PMU_USB_BRICKID_R UART3_SOC2BB_TX UART6_TS_ACC_TXD PP1V8_SW2 PP1V8_ALWAYS SPKR_L_CONN_P SPKR_R_CONN_N PMU_GPIO_CLK_32K_WLAN PP1V2_S2R GPIO_SOC2BB_RST_L BB_JTAG_TMS USB_BB_N BB_JTAG_TRST_L RESET_SOC_L PP3V3_S2R PP5V25_GRAPE_FILT PPVBUS_USB_DCIN LED_IO2_A_R I2C2_SCL_1V8 PPBATT_VCC PP1V2_S2R_SW2 BOARD_TEMP3_P BOARD_TEMP4_P BOARD_TEMP5_P BOARD_TEMP7_P BOARD_TEMP6_P BOARD_TEMP8_P CODEC_HP_DET_R CODEC_HP_LEFT CODEC_HP_RIGHT DISPLAY_SYNC_R E75_DPAIR1_CONN_N DWI_AP_CLK E75_DPAIR1_CONN_P FMI1_CE0_L GND_AUDIO_CODEC GPIO_BTN_HOME_FILT_L GPIO_BTN_ONOFF_L_FILT GPIO_BTN_SRL_L_FILT GPIO_BTN_VOL_DOWN_L_FILT GPIO_BTN_VOL_UP_L_FILT GPIO_FORCE_DFU GPIO_GRAPE_IRQ_L GPIO_GRAPE_RST_L GPIO_SOC2BB_WAKE_MODEM GPIO_SPKAMP_KEEPALIVE I2C0_SCL_1V8 I2C0_SDA_1V8 I2C2_SDA_1V8 ISP0_CAM_REAR_CLK ISP0_CAM_REAR_SCL ISP0_CAM_REAR_SDA ISP1_CAM_FRONT_CLK ISP1_CAM_FRONT_SCL ISP1_CAM_FRONT_SHUTDOWN_L JTAG_SOC_TCK JTAG_SOC_TDI JTAG_SOC_TMS JTAG_SOC_TRST_L JTAG_WLAN_SEL OSCAR2RADIO_CONTEXT_A WLAN_TX_BLANK LAT_SW2_CTL LED_IO1_A_R LED_IO6_A_R MIKEY_TS_N MIKEY_TS_P OVP_SW_EN_L_R PMU_GPIO_CLK_32K_OSCAR PP1V7_VA_VCP PP1V8_PLL_SOC_F PP1V8_SW1 PP1V8_S2R_SW3_COMP PP2V6_CAM_AF PP3V0_S2R_HALL_FILT PP3V0_S2R_TRISTAR PP3V0_S2R_SENSOR PP3V3_ACC PP3V3_SW PP6V0_LCM_VBOOST PPOUT_E75_ACC_ID2_CONN PPOUT_E75_ACC_ID1_CONN PPVBUS_PROT PPVCC_MAIN_LCD_SW_CONN PPVCC_MAIN PPVDD_GPU PPVDD_SRAM PPVDD_SOC PP_SMPS4_RF2_2V05 SPKR_R_CONN_P UART0_SOC_RXD TP_JTAG_WLAN_TCK TP_JTAG_WLAN_TRST_L TP_JTAG_SOC_TDO UART3_BB2SOC_TX UART0_SOC_TXD USB_SOC_P USB_SOC_N JTAG_SOC_SEL SPKR_L_CONN_N TP_BB_TEST_MODE_1 PP_LDO1 PP_LDO6_RUIM_1V8 PMU_GPIO_BB2PMU_HOST_WAKE DEBUG_RST_L BB_JTAG_RTCLK BB_JTAG_TDI BB_JTAG_TDO SIMCRD_IO_CONN SIM_TRAY_DETECT GPIO_SOC2BB_RADIO_ON_L PMU_GPIO_PMU2BBPMU_RST_L PS_HOLD_PMIC USB_BB_P PMU_GPIO_BB_VBUS_DET PP1V8_GRAPE_FILT SOC_TESTMODE LAT_SW1_CTL OSCAR2RADIO_CONTEXT_B PP1V8_XTAL CODEC_HP_HS3 CODEC_HP_HS4_REF CODEC_HP_HS4 CODEC_HP_HS3_REF GND FMI0_CE0_L E75_DPAIR2_CONN_P E75_DPAIR2_CONN_N LED_IO5_A_R LED_IO4_A_R LED_IO3_A_R SPI1_GRAPE_SCLK_R SPI1_GRAPE_MOSI SPI1_GRAPE_MISO BB_JTAG_TCK PP1V2_SW1 SPI1_GRAPE_CS_L PP1V8_S2R PMU_GPIO_WLAN_REG_ON PP3V0_UVLO 051-0886 A.0.0 93 OF 121 52 OF 54 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 18 7 20 47 54 25 27 25 27 10 24 28 5 49 47 54 47 54 45 48 44 48 44 48 7 23 5 11 47 54 47 54 24 25 27 28 30 5 15 46 54 13 50 54 10 24 28 15 48 5 13 47 54 48 5 11 24 28 5 11 46 54 47 54 16 43 16 43 44 48 46 47 54 5 24 26 5 24 27 11 24 53 5 24 27 4 8 10 11 24 48 46 54 13 46 54 47 5 16 46 54 46 54 48 48 48 48 48 48 15 15 15 13 43 5 48 43 6 12 15 13 17 17 17 17 5 5 13 5 13 5 28 5 16 5 11 48 5 11 48 5 16 7 23 7 23 7 23 7 20 7 20 7 20 4 11 4 4 11 4 10 44 19 28 44 28 44 14 28 47 47 11 15 11 15 46 19 48 16 47 54 4 46 50 54 54 47 54 13 47 54 47 54 47 54 48 54 47 43 43 11 46 18 46 47 48 49 54 46 54 46 54 46 54 25 30 16 43 5 11 44 44 4 5 11 24 28 5 11 4 11 4 11 4 10 16 43 27 25 10 24 25 27 24 28 48 24 27 24 27 5 24 27 5 24 27 10 24 28 10 24 28 5 24 26 24 26 48 24 26 11 24 53 24 27 48 13 4 10 14 24 28 19 28 44 8 15 15 15 15 6 12 43 43 47 47 47 13 5 13 5 13 5 24 27 46 54 5 13 46 47 54 44 48 47 54
- 54. PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP PP Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT NAND UART5 OSCAR GRAPE PROX FOR HSIC CHARACTERIZATION BASEBAND FOR HSIC CHARACTERIZATION AUDIO CAMERA HIGH SPEED, NO TEST DWI FOR FRANK (SEG) EE CHARACTERIZATION TP WIFI I138 I139 I140 I141 I142 I143 I144 I145 I146 I147 I148 I149 I150 I151 I152 I153 I185 I186 I187 I188 I189 PLACE_NEAR=U0652.AR33:3MM P4MM SM PP9440 I190 PLACE_SIDE=BOTTOM SMP4MM PP9401 I192 I193 PLACE_NEAR=U0652.AR34:3MM P4MM SM PP9441 SMP4MM PP9413 SMP4MM PP9412 P4MM SM PP9403 PLACE_SIDE=BOTTOM P4MM SM PP9402 PLACE_SIDE=BOTTOM P4MM SM PP9405 SMP4MM PP9406 PLACE_NEAR=U0652.AT33:3MM P4MM SM PP9442 SMP4MM PP9416 P4MM SM PP9417 P4MM SM PP9419 P4MM SM PP9420 PLACE_NEAR=U0652.AT34:3MM SMP4MM PP9443 SMP4MM PP9421 P4MM SM PP9422 SMP4MM PP9423 P4MM SM PP9425 P4MM SM PP9424 SMP4MM PP9426 P4MM SM PLACE_NEAR=U0652:3MMPP9468 P4MM SM PLACE_NEAR=U5800:3MMPP9469 PP9471 PLACE_NEAR=U0652:3MM SMP4MM PLACE_NEAR=U0652.AU25:3MM SMP4MM PP9444 PP9472 PLACE_NEAR=U5800:3MM SMP4MM PP9428 PLACE_SIDE=BOTTOM SMP4MM PP9429P4MM SM P4MM SM PP9480 P4MM SM PP9481 P4MM SM PP9482 P4MM SM PP9483 SMP4MM PP9445 PLACE_NEAR=U0652.AV25:3MM PLACE_NEAR=U0652.AU27:3MM SMP4MM PP9446 PLACE_NEAR=U0652.AV27:3MM SMP4MM PP9447 PLACE_NEAR=U0652.B27:3MMPP9465SMP4MM PP9466 PLACE_NEAR=U3400.C7:3MM P4MM SM PP9410 P4MM SM SMP4MM PP9411 PLACE_NEAR=U0652.AM33:3MMPP9460P4MM SM SMP4MM PLACE_NEAR=U5800.13:3MMPP9462 I76 P4MM SM PP9463 PLACE_NEAR=U5800.14:3MM PLACE_NEAR=U0652.V31:1MMPP9450SMP4MM PLACE_NEAR=U0652.AN30:1MMPP9451SMP4MM SYNC_MASTER=J72_MLB_C SYNC_DATE=11/26/2012 TEST: EE TP/PP PLACE_SIDE=BOTTOM PLACE_NEAR=U0652:2MMSPI2_CODEC_MISO PLACE_NEAR=U0652.D34:2MMFMI0_DQS TP_U1400_RB0 MIPI1C_CAM_FRONT_DATA_P<0> MIPI1C_CAM_FRONT_CLK_N UART4_OSCAR2SOC_RXD PLACE_NEAR=U0652:2MM PLACE_SIDE=BOTTOM SPI2_CODEC_MOSI PLACE_NEAR=U1900:2MM HSIC2_BB_DATA HSIC2_BB_STB USB_BB_N FUNC_TEST=TRUE USB_BB_P FUNC_TEST=TRUE UART2_WLAN2SOC_TX UART2_SOC2WLAN_TX UART1_SOC2BT_TX UART1_BT2SOC_TX HSIC1_WLAN_DATA HSIC1_WLAN_STB HSIC1_WLAN_DATA FMI0_AD<3> SPI2_CODEC_SCLK PLACE_NEAR=U1900:2MM I2S1_SPKAMP_DOUT PLACE_NEAR=U2040:2MM PLACE_SIDE=BOTTOM PLACE_NEAR=U0652:2MMI2S1_SPKAMP_DIN I2S1_SPKAMP_LRCK PLACE_NEAR=U2040:2MM I2S1_SPKAMP_MCK PLACE_NEAR=U2040:2MM I2S1_SPKAMP_BCLK PLACE_NEAR=U2040:2MM PLACE_NEAR=U1900:2MMI2S0_CODEC_ASP_MCK MIPI0C_CAM_REAR_DATA_N<0> MIPI0C_CAM_REAR_DATA_P<0> MIPI0C_CAM_REAR_CLK_N MIPI0C_CAM_REAR_CLK_P MIPI1C_CAM_FRONT_DATA_N<0> MIPI1C_CAM_FRONT_CLK_P NO_TEST=TRUEEDP_DATA_EMI_CONN_P<0..3> NO_TEST=TRUEEDP_DATA_EMI_CONN_N<0..3> NO_TEST=TRUEEDP_DATA_EMI_N<0..3> NO_TEST=TRUEEDP_DATA_EMI_P<0..3> NO_TEST=TRUEEDP_DATA_P<0..3> NO_TEST=TRUEEDP_DATA_N<0..3> MIPI1C_CAM_FRONT_DATA_FILT_N<0> NO_TEST=TRUE MIPI1C_CAM_FRONT_DATA_FILT_P<0> NO_TEST=TRUE NO_TEST=TRUEMIPI1C_CAM_FRONT_CLK_FILT_N NO_TEST=TRUEMIPI1C_CAM_FRONT_DATA_P<0> NO_TEST=TRUEMIPI1C_CAM_FRONT_CLK_N NO_TEST=TRUEMIPI1C_CAM_FRONT_DATA_N<0> NO_TEST=TRUEMIPI1C_CAM_FRONT_CLK_FILT_P NO_TEST=TRUEMIPI1C_CAM_FRONT_CLK_P NO_TEST=TRUEMIPI0C_CAM_REAR_DATA_FILT_N<0..3> NO_TEST=TRUEMIPI0C_CAM_REAR_DATA_FILT_P<0..3> MIPI0C_CAM_REAR_CLK_FILT_N NO_TEST=TRUE NO_TEST=TRUEMIPI0C_CAM_REAR_CLK_FILT_P NO_TEST=TRUEMIPI0C_CAM_REAR_CLK_P NO_TEST=TRUEMIPI0C_CAM_REAR_CLK_N NO_TEST=TRUEMIPI0C_CAM_REAR_DATA_P<0..3> NO_TEST=TRUEMIPI0C_CAM_REAR_DATA_N<0..3> PLACE_NEAR=U1900:2MMI2S2_CODEC_XSP_DOUT FMI0_DQS DWI_AP_DO PLACE_NEAR=U8100:2MM PPVDD_SOC_SOC_SENSE PPVDD_CPU_SOC_SENSE UART4_SOC2OSCAR_TXD PLACE_NEAR=U2400:2MM PLACE_NEAR=U1900:2MMI2S2_CODEC_XSP_LRCK TP_TCKC_U1400 TP_TMSC_U1400 TP_U1400_RB1 FUNC_TEST=TRUEGPIO_BT_WAKE HSIC1_WLAN2SOC_DEVICE_RDY HSIC1_WLAN2SOC_REMOTE_WAKE PMU_GPIO_WLAN_HOST_WAKE HSIC1_SOC2WLAN_HOST_RDY 051-0886 A.0.0 94 OF 121 53 OF 54 PLACE_NEAR=U0652.C34:2MM PLACE_NEAR=U0652.D34:2MM 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 15 6 12 53 12 7 20 53 7 20 53 5 19 5 15 4 24 27 4 24 27 11 24 52 11 24 52 5 44 5 44 5 44 5 44 4 44 53 4 44 4 44 53 6 12 5 15 5 16 5 16 5 16 5 16 5 16 5 15 7 23 53 7 23 53 7 23 53 7 23 53 7 20 53 7 20 53 18 18 18 18 7 18 7 18 20 20 20 7 20 53 7 20 53 7 20 53 20 7 20 53 23 23 23 23 7 23 53 7 23 53 7 23 53 7 23 53 5 15 6 12 5 48 9 9 5 19 5 15 12 12 12 5 44 5 44 5 44 44 48 5 44 53
- 55. Apple Inc. THE INFORMATIONCONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. 124578 B D 8 7 6 5 4 3 C B A NOTICE OF PROPRIETARY PROPERTY: PAGE 12 D A C PAGE TITLE SHEET IV ALL RIGHTS RESERVED R D SIZEDRAWING NUMBER REVISION BRANCH 6 3 THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT BUCK3_SW LDO3 BUCK3 BUCK5 LDO2 HALL EFFECT NEEDS TO BE ON IN HIBERNATE LDO5 PP1V2_S2R_SW2 SHOULD BE ON IN HIBERNATE VLCM1 BUCK6 BACKUP RAIL. CAN BE BOOSTED TO MEET LDO11 LDO1 LDO6 LDO8 LDO7 LDO7 SHOULD BE ON IN HIBERNATE ON_BUF BATTERY USB POWER INPUT POWER CONNECTIONS PROVIDE 1.2V TO OSCAR LDO13 LDO10 1.1V MIN ON CAMERA IF NEEDED. BUCK4_SW BACKLIGHT BOOST BUCK2 PP1V8_S2R_SW3 SHOULD BE ON IN HIBERNATE CURRENTLY POWERS OSCAR AND 1.8V RAIL ON SENSOR CHARGER MAIN BUCK4 BUCK1 BUCK0 LDO9 COMPASS, ACCEL, GYRO, PROX ARE ON OSCAR LDO3 SHOULD BE ON IN HIBERNATE LDO4 SHOULD IO ALS POWER HERE? SYNC_MASTER=J72_MLB_C SYNC_DATE=11/26/2012 POWER: ALIASES MAKE_BASE=TRUE PP1V8_EXT_SW =PP1V8_BEACON =PP1V8_EEPROM =PP1V8_VDDIO18_SOC =PP1V8_MIPI_SOC =PP1V8_SOC =PP1V8_EDP_SOC =PP1V8_SPKRAMP =PP1V8_NAND_SOC =PP1V8_NAND =PP1V8_PLL_SOC =PPVDD_GPU MAKE_BASE=TRUE PP1V8_S2R PP1V8_SW1 MAKE_BASE=TRUE =PP3V0_UVLO =PPBATT_AUDIO MAKE_BASE=TRUE PPBATT_VCC =PPVCC_MAIN_LED MAKE_BASE=TRUE PP1V2_S2R_SW2 =PP1V3_CAM_FRONT PP3V0_SPARE1 MAKE_BASE=TRUE =PP1V8_S2R_EXT_SWITCH =PP1V8_S2R_REAR_CAMERA MAKE_BASE=TRUE PPVDD_GPU MAKE_BASE=TRUE PPVDD_SRAM PPVDD_CPU MAKE_BASE=TRUE =PP3V0_S2R_TRISTAR=PPVDD_SRAM_CPU =PPVDD_SRAM_SOC PP3V3_SW MAKE_BASE=TRUE MAKE_BASE=TRUE PP3V3_S2R =PPVCC_MAIN_LCD =PP3V0_HP_ALS =PP3V0_SPARE1 =PP3V3_ACC =PPVDD_CPU =PPVCC_MAIN_GRAPE =PPVCC_MAIN_CPU =PPVCC_MAIN_SOC =PP1V2_VDDQ_DDR =PP1V2_HSIC_SOC =PP1V2_S2R_OSCAR =PP1V2_VDDIOD_SOC =PP1V0_MIPI_SOC =PP1V0_USB_SOC =PP5V25_GRAPE MAKE_BASE=TRUE PP5V25_GRAPE PP1V7_VA_VCP MAKE_BASE=TRUE =PP3V0_ALS MAKE_BASE=TRUE PP3V3_ACC =PP3V3_EDP_PU =PP3V3_USB_SOC =PP3V0_PROX MAKE_BASE=TRUE PP3V0_S2R_TRISTAR =PP3V0_IO_ALS PP2V6_CAM_AF MAKE_BASE=TRUE PP2V9_CAM MAKE_BASE=TRUE =PP2V6_CAM_REAR_AF =PP2V9_CAM_REAR =PP2V9_CAM_FRONT =PPVBUS_USB_EMI =PP1V8_ALWAYS MAKE_BASE=TRUE PP1V8_ALWAYS =PPLED_REG_A MAKE_BASE=TRUE PPLED_OUT_A =PPVCC_MAIN_NAVAJO =PPVCC_MAIN_VDD_LCM =PP1V7_VA_VCP =NC_LDO8 =PP3V0_S2R_GYRO =PP3V0_S2R_COMP =PP3V0_S2R_ACCEL MAKE_BASE=TRUE PPVBUS_USB_DCIN =PP3V3_NAND =PPBATT_VCC_BB MAKE_BASE=TRUE PP3V0_S2R_SENSOR =PP3V3_S2R_WIFI_PA =PP3V3_S2R_SWITCH =PPBATT_POS_CONN PP1V2_SW1 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUENC_LDO8 MAKE_BASE=TRUE PP1V0_SOC =PP1V0_EDP_PAD_DVDD_SOC =PP1V3_CAM_REAR MAKE_BASE=TRUE PPVDD_SOC =PP1V8_S2R_TRISTAR =PP1V8_S2R_VDDIO_WLAN_BT =PP1V8_S2R_MISC =PP1V8_S2R_MESA =PP1V8_S2R_VDD_CORE_GPS =PP1V8_S2R_VDD_IO_GPS =PP1V8_AUDIO =PP1V8_GRAPEPP1V8_SW2 MAKE_BASE=TRUE =PP1V8_S2R_GYRO =PP1V8_S2R_ACCEL =PP1V8_S2R_OSCAR =PP1V8_S2R_COMP =PP1V2_S2R_DDR =PP1V2_S2R_DDR_SOC =PP1V2_S2R_CAM_REAR =PPVCC_MAIN_WLAN =PPVCC_MAIN_GPS MAKE_BASE=TRUE PPVCC_MAIN MAKE_BASE=TRUE PP3V0_ALS =PPVCC_MAIN_GPU =PPVCC_MAIN_DEV =PPVCC_MAIN_DOCK =PPVCC_MAIN_AUDIO =PPVDD_SOC =PP1V8_S2R_GRAPE =PP1V8_S2R_DDR PP1V3_CAM MAKE_BASE=TRUE =PP1V8_DMIC =PP1V8_PROX =PP1V8_CAM_REAR =PP1V8_CAM_FRONT =PP3V0_S2R_HALL MAKE_BASE=TRUE PP3V0_UVLO PP1V2_S2R MAKE_BASE=TRUE MAKE_BASE=TRUE PP1V8_S2R_SW3_COMP PP1V8_S2R_SW3_COMP MAKE_BASE=TRUE PP1V8_S2R_SW3 051-0886 A.0.0 121 OF 121 54 OF 54 5052 51 8 9 7 4 5 7 10 18 7 6 12 48 4 9 464752 465052 49 4652 47 4652 4752 50 4652 4652 4652 11 9 4852 4652 18 49 11 9 13 46 46 8 4 19 8 7 4 1347 164752 20 4752 4 22 4752 4752 4752 23 23 20 43 54752 184752 47 15 16 21 21 21 4652 12 24 25 33 34 35 36 37 38 4752 44 48 45 4652 47 4752 7 23 4652 11 44 5 51 15 134652 21 21 19 21 8 8 44 4647484952 4752 46 43 15 16 9 13 8 4752 14 22 23 20 13 4752 464752 5254 52 54 46