9. Gate Length Biasing
• Freedom to assign different biased gate-lengths to
different devices.
We consider three options:
• Technology level: All devices in the library have the same
biased gate-length.
• Cell level: All devices in a cell have the same biased gate-
length. Devices in different cells may have different biased
gate-lengths.
• Device level: All devices are free to have an independent
biased gate-length.
10. Gate Length Biasing
• Application of this technique results in reduced leakage and
leakage variability while having very small impact on circuit
performance.
• Approach does not require additional process steps and can be
applied anytime during the design cycle.
• Gate-length biasing reduces leakage and its variability,
however, with a delay penalty.
Constrained to less than 10% to preserve pin- and layout-
compatibility.
Approach applicable as a post-layout/post-RET step
11. Gate Length Biasing
• Allow devices in a cell to have different biasing, and have
cell variants with different sets of timing arcs slowed down
• Rise & fall transitions not both critical bias devices
that govern the non-critical transition
• Timing arcs of a cell not all critical bias devices to
make non-critical arcs slow and reduce leakage
• Initial results:
• Additional 2%-5% leakage reduction
• Significant leakage variability reduction
Disadvantages:
• Increased cell library and GDSII size
• Evaluate at future technology nodes
12. • Leakage power contributes significantly to
total power
• All High- Vth implementation too slow
• All Low-Vthimplementation too leaky
• Dual- Vthprocesses popular
