NAND Flash Controller F/W Implementation

1. FTL Write
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2. 4 Threads for Write
• Each thread runs according to its state on the resources it manages.
User
Head Block
(SLC or MLC)
User
SLC
Free Block List
User
MLC (or TLC)
Free Block List
Meta
Head Block
(SLC)
Meta
SLC
Free Block List
Meta Cache
(RAM)
④ User Write
② Meta Write
① Reclaim Meta Block
③ Reclaim User Block

3. Synchronized (Asynchronized) Write
• When the User Head Block is changed, the Cached User Block List must be written in
Meta Page.
t
User Block X
Meta Cache (RAM)
User Block Y
Meta Block N
User Write
Meta Write