More Related Content
More from Bizan Nishimura
More from Bizan Nishimura (20)
FM音源シールド for GR-SAKURA
- 11. メモリバス
桜ライブラリにないので自力でレジスタ設定
// read YM2203 status
#define YM2203_STATUS
(*(volatile unsigned char*)0x05000000) // CS3,A16=0
// read YM2203 register address
#define YM2203_REG_ADDR (*(volatile unsigned char*)0x05000000) // CS3,A16=0
// read/write YM2203 register value
#define YM2203_REG_DATA (*(volatile unsigned char*)0x05010000) // CS3,A16=1
SYSTEM.SYSCR0.WORD = 0x5a03;
SYSTEM.SCKCR.BIT.BCK = 4;
// enable external bus
// BCLK 1/4 prescale
MPC.PWPR.BIT.B0WI = 0;
MPC.PWPR.BIT.PFSWE = 1;
// disable access protection
//
MPC.PFCSE.BIT.CS3E = 1;
MPC.PFCSS0.BIT.CS3S = 2;
MPC.PFAOE1.BIT.A16E = 1;
MPC.PFBCR0.BYTE = 0;
//
//
//
//
enable CS3
set PC4 function as CS3
enable A16
8bit data bus, PCX as address bus
BSC.CS3CR.WORD = 0x0001 | (2 << 4);
// 8bit data bus.
- 12. マスタークロック(4MHz)
// set PC7 as MTIOC3A
MPC.PWPR.BIT.B0WI = 0;// disable access protection
MPC.PWPR.BIT.PFSWE = 1; //
MPC.PC7PFS.BIT.PSEL = 0x01; // set PC7 as MTIOC3A
MPC.PWPR.BIT.PFSWE = 0; // enable access protection again
MPC.PWPR.BIT.B0WI = 1;//
PORTC.PMR.BIT.B7 = 1;// use PC7 as peripheral
SYSTEM.PRCR.WORD = 0xA502;// disable access
MSTP(MTU) = 0;// enable MTU (MTU0-MTU5)
// stop and clear MTU3's TCNT
MTU.TSTR.BIT.CST3 = 0;
MTU3.TCNT = 0x0000;
MTU3で
protection
4MHz, Duty 50%
のパルスを発生
MTU3.TCR.BIT.TPSC = 0;// counter clock: PCLK/1 = 48MHz
MTU3.TCR.BIT.CKEG = 0;// count on rising edge
MTU3.TCR.BIT.CCLR = 1;// clear TCNT on TGRA compare match
// PWM mode 1
MTU3.TMDR.BYTE = 0x02;
// set output level
MTU3.TIORH.BIT.IOA = 1; // initially output 0, output 0 on cycle compare match
MTU3.TIORH.BIT.IOB = 2; // output 1 on duty compare match
// set cycle and duty
MTU3.TGRA = 11; // cycle = 1/4MHz = 250ns(48MHz/12 =4MHz)
MTU3.TGRB = 5;// duty = cycle/2 = 125ns
// start MTU3's TCNT
MTU.TSTR.BIT.CST3 = 1;
- 13. タイマ割り込み
TMR0+TMR1でタイマ割り込みを発生
// TMR0(8bit) + TMR1(8bit) cascaded 16bit timer mode
// TMR0: upper 8 bits / TMR1: lower 8 bits
SYSTEM.PRCR.WORD = 0xA50B; // enable writing to protected registers
MSTP(TMR01) = 0;
// turn on TMR0,1
TMR0.TCCR.BIT.CSS = 0x03;
// TMR0 clocked by TMR1 overflow
TMR1.TCCR.BIT.CSS = 0x01;
// TMR1 clocked by PCLKB / prescaler
TMR1.TCCR.BIT.CKS = 0x04;
// 1/64 prescaler for TMR1
// default BPM = 80 (80 quarter notes in 1 minute)
// interrupt interval = 1/8 * 32th note interval
//
= 60sec / (BPM*8*8)
// compare match = 60 * 1,000,000us / (BPM*4*8) * (48MHz / 64)
TMR01.TCORA = (uint16_t)((60000000UL * 48) / (80*8*8*64));
TMR0.TCR.BIT.CCLR = 0x01;// set counter clear by compare match A
TMR0.TCR.BIT.CMIEA = 0x01;// enable compare match A interrupt
TMR01.TCNT = 0x0000;// clear the counter
IPR(TMR0, CMIA0) = 1;// set interrupt priority level
IEN(TMR0, CMIA0) = 1;// enable compare match A interrupt
- 14. 多重割り込み
extern "C" void Excep_TMR0_CMIA0(void) __INTTERUPT_FUNC;
extern "C" void Excep_TMR0_CMIA0(void)
{
int i;
static int tgl=0;
// enable multiple interrupt
// setpsw_i();
// for Renesas CCRX
__builtin_rx_setpsw('I');// for GCC
i = 100;
// interval procedure for playing music
MMLplayer.onTimer();
// clear interrupt
IR(TMR0, CMIA0) = 0;
}
- 17. 昔なつかしのMML
楽譜を文字列で表現
char *note1,*note2,*note3;
note1 = (char*)"L8Q7O4V14"
"DBAGD4RDDBAGE4REE>C<BAF+4R>DDDC<AB4RD"
"DBAGD4RDDBADE4REE>C<BA>DDDDEDC<AGR>D4";
note2 = (char*)"L8Q4O5V13"
"RRRRRD16C+16D16C+16DRRRRRE16D+16E16D+16E"
"RRRRRF+16F16F+16F16F+RRRRRD16D+16E16D+16D"
"RRRRRD16C+16D16C+16DRRRRRE16D+16E16D+16E"
"RRRRRF+16F16F+16F16F+RRRRRRD4";
note3 = (char*)"L8Q8O4V14"
"G4D4G4D4G4AB>C4<G4>C4<G4A4D4A4D4GDEF+"
"G4D4G4D4G4AB>C4<G4>C4<G4A4D4ADEF+G4D4";
MMLplayer.setNote(FM_CH1, note1);
MMLplayer.setNote(FM_CH2, note2);
MMLplayer.setNote(FM_CH3, note3);
