Final_report_rahulekhande

MMIC 2016 Final Term Project
Report on
Design of Distributed Amplifier
(Travelling Wave Amplifier)
By
Rahul Ekhande
U37692717
May 7, 2016

Table of Contents:
1. Abstract
2. Introduction
3. Design Procedure
4. LVS Rule Check
5. DRC Rule
6. Conclusion
7. Learning from the Project

Abstract:
We designed the Broadband Distributed Amplifier using TQPED (GaAs) block in ADS. The goal
parameters are to design Travelling Wave Amplifier with bandwidth 2 – 20 GHz, VSWR (IN/OUT) to be
less than 2 and noise figure to be less than 4 with flat gain of 10 dB along whole bandwidth. The critical
parameter is to have Pin (dB) to be more than 15 dB. Various design stages with different transistor
dimension and biasing point have been studied and optimized to get the given specification.

List of Figures:
Figure 1: Intrinsic Parameter Calculation in ADS..........................................................................................7
Figure 2: Ideal 3 Stage TWA..........................................................................................................................7
Figure 3: 3-Stage TWA: Stage 2.....................................................................................................................8
Figure 4: 3-Stage TWA: Final Stage...............................................................................................................8
Figure 5:Results for 3- Stage TWA ................................................................................................................9
Figure 6: Gain Compression for 3-Stage TWA...............................................................................................9
Figure 7: Ideal Schematic for 4- Stage TWA................................................................................................10
Figure 8: TQPED Schematic for 4 stage TWA..............................................................................................11
Figure 9: Results for 4 stage TWA...............................................................................................................11
Figure 10:Power Compression for 4 Stage TWA.........................................................................................12
Figure 11: Biasing point selection for 6- stage TWA...................................................................................13
Figure 12:Ideal Schematic for 6- Stage TWA...............................................................................................13
Figure 13:Results for Ideal 6- Stage TWA....................................................................................................14
Figure 14:Gain Compression for 6-Stage TWA............................................................................................15
Figure 15: Meander modelling of Drain Inductor.......................................................................................16
Figure 16:Drain Inductance Meander Modelling plots...............................................................................16
Figure 17:Gate Inductor to EM Model Flow ...............................................................................................17
Figure 18: Final Schematic 6- Stage TWA....................................................................................................17
Figure 19: Final Schematic: Top Side ..........................................................................................................18
Figure 20:Final Schematic:Top Left.............................................................................................................18
Figure 21:Final Schematic -Top Left............................................................................................................18
Figure 22:Final Schematic: Center ..............................................................................................................19
Figure 23:Final Schematic-Bottom Gate Inductance ..................................................................................19
Figure 24:Final Schematic-Bottom Right ....................................................................................................19
Figure 25:Final Schematic -Bottom Right.................................................................................................20
Figure 26: Final Layout................................................................................................................................20
Figure 27:3D view of Layout .......................................................................................................................21
Figure 28:Final Simulation Results..............................................................................................................21
Figure 29:Final gain Compression (Pin dB) .................................................................................................22

List of Tables:
Table 1: Design Specifications.......................................................................................................................6
Table 2: Design Achieved in Stage 1 Design................................................................................................10
Table 3:Design Achieved in Stage 2 Design ................................................................................................12
Table 4:Design Achieved in Stage 3: Ideal Design.......................................................................................15
Table 5: Transistor Size variation from Ideal to Final Schematic................................................................22
Table 6: 50-ohm Load resistor combination for Optimum Pin...................................................................23

Introduction:
The design of Distributed amplifier (DA)is done in this report. Distributed Amplifier consists of pair of
transmission lines with impedances of Z0 which are connected to the active device (amplifier) on each stage.
The input RF signal is introduced in through the source of the transistor, the active device responds to the
input RF signal and amplify the signal at each stage in respond to the input coming wave. Thus this the
signal is amplified at each stage and we can get the signal of high gain over high bandwidth.
Here the goal to design an DA is given below:
Target Specifications
Bandwidth 2-20 GHz
Gain >10 dB
Gain Flatness < (+/-1)
VSWR(in/out) < 2:1
K factor >1
Noise figure(max) 4 dB
Gain compression +15 dB
Table 1: Design Specifications
The aim is to design of DA with above specification using Keysight Advanced Design System(ADS) with
Triquint TQPED (GaAs) blocks. Below report show the details flow of work done. Different stages and
transistor dimensions are used to achieve the above specifications.

Design Procedure:
Stage 1: 3- Stage TWA
The design of Distributed Amplifier was started with the 3 stages following specifications:
Transistor Parameter Biasing Point
Width Number VGS(Volts) VDS(Volts)
30 3 3 1
The intrinsic parameters we calculated using ADS, its formula and the Ideal 3 stage TWA amplifier
Schematic was created, which is shown below: (ideal_3stage.dsn)
Figure 1: Intrinsic Parameter Calculation in ADS
Figure 2: Ideal 3 Stage TWA

Calculated Lg Cgs and Cds using the biasing point was used to create the Ideal 3 stage TWA shown above in
Figure. 2. The Ideal Circuit was then converted into TQPED transmission line with VIA model in the
following two stages:
Figure 3: 3-Stage TWA: Stage 2
Figure 4: 3-Stage TWA: Final Stage
Initially, the Gate inductance was converted into EM model in the 2nd
stage, but in Final stage the
transmission line model was used. The cut-off frequency used to calculate the parameters was 20 GHz.
(tqped_model_3stage_TWA.dsn)
The Ground via was connected in order to check he effect of adding inductance due to it. The results for
the Final 3-Stage TWA are shown below:

Figure 5:Results for 3- Stage TWA
AS we can see the above design was stable, had VSWR in and out less than 2 with stable gain and flat with
±0.5 dB variation in given bandwidth. But the Noise figure nf(2) was not below in given bandwidth. More
importantly the Gain compression. The gain compression for the above design was 6 dB less than the
required.
The current consumption for each stage was 27 mA with Vds=3.5 volts. Therefore, the power consumption
for the design was 283.5 mW
Figure 6: Gain Compression for 3-Stage TWA

The designed TWA fulfilled the following:
Target Specifications Simulation results
Bandwidth 2-20 GHz 2-20 GHz
Gain >10 dB >10 dB
Gain Flatness < (+/-1) < (+/-1)
VSWR(in/out) < 2:1 < 2:1
K factor >1 >1
Noise figure(max) 4 dB No
Gain compression +15 dB 9.371
Table 2: Design Achieved in Stage 1 Design
Stage 2: 4- Stage TWA
In this the number of stages was increased from 3 to 4 with the following biasing points:
Transistor Parameter Biasing Point
50 6 3 0.75
Since most of the specification were achieved in the above design, now the Gain Compression and Noise
figure was the aim. Increasing the dimensions can increase the current drawing capacity of transistor which
increases the power compression of the transistor which increases the gain compression. So the figures
numbers and width was increased along with one stage. Below are the figures for designed schematic and
results for 4 stage TWA. (cell_4.dsn)
Figure 7: Ideal Schematic for 4- Stage TWA

tl_042516.dsn
Figure 8: TQPED Schematic for 4 stage TWA
Figure 9: Results for 4 stage TWA

Figure 10:Power Compression for 4 Stage TWA
The designed TWA fulfilled the following:
Gain >10 dB >10 dB
Gain Flatness < (+/-1) < (+/-1)
VSWR(in/out) < 2:1 > 2:1
K factor >1 >1
Noise figure(max) 4 dB No
Table 3:Design Achieved in Stage 2 Design
The increase in stage and the dimension of the transistor increased the power consumption:
Stages Idss Vdc Power
4 44 mA 3 528 mW
The gain compression was increased by 4 dB, but the design degraded the VSWR making no improvement
in the Noise figure. The next aim was to increase the gain compression and to improve VSWR and noise
figure. The increase in figure dimension had not only degraded the VSWR, but also varied the gain stability
in given bandwidth. In order to achieve all specifications, the following idea was implemented.

Stage 3: 6- Stage TWA with less transistor dimension
Initially, the biasing points are selected for the transistor W=30 and finger number N=3
(biasing_network.dsn)
Figure 11: Biasing point selection for 6- stage TWA
Transistor Parameter
Biasing
Point
Biasing
Network 30 3 3.5 0.88
Intrinsic parameter calculation was done (figure.1). The ideal schematic is shown as below
Figure 12:Ideal Schematic for 6- Stage TWA

In previous stages, the ground termination of source of the transistor was not done by the via, because of
which the additional inductance which adds up was not considered in Ideal stages. This causes the
degradation in the performance of the design. To avoid that the ground vias are added in the Ideal model
itself. The drain capacitance (Cadd)are also neglected in the Ideal schematic as they are removed in later
stages. (6_stage_ideal.dsn)
A transmission line is connected between the drain and the drain inductances in order to consider the
later addition inductance which will add. The results for the design is shown below:
Figure 13:Results for Ideal 6- Stage TWA

Figure 14:Gain Compression for 6-Stage TWA
As we can see all the required specification we fulfilled, so above biasing point and transistor dimensions
were used for final design. Below table shows the specification table required and fulfilled by above Ideal
design:
Gain >10 dB >10 dB
Gain Flatness < (+/-1) < (+/-1)
VSWR(in/out) < 2:1 < 2:1
K factor >1 >1
Noise figure(max) 4 dB 4 dB
Table 4:Design Achieved in Stage 3: Ideal Design
Gate Inductor EM Modelling:
Meander Model:
As we go from Ideal to TQPED schematic, the gate and drain inductor we replace it by TQPED transmission
lines. As the TL inductor model needs more length, we bend them into Meander lines. This decreases the
size of the design model.

The inductor is tuned and optimized with its transmission line model(Meander Model) shown below:
Figure 15: Meander modelling of Drain Inductor
The design is optimized and tuned in order to behave like inductor. As we know Tl inductor model have
less width and high length, so care must be taken during modelling for dimension of Meander model. The
S11 and S21 response of the inductor and model are compared and optimized to become same as shown
below. (innductor_tuning.dsn)
Figure 16:Drain Inductance Meander Modelling plots
Similarly, the half gate inductance is modeled and they are connected to form a Hai pin like model. The
model is then used to create the layout. While optimizing care is taken that the width of all the connections
(TL and M-corns) are same, in order to have proportionate design of the inductance model.

The layout is then used to create the EM model of the layout which can be used in Schematic for further
design. The flow of inductance to it EM model is shown below:
Figure 17:Gate Inductor to EM Model Flow
Final Schematic: (6_stage_ideal_WITHVIA_final.dsn)
Figure 18: Final Schematic 6- Stage TWA

Top side:
Figure 19: Final Schematic: Top Side
Top Left:
Figure 20:Final Schematic:Top Left
Top Right:
Figure 21:Final Schematic -Top Left
Center:

Figure 22:Final Schematic: Center
Bottom Gate Inductance:
Figure 23:Final Schematic-Bottom Gate Inductance
Bottom Right:
Figure 24:Final Schematic-Bottom Right

Bottom Left:
Figure 25:Final Schematic -Bottom Right
Layout:
Figure 26: Final Layout

3-D view of Layout:
Figure 27:3D view of Layout
Final Simulation Results:
Figure 28:Final Simulation Results

Final Power Compression:
Figure 29:Final gain Compression (Pin dB)
Transition of Transistor Dimension from Biasing to Final Schematic:
Transistor Parameter
Biasing
Point
Sr No. Width Number VGS(Volts) VDS(Volts) Power
1
Biasing
Network 30 3 3.5 0.88
294
mW
2 Ideal Schematic 30 3 3.5 0.88
294
mW
3 Final Schematic 17 3 3.5 0.88
294
mW
Table 5: Transistor Size variation from Ideal to Final Schematic

Finally, in order to meet the gain compression, the 50Ω resistor were also optimized and from the
following the best combination was selected:
Resistor Gain(dB)
Sr.No I/P O/P
Power
Compression 2 GHz
20
GHz
1 50 35 14.136 10.33 9.65
2 50 30 14.3 9.456 9.72
3 45 35 14.14 10.065 9.65
4 45 30 14.323 9.19 9.729
5 40 40 14.261 10.797 9.609 Transistor
6 40 35 14.388 9.743 9.68 width number
7 40 30 14.474 8.87 9.738 15 3
8 35 40 14.124 10.078 9.651
9 35 35 14.214 9.351 9.696
40 30 14.474 8.87 9.738 17 3 Final
Table 6: 50-ohm Load resistor combination for Optimum Pin
The below is the table showing comparison between the specification required and specification meet:
Target Specifications Final Results
Gain >10 dB >10 dB
Gain Flatness < (+/-1) < (+/-1)
VSWR(in/out) < 2:1 < 2:1
K factor >1 >1
Noise figure(max) 4 dB 4 Db (5 to 20 GHz)
Table 7:Goals Achieved
The Nosie figure goal I could not achieve, as I was trying to improve my noise figure my Pin (dB) was
getting low. So compromised my NF for Gain and P(in).

LVS Rule Check Report:
LVS Report
Advanced Design System 2016.01
Copyright 2004 - 2015 Keysight Technologies 1989-2016
May 7 2016
Design
Schematic:
MMIC_project_lib:6_stage_ideal_WITHVIA_final:schematic
Layout:
MMIC_project_lib:6_stage_ideal_WITHVIA_final:layout
LVS Analysis
LVS Analysis: Components with Pin Nets
Hierarchy Check: All levels - dissimilar hierarchy
Elapsed time 9.934 (seconds)
Component Mapping
Component mapping Component name and pin
connections only
Settings
Check Parameters Mismatch: On
Use instance name mapping: Off
Use parameter value mapping: Off
Summary:
Components Not in Schematic: 0
Components Not in Layout: 0
Nodal Mismatches: 0
Nodal Mismatches: 0
Parameter Mismatches: 0
Component Count Schematic: 214
Component Count Layout: 214
Wires/Flight-lines in layout: 0
Physical/Nodal mismatches: 0
Errors 0
Components not in schematic 0
Components not in layout 0
Nodal Mismatches 0
Parameter Mismatches 0
Warnings 0
Wires/Flight-lines in layout 0

DRC Check Report:
TOTAL DRC VIOLATIONS = 283
TOTAL OFF-GRID WARNINGS = 5436
====================================================================================
======
#_OF GDS_DRC
ERRS FLAG_ID LDR DESCRIPTION
====================================================================================
======
4 101 5.2.2A.1 NiCr Resistor Width must be 2.0 <= width <= 250.0
4 102 5.2.2A.2 NiCr Resistor Width or Length < 2.0
63 103 5.4.1 Via1 contact area larger than 10% of MIM plate area
18 104 6.2K.3 Metal0 to Ohmic Exclusion < 1.0 (intra Device)
1 105 6.2S MIM to NiCr Exclusion < 4.0
22 106 7.2_stack_via1 stacked via1 area < 20.0 square um
6 107 7.3C.2 Via1 can not straddle MIM
42 108 7.3E.1 Inclusion of Via2 within Metal1 (per edge) must be >= 0.5
67 109 7.3F Inclusion of Via2 within Metal2 (per edge) must be >= 1.0 (Tolerance <= 0.049)
48 110 5.6J.NOTE.1 Metal outside Cell Boundary (layer 63)
8 111 5.6J.NOTE.2 ERROR, Cell Boundary (layer 63) missing, NO Substrate Via or BPIL to Cell Edge
Check Performed
====================================================================================
======
= OFF_GRID WARNINGS LDR DESCRIPTION
LAYER AND COORDINATES OF OFFGRID POINTS
( DATA IS CURRENTLY NOT PROVIDED IN GDSII DRC OUTPUT )

====================================================================================
======
144 OFFGRID.2 WARNING, Offgrid (90 or 45 degree) w_recs Polygons
72 OFFGRID.3 WARNING, Offgrid (90 or 45 degree) iso_imp Polygons
4 OFFGRID.4 WARNING, Offgrid (90 or 45 degree) NiCr Polygons
200 OFFGRID.5 WARNING, Offgrid (90 or 45 degree) ohmic Polygons
144 OFFGRID.7 WARNING, Offgrid (90 or 45 degree) e_gate Polygons
12 OFFGRID.9 WARNING, Offgrid (90 or 45 degree) MIM Polygons
1124 OFFGRID.10 WARNING, Offgrid (90 or 45 degree) via1 Polygons
192 OFFGRID.12 WARNING, Offgrid (90 or 45 degree) via2 Polygons
60 OFFGRID.13 WARNING, Offgrid (90 or 45 degree) metal2 Polygons
56 OFFGRID.14 WARNING, Offgrid (90 or 45 degree) passivation_via Polygons
1192 OFFGRID.OTHER.11 WARNING, Offgrid metal1 Edges
1147 OFFGRID.OTHER.12 WARNING, Offgrid via2 Edges
1089 OFFGRID.OTHER.13 WARNING, Offgrid metal2 Edges
OFF GRID VERIFICATION
The following warnings are of horizontal / vertical / 45 degree geometries with vertexes
off-grid, or geometries specified to be placed on a .1u or .5u grid. Circles, arcs and
like geometries are excluded from off-grid verification.
Please follow instructions provided in the attached document 'grid_ADS_offgrid_how_to.pdf'
for off-grid verification. Currently TQHIP, TQRLC and TQTRX do not have Offgrid
checks define for the Qorvo kits.
====================================================================================
======

maildrc EXECUTED BY Rahul Ekhande ON 2016-05-07_19:53:19
assura PROCESSING TIME (in seconds) = 22 REPORTED CPU TIME (in seconds) = 2.23
PROCESSING TIME from receipt of eMail to transmission of eMail results (in seconds) = 25
GOLDEN DRC RULE FILE: ver2.24 for TQPED 2015_09_02 mailDRC rev: 1.108 16.03.08
VERIFICATION SERVER : tqolvsserver1 Assura (tm) Physical Verification Version
av4.1:Production:dfII5.1.41:5.10.41.500.6.144
-------------- eMail SPECIFIED DIRECTIVES --------------
drccellname = 6_stage_ideal_WITHVIA_final
processname = TQPED
switches =
streamfile = 6_stage_ideal_WITHVIA_final.gds
DATABASE UNITS: 1000
EDA SOFTWARE VERSION: ADS 2009
-----------------------------------------------------------------------------------------------------
| |
| >>> QORVO mailDRC UPDATE ANNOUNCEMENTS <<< |
| VERIFICATION QUEUE STATUS AND REFERENCE INFORMATION IS NOW AVAILABLE
FROM |
| http://triconnect.triquint.com/sites/CADEng/Apps/SitePages/LICENSE%20MONITOR.aspx |
| (located lower right corner of SharePoint page) |
| |
| If you have any issues with the your requests please contact eda@qorvo.com |
| |

| |
| NEW FEATURES: |
| |
-----------------------------------------------------------------------------------------------------
| The current DRC rule deck is a best effort to check current LDR specifications |
| |
| IF FALSE OR UNDISCOVERED DRC VIOLATION(S) EXIST AND THEY ARE NOT DOCUMENTED
WITHIN THE PDK KIT |
| THEN PLEASE REPORT THE PROBLEM(S) TO foundry@qorvo.com |
| |
| Qorvo "all around you" |
-----------------------------------------------------------------------------------------------------
Conclusion:
The Distributed Amplifier(TWA) was studied in detail. Different stages and transistor dimensions
(Width and Finger Number) were used to achieve the given goals. Biasing point plays vital role in
the design of broadband TWA along with the transistor dimensions. Number of stages stabilized
the gain over high frequency and increases the power consumption. Gain and noise cannot be
optimized together; trade-off have been made in this design. To get stable gain and high Pin (dB),
the Nosie (nf2) is compromised.
Learning form this Project:
 Design of TWA with different stages and different transistor dimensions with various
biasing points.
 Effect of replacing Ideal DC feed and DC block with real lumped elements.
 Generation on an EM model, Meander Model (Gate Inductance) an efficient method to
decrease the overall area consumption.
 Connection of different layers of TL with various vias.
 Effect of ground vias (additional inductance introduction) (Drain grounding).

Final_report_rahulekhande

Recommended

Recommended

More Related Content

Similar to Final_report_rahulekhande

Similar to Final_report_rahulekhande (20)

Final_report_rahulekhande