document final

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CHAPTER 1
PROFILE OF INDUSTRY
1.1 ELECTRICAL INDUSTRY:
The worldwide electric power industry provides a vital service essential to
modern life. It provides the nation with the most prevalent energy form known in
history—electricity. It advances the nation’s economic growth and productivity;
promotes business development and expansion; and provides solid employment
opportunities to workers globally in general and India in particular. It is a robust industry
that contributes to the progress and prosperity of our nation. Today the electric power
industry operates in a hybrid model of competition and regulation. The worldwide
electrical and electronics industry is growing at a fast pace which consist of
manufacturers, suppliers, dealers, retailers, electricians, electronic equipment
manufacturers.
History:
 The Beginnings 1878-1900
 1878 Edison Electric Light Co
 1879 Incandescent lamp
 1882 World’s first hydroelectric system at Appleton, WI
 1882 Pearl Street Station, NY (DC system)
 85 customers with 400 lamps
 Economic to distribute w/in 1 mile of station
 1888 Tesla’s AC system prevails
 Early city franchises were nonexclusive!

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 29 franchises in Chicago granted 1882-1905
 1891 National Brotherhood of Electrical. The World's electrical market size was
$1038.8 billion in 2006, since last year an increase of 10.6% is fore casted to grow
even more. The industrial electrical goods industry size was $651.3 billion,
contributing around 62.7% of the total. With regard to electronics parts and
components sector, the total market share was around $282.7 billion i.e. 27.2% while
home electronics was $ 104.7 billion. This figure is supposed to increase in this
decade.
1.2 FUTURE OUTLOOK OF ELECTRONICS AND ELECTRICAL:
Industry:
Today, the electrical and electronics industry is experiencing phenomenal and
remarkable changes worldwide. The worldwide electronics industry is distinguished by
fast technological advances and has grown rapidly than most other industries over the
past 30 years. Products are heading towards new destinations where cost is less than
other place with higher costs involved. These places offer the most long term potential
for market growth. Companies indulged in manufacturing electrical products are
investing a lot on research and development for the best products to meet the demand of
the market. They are manufacturing the product with best quality at reduced cost due to
many competitors.
Railways:
The Ministry of Railways under Government of India controls Indian Railways.
The Ministry is headed by Union Minister who is generally supported by a Minster of
State. The Railway Board consisting of six members and a chairman reports to this top
hierarchy. The railway zones are headed by their respective General Managers who in

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turn report to the Railway Board.
Indian Railways have their research and development wing in the form of
Research, Designs and Standard Organization (RDSO). RDSO functions as the technical
adviser and consultant to the Ministry, Zonal Railways and Production Units. Railway
Budget since 1924-25, railway finances have been separated from General Revenue.
Indian railways have their own funds in the form of Railway Budget presented to the
Parliament annually. This budget is presented to the Parliament by the Union Railway
Minster two days prior to the General Budget, usually around 26th February. It has to be
passed by a simple majority in the LokSabha before it gets final acceptance. Indian
Railways are subject to the same audit control as other government revenues and
expenditure.
Freight-traffic:
The revenue fright traffic has also grown immensely from 73.2 million tons in
1950- 51 to 557.39 million tones. Indian railways carry huge variety of goods such as
mineral ores, fertilizers, petrochemicals, agricultural produce and others. It has been
made possible with measures such as line capacity augmentation on certain critical
sectors and modernization of signaling system and increase in roller bearing equipped
wagons. Indian Railways make huge revenue and most of its profits are from the freight
sector and uses these profits to augment the loss-making passenger sector.
Indian Railways (IR) has been the prime mover of the nation and has the
distinction of being the largest railway system in Asia and the second largest railway
system in the World under single management. IR operates more than 11,000 trains per
day of which 7000 are passenger trains. The railways have played a critical role in
catalyzing the pace of economic development and continue to be an integral part of the

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growth engine of the country.
Infrastructure:
Railways have
 8000 engines
 40,000 coaches about 2.5 lakh of wagons
 7000 stations
 1 lakh km of track
 17 lakh employees worked under one organization and there is no strike since
last 30 years.

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CHAPTER 2
INTRODUCTION TO COMPANY
2.1 COMPANY PROFILE:
Efftronics Systems Pvt. Ltd. is a knowledge-driven company. Efftronics work
environment is a breeding ground for highly energetic and motivated individuals. It presents
you a stimulating, vibrant and a challenging arena where the word "EXCELLENCE" is
embodied in the performance-oriented work culture. The work environment is open, fair,
collaborative and conductive to continuous learning and enables professional as well as
personal growth. We will be working with one of the most talented, brilliant, hardworking
workforce in the industry .The company offers innovative products and solutions that help
customers to overcome their challenges.
Efftronics Systems Pvt. Ltd. was established as an SSI unit and extended
approximately in 50,000 sq. ft. The company is continuously broadening its perspective,
research and the area of analysis to a new format and platform. In this rapid changing work
environment, it has become imperative for everybody to be on their toes constantly to enable
them for adjusting to the ever changing technologies and work environment.
By pioneering new ways of collecting and managing information and knowledge, we
have strengthened and extended our R&D activities to diverse areas. Efftronics Systems Pvt.
Ltd. is an ISO 9001-2008 certified IT company now has grown into technology leader in
manufacturing Data Acquisition Systems, Data Dissemination Systems, Multilingual Graphics
and Engineering solutions, providing software and hardware solutions that enable companies
to develop better products faster and more cost-effectively. The company has vast expertise in

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comprehensive design, development, assembly and testing of microprocessor / micro
controller systems for diverse interfaces and applications.
2.1.1 Vision:
“To provide insight for enhancing wealth."
INSIGHT—refers to TRUTH. Our Vision is to develop Products and Solutions to the
Customers which provide truthful information that can optimize and improve their Business
Process. The Customers can take knowledgeable decisions towards ENHANCING WEALTH.
2.1.2 Mission:
"To provide freedom of creativity/innovation in exploiting the potential of
information technology.”
Efftronics provides Information Technology products and is experienced in conceiving,
Designing, Developing, Manufacturing and Implementing Microprocessor based Products
along with Application Software. Efftronics mainly focus on Domains and Products developed
for each and every area such as Railways, Defense, Water Management, Power, Meteorology,
and Transport.
Efftronics Systems Pvt. Ltd. has established, documented, implemented and maintains
a Quality Management System and continually improve-sits effectiveness in accordance with
the requirements of ISO 9001:2008 using PDCA as the operating principle.
2.1.3 Key Persons in the Organization:
 D. Rama Krishna, Managing Director/CEO, M/s. Efftronics Systems (P) Ltd., Vijayawada
since January 1988
 M. V. Murali Krishna, Director, Efftronics Systems (P) Ltd., since October 1992.
 Bhimavarapu Sambi Reddy, Director, Efftronics Systems (P) Ltd, since 04 November,

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2008.
2.1.4 Career at EFFTRONICS means
 Opportunity to learn & grow continuously.
 Opportunity to become a domain expert.
 Opportunity to work on latest technologies.
 Challenging assignments
 A world class working environment.
2.2 PRODUCT PROFILE:
Over 26 years in the embedded development industry has enabled Efftronics systems
to amass an enormous family of customers, partners and Value Added Resellers (VARs).
Efftronics systems provides products and services for a wide range of prestigious customers
including South-central railway, BSE and many more It want to become the worldwide market
leader of its kind. Efftronics believe that the extensive functionality and possibilities of our
embedded products and software will make every potential customer decide to choose our
products.
2.2.1 List of products developed by Efftronics:
2.2.1.1 Railways:
 Remote Terminal Units for Railway Signaling
 Integrated Passenger Information System
 LED Signal Lamps for Railways
 Digital Clock with GPS Synchronization
 Solid State Block Proving by Axle Counter
 Point Machine & Track Circuit Health Monitoring Unit

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 Water Level Warning System
 Flat Wheel Detection
2.2.1.2 Defense:
Battery Health Monitoring Unit
2.2.1.3Water Management:
SCADA Systems for Water Management
2.2.1.4 Power:
 Energy Information System
 Integrated Distributed Light Controller
 LED Lighting
2.2.1.5 Meteorology:
Automatic Weather Station
2.2.1.6 Transport:
Road Traffic Signals & Traffic light Controller
LED signs on Buses

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2.2.2 Product Development Process at Efftronics:
Fig. 2.1 Product Development Process at Efftronics
The above process is applied for an overall product development. The product may be
Challenge Management
Domain Study
Research
Prototype
Market Research
Standards and Third Party Evaluations
Product Specifications
Analysis
Design
Implementation
Testing
Product Release
Product Disposal
Maintenance and Upgradation

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a hardware solution or software solution or mix of both. The main aim of this organization is
to give complete solution to customers under problem under one roof.
2.2.3 Tools & Software’s used in this Organization:
Software Design: In software modules design, various tools and software’s are used by
our organization.
 Delphi: To develop software applications.
 Inter base: Database design
 .NET Frame Work: To develop software applications.
Mechanical Design: We develop our own enclosures and housings for all our products. The
design was being developed using following software’s:
 CATIA
2.3 ORGANIZATION STRUCTURE:
An organizational structure consists of activities such as task allocation, coordination
and supervision, which are directed towards the achievement of organizational aims. It can
also be considered as the viewing glass or perspective through which individuals see their
organization and its environment. Organizations are a variant of clustered entities.
An organization can be structured in many different ways, depending on their
objectives. The structure of an organization will determine the modes in which it operates and
performs.
Organizational structure allows the expressed allocation of responsibilities for different
functions and processes to different entities such as the branch, department, work
group and individual.

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Organizational structure affects organizational action in two big ways. First, it provides
the foundation on which standard operating procedures and routines rest. Second, it
determines which individuals get to participate in which decision-making processes, and thus
to what extent their views shape the organization’s actions.
Objectives:
Organizational structure is a business' skeleton. Organizations are alive and breathing,
so they require something to give them shape and support their life functions. Organizational
structures help everyone involved in a company to clarify and understand everyone else's role
and scope. They help facilitate divisions of labor, efficiency and assist in avoiding conflicts
and confusion. In turn, businesses get more done with fewer glitches and less strife.
Fig. 2.2 Organizational Structures
2.3.1 Departments and their functions:
There are different types of organizations. Few of them does only Production, few does

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only Research and Development, few does only distribution, few does only marketing, few
does only testing etc. Some of them may have combinations or all of these activities and
Efftronics Systems Pvt. Ltd. has all those operations. The different wings of Efftronics
Systems are:
 R&D (Research and Development)
 Production
 CS (Customer Support)
 Administration
The wings are further divided into sub categories.
R&D:
Product development is done in R&D. They start developing a product based on their
own idea after getting it approved from management or they may realize an idea from
customer.
Production:
They manufacture all the products required by the customer. The requirements of
customer are known by them from Sales department.
Assembling:
They do soldering of cards and later given for cleaning and heat test.
Testing:
Here the assembled cards are tested module wise and after few activities of Shop floor,
entire product will be tested.
Shop floor:
Fixings and Wiring is done in Shop floor

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QA:
QA is been divided into four wings. Where the inward material is tested assemble cards
are tested in the Process. This is called INPROCESS QA Finished Product QA, where the final
product is tested Calibration, Where the Quality Assurance of measuring equipment is done.
Purchases:
The material is bought from Vendors/Suppliers based on the requisitions of Stores.
Stores:
The material required in the entire organization is maintained safely and issued
whenever anyone needs it.
Sales & Marketing:
The products developed in R&D are marketed and sold and the requirements from
customers are given to R&D for development.
HRD:
HRD is been divided in to three divisions. HR GENERAL, where all the general
requirements of Employees like food, Uniform, Salary, Leaves, Grievances, if any, are dealt.
HR Recruitment, where the man power is given to the concerned required departments when
in need by the recruitment team.
CS:
Here the complaints from customers are logged and solved by the site engineers with
the help of technical team as soon as possible.
SYS ADMIN:
All the systems in the organization are maintained by this department. If any problem
is logged, it will be solved.

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General Administration:
All the reception activities, provision of food, tea, snacks for the employees etc. is
done by General Admin, department.
Finance & Accounts:
All the budgetary and accounting is done and expenditures of each department are
maintained.
Training Program:
INTERNSHIP program at Efftronics Systems Pvt. Ltd. is conducted in a well-
organized manner. During the initial days we were trained in various aspects like spreadsheet
training. Then we were assigned to a project. The works assigned later is also in various
phases. The training program and the works done will be detailed in this section.
The Orientation Program conducted at the company, Efftronics Systems Pvt. Ltd
commenced on 4th January, 2016 and continued till 11th January, 2016.
Induction Training:
The Induction training, gives the overall idea about the company. It started with the
introduction of the company’s mission and continued with vision, products, organizational
structure, departments in the company, and authorities of the company. The cycle of the
production, which contains the contribution of each department at various stages, along with
the number of days each department should take at each stage was briefed. Finally, the session
ended with the rules and norms to be followed during the course of our practice school.
What is 5S?
A 5S program is usually a part of and the key component of establishing a visual
workplace and are both a part of Kaizen- a system of continual improvement, which is
essential for manufacturing industries. The results you can expect from a 5S program are

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improved profitability, efficiency, service and safety.
Sort: The first step is making things cleaned up and organized.
Set in order: Organize, identify and arrange everything in a work area.
Shine: Regular cleaning and maintenance.
Standardize: Make it easy to maintain, simplify and standardize.
Sustain: Maintaining what have been accomplished.
QMS:
For any organization to succeed, Product Quality is the ultimate necessity of the
customer which has to be fulfilled. In achieving product Quality, processes play the crucial
role i.e., the requirements for any organization are:
 Product Quality
 Optimized process
Along with Quality, Cycle time & cost optimizations are essential factors. The basic
objective of establishing QMS in our organization is to achieve optimized
 Quality
 Cost
 Time
Efftronics Systems Pvt. Ltd. has established, documented, implemented and maintains
a Quality Management System and continually improves its effectiveness in accordance with
the requirements of ISO 9001:2008 using PDCA as the operating principle.
Quality Policy:
Efftronics Systems Pvt. Ltd. Shall provide Information Technology Products that does
Value creation to customer through products that exceed their expectations in functionality,
usability, reliability, performance, availability, adaptability and supportability.

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For this the organization shall establish and review Quality Objectives to focus on:
 Domain expertise and Technology management for building competence
 Quality improvement
 Customer Value Creation
 Human Resource Development
 Development of Niche Products
 World class product and process development
Quality Objectives
 Identification, understanding and effective implementation of technology for
development of products / services.
 Achieve MTBF of 3 years.
 Improve Quality in Sigma levels.
 Improve response time to customer requests.
 Education of customers in regard to product / technology applications.
 Increase organizational productivity by 25% every year.
 50% increase in turn over every year.

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The Quality Management System process sequence and interaction is defined here
Fig. 2.3 QMS sequence of interaction
Spread Sheet Training:
The data in the spread sheet is filled using functions, some logical functions like if
statement, sum functions, Subtract functions.
 Conditional formatting based on various logical tests is done.
 Pivot tables and charts are made from the already existing data, Page breaks and

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freezing the pane is practiced.
 After this Training I was assigned to the department of HR for improving &
ensuring the management development process. The Project and the works done
are detailed in the next part of the report.
 Filter and advanced filter are implemented and the difference in these options is
observed.
 Some cells are formatted in a way to satisfy one condition, if the inputted data
violates this rule then the software does not allow it. This is done with the data
validation option.
 The data from various sheets are consolidated into a new sheet using the data
consolidate option.
 What if analysis, both single variable and double variable are practiced and thus
the orientation program in the company was fruitful in many aspects. Finally, the
major aspect in which we were majorly trained is spread sheet.

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CHAPTER 3
COMMUNICATIONS
3.1 NEED FOR COMMUNICATION:
Communications is the field of study concerned with the transmission of information
through various means. It can also be defined as technology employed in transmitting
messages. It can also be defined as the inter-transmitting the content of data (speech, signals,
pulses etc.) from one node to another.
Mankind has always communicated, but the means of communication changes. Over the
past century, communication technologies have had a fundamental impact on how we carry
out our daily lives. Besides using the internet and mobile phones for interpersonal
communication; businesses, banking, transportation systems, TV and radio broadcasts and
smart power grids rely on advanced communication technology. In a constant and rapidly
evolving field, being as a communication engineer will be needed to design and build the
systems of the future.
When participants within the information system have a need to transmit and receive data
or information, the type of system required is a communication system. Communication
systems support people who are working together, by enabling the exchange of data and
information electronically. In this topic, the information processes of transmitting and
receiving are featured, with the other processes considered when relevant because all
information processes play a role in communication systems.

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3.2 CHARACTERISTICS OF COMMUNICATION SYSTEMS:
 Communication systems as being those systems which enable users to send and receive
data and information
 The framework in which communication systems function, demonstrated by the following
model
Fig. 3.1 Communication System Function Model
 The functions performed within the communication systems in passing messages between
source and destination, including:
 Message creation
 Organization of packets at the interface between source and transmitter
 Signal generation by the transmitter
 Transmission
 Synchronizing the exchange
 Addressing and routing

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 Error detection and correction
 Security and management
 The roles of protocols in communication
 handshaking and its importance in a communications link
 Functions performed by protocols at different levels
3.3 TYPES OF COMMUNICATION MEDIA:
The Communication Medium plays an important role in Networks. If the medium
works well and properly, then the speed of transferring data is good but if the medium is not
working properly, then your data would be delayed or would not be sent or even can be lost
during transmission. In Computer Networks, we call this speed of transmitting data, as
DATARATE.
There are two types of networks that you can set-up.
1. Wired Network and
2. Wireless Network
Fig. 3.2 Communication Channel

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3.3.1 Wired Network:
The Wired network is mostly set-up using an Ethernet Cable. This can be done using 3
technologies.
3.3.1.1 Twisted Pair Wires:
Fig. 3.3 Twisted pair wire
This technology was invented by Alexander Graham Bell. These wires are the most
oldest means of communication in computer networking. For more than 100 years, the phone
technology has used these wires. Most of use these twisted wires in our homes and offices.
These are the least expensive mode of communication used in networks.
In this, there is a pair of 2 copper wire, each 1-2 mm thick, enrolled on each other in a
spiral pattern. These are used to avoid interference from the nearby similar pairs. There are
number of pairs bundled together in a cable by wrapping the pairs in a protective shield. A pair
consists of a single communication link.
3.3.1.2 Coaxial Cables:
Fig. 3.4 coaxial cables
Coaxial Cables same as twisted Wire cables consists of two copper wire. But in this, the
two wires are concentric to each other. Coaxial Cables has a wire conductor in the center , a

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circumferential outer conductor known as foil shield, and an insulating medium called the
dielectric separating these two conductors. The outer conductor is protected in an outer jacket.
Coaxial Cables with this type of formation and special insulation and shielding, can
achieve high data transmission rates. Coaxial cables are common in cable television systems.
3.3.1.3 Fibre Optics:
Fig. 3.5 Fibre optics
An optical fiber is a flexible, thin, transparent fiber made of high quality glass or plastic,
slightly thicker than a human hair. Or you can also say an optical fiber is a thin, flexible
medium that conducts pulses of light, with each pulse representing a bit of your data. Fibre
optics can generate high Data Rates, so these are used for long distance communications,
which require high speed and least data loss. Optical Fibers have no electromagnetic
interference and can process data at GB/sec of speed.
This quality has made them popular in long run data transfers.
In United Kingdom and United States Of America and many other countries, most of them
use fiber optics in distance telephone networks.
But as they are very expensive also. So use of Fibre optics in local LAN , institutions,
companies etc. is still not very popular. The joining of two or optical fibre is still more
complex than joining two electrical wire or cables.

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3.3.2 Wireless network:
Examples:
 Bluetooth
 WI-FI
 WI-Max
 ZigBee etc..,
Types of communication:
1.Serial Communication
2.Parallel Communication
3.3.2.1 Serial communication:
Introduction:
Serial communication is common method of transmitting data between a computer and
a peripheral device such as a programmable instrument or even another computer. Serial
communication transmits data one bit at a time, sequentially, over a single communication line
to a receiver. Serial is also a most popular communication protocol that is used by many
devices for instrumentation; numerous GPIB-compatible devices also come with an RS-232
based port. This method is used when data transfer rates are very low or the data must be
transferred over long distances and also where the cost of cable and synchronization
difficulties make parallel communication impractical. Serial communication is popular
because most computers have one or more serial ports, so no extra hardware is needed other
than a cable to connect the instrument to the computer or two computers together.
Serial communication is often used either to control or to receive data from an embedded
microprocessor. Serial communication is a form of I/O in which the bits of a byte begin
transferred appear one after the other in a timed sequence on a single wire. Serial

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communication has become the standard for inter-computer communication. In this lab, we'll
try to build a serial link between 8051 and PC using RS232.
Many popular serial communication standards exist-some examples are:
 RS-232 (using UART)
 Serial peripheral interface (SPI)
 Synchronous Serial Port(SSP)
Fig. 3.6 Serial communication
In Telecommunication and Computer Science, serial communication is the process of
sending/receiving data in one bit at a time.
3.3.2.2 Parallel communication:
 Parallel communication implies sending a whole byte (or more) of data over multiple
parallel wires
 Control bits used to determine the timing for reading and writing the data
Fig. 3.7 Parallel communication

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Parallel communication is the process of sending/receiving multiple data bits at a time
through parallel channels.
3.3.2.3 Serial vs. Parallel Communication:
Table 3.1 Difference between Serial vs Parallel communication
Fig. 3.8 Serial vs. parallel communication
Serial Communication Parallel Communication
1. One data bit is transceived at a time 1. Multiple data bits are transceived at
a time
2. Slower 2. Faster
3. Less number of cables required to
transmit data
3. Higher number of cables required

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3.3.2.4 Major Factors Limiting Parallel Communication:
1. Speed: Superficially, the speed of a parallel link is equal to bit rate*number of
channels. In practice, clock skew reduces the speed of every link to the slowest of all
of the links.
2. Cable length: Crosstalk creates interference between the parallel lines, and the effect
only magnifies with the length of the communication link. This limits the length of the
communication cable that can be used.
These two are the major factors, which limit the use of parallel communication.
3.3.2.5 Advantages of Serial over Parallel:
 Clock skew between different channels is not an issue (for un-clocked asynchronous
serial communication links).
 A serial connection requires fewer interconnecting cables (e.g. wires/fibers) and hence
occupies less space. The extra space allows for better isolation of the channel from its
surroundings.
 Cross-talk is not a much significant issue, because there are fewer conductors in
proximity.
In many cases, serial is a better option because it is cheaper to implement. Many ICs have
serial interfaces, as opposed to parallel ones, so that they have fewer pins and are therefore
less expensive. It is because of these factors, serial communication is preferred over parallel
communication.
3.3.2.6 How is Data Serially?
When a particular data set is in the micro-controller, it is in parallel form, and any bit can
be accessed irrespective of its bit number. When this data set is transferred into the output
buffer to be transmitted, it is still in parallel form. This output buffer converts this data into

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Serial data (PISO) (Parallel In Serial Out), MSB (Most Significant Bit) first or LSB (Least
Significant Bit) first as according to the protocol. Now this data is transmitted in Serial mode.
When this data is received by another micro-controller in its receiver buffer, the receiver
buffer converts it back into parallel data (SIPO) (Serial In Parallel Out) for further
processing. The following diagram should make it clear.
Fig. 3.9 Serial Data Transfer
3.3.2.7 Serial Transmission Modes:
Serial data can be transferred in two modes –
 Asynchronous and
 Synchronous.
3.3.2.7.1 Asynchronous Data Transfer
Data Transfer is called Asynchronous when data bits are not “synchronized” with a
clock line, i.e. there is no clock line at all!
Asynchronous data transfer has a protocol, which is usually as follows:
 The first bit is always the START bit (which signifies the start of communication on
the serial line), followed by DATA bits (usually 8-bits), followed by a STOP bit (which
signals the end of data packet). There may be a Parity bit just before the STOP bit. The
Parity bit was earlier used for error checking, but is seldom used these days.
 The START bit is always low (0) while the STOP bit is always high (1).

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 The following diagram explains it.
Fig. 3.10 Asynchronous data transfer
3.3.2.7.2 Synchronous Data Transfer
Synchronous data transfer is when the data bits are “synchronized” with a clock pulse.
The concept for synchronous data transfer is simple, and as follows:
 The basic principle is that data bit sampling (or in other words, say, ‘recording’) is done
with respect to clock pluses, as you can see in the timing diagrams.
 Since data is sampled depending upon clock pulses, and since the clock sources are very
reliable, so there is much less error in synchronous as compared to asynchronous.
Fig. 3.11 Synchronous data transfer Timing diagram
3.3.2.8 Serial Communication Terminologies:
1.Simplex Communication: In this mode of serial communication, data can only be
transferred from transmitter to receiver and not vice versa.

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2.Half Duplex Communication: this means that data transmission can occur in only one
direction at a time, i.e. either from master to slave, or slave to master, but not both. Full
3.Duplex Communication: full duplex communication means that data can be transmitted
from the master to the slave, and from slave to the master as the same time!
Fig. 3.12 Types of Serial Communication
3.3.2.9 Importance of Baud Rate
For two micro controllers to communicate serially they should have the same baud rate,
else serial communication won’t work. This is because when you set a baud rate, you direct
the micro controller to transmit/receive the data at that particular rate. So if you set different
baud rates, then the receiver might miss out the bits the transmitter is sending (because it is
configured to receive data and process it with a different speed!)
Different baud rates are available for use. The most common ones are 2400, 4800, 9600,
19200, 38400 etc. You cannot choose any arbitrary baud rate, there are some fixed values
which you must use like 2400, 4800, etc. Please note that the unit of baud rate is bps (bits per
second).
3.3.2.10 UART and USART
UART stands for Universal Asynchronous Receiver Transmitter, whereas USART stands
for Universal Synchronous Asynchronous Receiver Transmitter. They are basically just a piece
of computer hardware that converts parallel data into serial data. The only difference between

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them is that UART supports only asynchronous mode, whereas USART supports both
asynchronous and synchronous modes. Unlike Ethernet, Firewire etc., there is no specific port
for UART/USART. They are commonly used in conjugation with protocols like RS-232, RS-
434 etc. (we have specific ports for these two!).
In synchronous transmission, the clock data is recovered separately from the data stream
and no start/stop bits are used. This improves the efficiency of transmission on suitable
channels since more of the bits sent are usable data and not character framing.
The USART has the following components:
 A clock generator, usually a multiple of the bit rate to allow sampling in the middle of
a bit period
 Input and output shift registers
 Transmit/receive control
 Read/write control logic
 Transmit/receive buffers (optional)
 Parallel data bus buffer (optional)
 First-in, first-out (FIFO) buffer memory (optional)
3.3.2.11 Serial Communication Protocols
A variety of communication protocols have been developed based on serial communication
in the past few decades. Some of them are:
1. SPI – Serial Peripheral Interface: It is a three-wire based communication system. One
wire each for Master to slave and Vice-versa, and one for clock pulses. There is an
additional SS (Slave Select) line, which is mostly used when we want to send/receive data
between multiple ICs.
The Serial Peripheral Interface (SPI) is a synchronous serial bus developed by

32
Motorola and present on many of their microcontrollers.
The SPI bus consists of four signals: master out slave in (MOSI), master in slave out
(MISO), serial clock (SCK), and active-low slave select (/SS). As a multi-master/slave
protocol, communications between the master and selected slave use the unidirectional
MISO and MOSI lines, to achieve data rates over 1Mbps in full duplex mode.
2. I2C – Inter-Integrated Circuit:
 The Inter-Integrated Circuit bus (I2C) is a patented interface developed by Philips
 The I2C bus is a half-duplex, synchronous, multi-master bus requiring only two
signal wires: data (SDA) and clock (SCL). These lines are pulled high via pull-up
resistors and controlled by the hardware via open-drain drivers, giving a wired-
AND interface
 I2C uses an addressable communications protocol that allows the master to
communicate with individual slaves using a 7-bit or 10-bit address. Each device
has an address that is assigned by Philips to the manufacturer of the device
 I2C has a rather interesting feature called clock stretching, which is done when the
slave device is unable to process the bit and wishes for more time
Fig. 3.13 Timing diagram of I2C

33
3.Ethernet: Used mostly in LAN connections, the bus consists of 8 lines, or 4 Tx/Rx
pairs.
4. Universal serial bus (USB): This is the most popular of all. Is used for virtually all
type of connections. The bus has 4 lines: VCC, Ground, Data+, and Data-.
Fig. 3.14 USB pin diagram
5. RS-232 – Recommended Standard 232:
The RS-232 is typically connected using a DB9 connector, which has 9 pins, out of which
5 are input, 3 are output, and one is Ground. You can still find this so-called “Serial” port in
some old PCs.
 Logic 0 is called “space”.
 Logic 1 is called “mark”.
Fig. 3.15 232 levels

34
 The voltage sent by using the RS-232 standard is sent with reference to a ‘common
ground or 0-V point’-called Single-ended.
Fig. 3.16 RS-232 Level Data Transmission
EIA-232F For a DB9 Connector:
Table 3.2 Pin Configuration Names of 232F
Pin Number Circuit Originates From Circuit Names
1 DCE
Data Carrier
Detect(Received Line Signal
Detector)
2 DCE Received Data
3 DTE Transmitted Data
4 DTE Data Terminal Ready
5 --- Ground
6 DCE Data Set Ready
7 DTE Request to Send
8 DCE Clear to send
9 DCE Ring Indicator

35
Fig. 3.17 RS-232 Data Transmission
Table 3.3: RS232 Pin names
DB9 Pin Number RS232 Name Direction
1 DCD In
2 RXD In
3 TXD Out
4 DTR Out
5 SG Ground
6 DSR In
7 RTS Out
8 CTS In
9 RI* In

36
Fig. 3.18 Pin diagram of DB9
 The TTL levels are transformed to RS-232 levels in the following form:
Fig. 3.19 TTL and RS232 voltage levels
6. RS-485:
Also defined by the EIA/TIA standard, this interface is now called TIA-485. It defines not
only a single device-to-device interface but also a communications bus that can be used to
form simple networks of multiple devices. Its configuration and specifications also extend the
range and data rate beyond the RS-232 interface capabilities.

37
The RS-485 standard specifies differential signaling on two lines rather than single-ended
with a voltage referenced to ground. Logic 1 is a level greater than –200 mV, and logic 0 is a
level greater than +200 mV. Typical line voltage levels from the line drivers are a minimum of
±1.5 V to a maximum of about ±6 V. Receiver input sensitivity is ±200 mV. Noise in the range
of ±200 mV is essentially blocked. The differential format produces effective common-mode
noise cancellation.
Table 3.4 Key Characteristics of RS-232 and RS-485
KEY CHARACTERISTICS OF THE RS-232 AND RS-485 SERIAL INTERFACES
PARAMETER RS-232 RS-485
Line Configuration Single-ended Differential
Mode of operation Simplex or full duplex Simplex or half duplex
Maximum cable length 50 feet 4000 feet
Maximum data rate 20 kbits/s 10 Mbits/s
Typical logic levels ±5 to ±15 V ±1.5 to ±6V
Minimum receiver input impedance 3 to 7 kΩ 12 kΩ
Receiver sensitivity ±3V ±200 mV
USB TO RS 485 BLOCK DIAGRAM:
Fig. 3.20 Block diagram of USB to RS485

38
CHAPTER 4
E1 COMMUNICATIONS
4.1 E1 CARRIER:
The E-carrier standards (ITU - Recommendation G.703, G.704, 7043) form part of the
Plesiochronous Digital Hierarchy (PDH) where groups of E1 circuits may be bundled onto
higher capacity links between telephone exchanges. This allows a Network Operators to
provide TDM circuit between customers. Unlike Internet data services (generally based on
Ethernet and IP which are Statistical Multiplexing technologies) E-carrier systems
permanently allocate capacity for a voice/ data call for its entire duration. This ensures
permanent quality because the transmission arrives with the same delay (latency)and
bandwidth at all times. This is the essence of time-division multiplexing (TDM) technology.
E1 circuits have been used widely in telephony (ISDN, GSM), datacom (leased lined, Frame
Relay) and synchronization of SDH and Mobile Network; nevertheless, the use of TDM / E-
Carrier is declining since early 2000 when Ethernet/IP begun to be used not only in LAN but
also in WAN.
4.2 E1 FRAME STRUCTURE:
An E1 link operates over two separate sets of wires, usually
 Unshielded twisted pair(balanced cable)
 Or using coaxial (unbalanced cable).
A nominal 3 volt peak signal is encoded with pulses using a method avoiding long periods
without polarity changes.
The line data rate is 2.048 M bit/s (full duplex, i.e. 2.048 M bit/s downstream and 2.048 M
bit/s upstream) which is split into 32 time slots, each being allocated 8 bits in turn. Thus each

39
time slot sends and receives an 8-bit PCM sample, usually encoded according to A-law
algorithm, 8000 times per second (8 ×8000 × 32= 2,048,000). Each individual channel can
support upto 64Kbps.
The E1 frame defines a cyclical set of 32 time slots of 8 bits. The time slot 0 is devoted to
transmission management and time slot 16 for signaling; the rest were assigned originally for
voice/data-transport.
Fig. 4.1 E1 Fame Structure

40
4.2.1 Special Time slots:
TS0:
 It is reserved for framing purposes, and alternately transmits a fixed pattern.
 This allows the receiver to lock onto the start of each frame and match up each channel
in turn.
 The standards allow for a full Cyclic Redundancy Check to be performed across all
bits transmitted in each frame, to detect if the circuit is losing bits(information),but this
is not always used.AnalarmsignalmayalsobetransmittedusingtimeslotTS0.
TS16:
 This slot is reserved for signaling purposes, to control call setup and tear down
according to one of several standard telecommunications protocols.
 This includes channel-associated signaling (CAS) where a set of bits is used to
replicate opening and closing the circuit, or using tone signaling which is passed
through on the voice circuits themselves.
4.2.2 Frame Alignment:
In an E1 channel, communication consists of sending consecutive frames from the
transmitter to the receiver. The receiver must receive an indication showing when the first
interval of each frame begins, so that, since it knows to which channel the information in each
time slot corresponds, it can DE multiplex correctly. This way, the bytes received in each slot
are assigned to the correct channel. A synchronization process is then established, and it is
known as frame alignment.
4.2.3 Frame Alignment Signal:
In order to implement the frame alignment system so that the receiver of the frame can tell
where it begins, there is what is called a frame alignment signal (FAS).

41
In the 2 M bit/s frames (shown above), the FAS is a combination of seven fixed bits
("0011011") transmitted in the first time slot in the frame (time slot zero or TS0). For the
alignment mechanism to be maintained, the FAS do not need to be transmitted in every frame.
Instead, this signal can be sent in alternate frames (in the first, in the third, in the fifth, and so
on). In this case, TS0 is used as the synchronization slot. The TS0 of the rest of the frames is
therefore available for other functions, such as the transmission of the alarms.
4.2.4 Multi Frame CRC-4:
In theTS0 of frames with FAS, the first bit is dedicated to carrying the cyclic redundancy
checksum (CRC).It tells us whether there are one or more bit errors in a specific group of data
received in the previous block of eight frames known as sub-multiframe.
4.2.5 Signaling Channel:
Signaling refers to the protocols that must be established between exchanges so that the
users can exchange in formation between them.
In the E1 PCM system, signaling information can be transmitted by two different methods:
 Common channel signaling(CCS)method
 Channel associated signaling(CAS)method
In both cases, the timeslot TS16 of the basic 2Mbit/s frame is used to transmit the signaling
information.
4.3 TERMS USED IN E1 CONCEPT:
4.3.1 Alarm Indication signal (AIS): (also called all "ones" because of data & framing
pattern)
It is a signal transmitted by an intermediate element of a multi-node transport circuit that is
part of a concatenated telecommunications system to alert the receiving end of the circuit that
a segment of the end-to-end link has failed at a logical or physical level, even if the system it

42
is directly connected to is still working. The AIS replaces the failed data, allowing the higher
order system in the concatenation to maintain its transmission framing integrity. Downstream
intermediate elements of the transport circuit propagate the AIS onwards to the destination
element.
4.3.2 HDB3 Coding:
Another coding scheme is HDB3, high density bipolar 3, used for 2.048MHz (E1)
carriers. This code is similar to BNZS in that it substitutes bipolar code for 4 consecutive zeros
according to the following rules:
If the polarity of the immediate preceding pulse is (-) and there have been an odd
(even) number of logic 1 pulses since the last substitution, each group of 4 consecutive zeros is
codedas000-(+00+).
If the polarity of the immediate preceding pulse is (+) then the substitution is 000+(-00-)
for odd(even) number of logic 1 pulses since the last substitution.
Fig. 4.2 HDB3 Coding
4.4 PCM FRAMING: (E1 Communication Time division Multiplexing):
Principles of multiplexing

43
Fig. 4.3 Principle of TDM
Source coding produces 8-bit code words at a rate of 8 kHz for each speech channel,
giving 64kbit/s which can then be transmitted. To improve the utilization of the transmission
medium, the signals are transmitted by time-division multiplexing, where the code words are
interleaved and contained in a pulse code modulation (PCM) frame. The figure above shows
the principle of time-division multiplexing as illustrated by the transmission of four digital
signals.
4.4.1 The Primary Frame:
A primary frame consists of 32 code words called time slots and is numbered 0 to 31. A
PCM31 frame comprises of 31 time slots used for traffic and 1 time slot used for
synchronization.
Fig. 4.4 Time slot of PCM31 System
In a PCM30 system the frame comprises of 30 time slots used for traffic and 2 code
words that are used for synchronization and signaling purposes.

44
Fig. 4.5 Timeslots of PCM30 System
4.4.2 Frame alignment:
The transmitting and receiving sides are synchronized to the PCM frame with the aid
of the Frame Alignment Signal (FAS) which is transmitted in time slot 0 of every second
frame. The Not Frame Alignment Signal (NFAS) is transmitted in time slot 0 of the alternate
frames.
Fig. 4.6 the FAS and NFAS Signals
4.4.3 Frame Alignment Signal (FAS):
Table 4.1 Truth Table of FAS
Bit number 1 2 3 4 5 6 7 8
Binary value S(C) 0 0 1 1 0 1 1
Bit 1: S i is reserved for international use, in PCM30 or PCM31 or
C is used for transmitting the CRC division remainder in PCM30C or PCM31C bits

45
4.4.4 FAS:
The receiving side of the PCM system determines the timeslots of the PCM frame on
the basis of the received frame alignment signals, so that the received bits can be assigned to
the various channels in the correct sequence.
The FAS is transmitted in timeslot 0 of every even PCM frame, i.e. frame numbers 0, 2, 4, 6,
and soon. It is always a 7 bit word with the binary sequence 001101 starting at bit 2.
Bit 1 in timeslot 0 is known as the Si bit and is reserved for international use. It is normally
set the 1except in systems that use CRC. Here the division remainder which results from the
comparison is transmitted to the receiving side using this bit.
4.4.5 Not Frame Alignment Signal (NFAS):
The NFAS is used to carry information about the status of the link and to provide control
signals for primary rate multiplexers.
Table 4.2 Truth Table of NFAS
Bit number 1 2 3 4 5 6 7 8
Binary value S(M) 1 A Sa4 Sa5 Sa6 Sa7 Sa8
Bit 1: Si is reserved for international use, in PCM30 or PCM31 or M is used for transmitting
the CRC-multiframe alignment signal in PCM30C or PCM31C;
Bit 2: is set to 1 - prevents simulation of the FAS;
Bit 3: A shows the remote alarm indication.
Bits 4 to 8: Sa4 to Sa8 are additional spare bits which can be used as follows:
4.4.6 Sa bits
ITU-T Recommendations allow for bits Sa4 to Sa8 to be used in specific point-to-point
applications (e.g. for transcoder equipment) within national borders. When these bits are not

46
used and on links crossing an international border they should be set to 1.
Bit Sa4 may be used as a message-based data link for operations, maintenance and
performance monitoring. This channel originates at the point where the frame is generated and
terminates where the frame is split up.
4.4.7 Frame Synchronization:
Fig. 4.7 2048kbit/s transmission system
PCMX 30 = Primary Multiplexer for 30 speech/data channels
LTE = Line Terminating Equipment
LR = Line Regenerator
Considering the multiplexers in the above diagram.
PCM multiplexer B will synchronize on to the incoming bit stream from multiplexer A under
the following conditions:
1.Correct FAS, Si 0 0 1 1 0 1 1, is received in timeslot 0 of a frame.
2.Bit 2 in timeslot 0 (NFAS) of the next frame received must be 1, Si 1 A Sa4 S a5 Sa6 Sa7
Sa8 is received in time slot 0.
3.FAS, Si 0 0 1 1 0 1 1, is received in timeslot 0 of the subsequent frame.
The multiplexer is synchronized on to the incoming frames only if all three conditions are
fulfilled.

47
4.5 SIGNALLING
In PCM30 and PCM30C systems timeslot 16 is used for channel-associated signalling
(CAS). The information necessary for switching and routing all 30 telephone channels
(signalling and status codes) are interleaved and transmitted in this timeslot.
The interchange of signalling between the multiplexers in the forward and backward
channel takes place using pulse signals comprising four bits (a, b, c, d) which are formed by
signalling multiplex equipment from the signals originating in the exchange. One example of a
Signalling method is Exchange and Multiplex (E & M) signalling.
Fig. 4.8 E& M signaling
4.5.1 E & M signalling
In this method, relay units are used to match the signals coming from the exchange to the
E & M equipment. The E & M multiplexer detects the signalling, converts it into 4-bit signals
and passes these on to the PCM multiplexer for insertion into timeslot 16 of the PCM frame.
Fig. 4.9 channel associated signalling

48
4.5.2 Channel-associated signalling (CAS)
Interchange of signalling in the forward and backward directions is accomplished using
bits that only change state slowly. It is therefore sufficient to transmit these relatively static
signalling bits at a rate of 2kbit/s for each subscriber.
As a result, the 64kbit/s capacity of timeslot 16 is divided between the 30 subscriber
channels and 2auxiliary channels for synchronization and alarms. A signalling multiframe is
formed which comprises16 normal PCM frames.
Each signalling timeslot of the multiframe has a transmission capacity of 4kbit/s (64kbit/s
divided into16 frames). Each of these timeslots is sub-divided to include 2 subscriber
channels, giving a signalling rate per channel of 2kbit/s.
Fig. 4.10 Signalling Time Slot
4.5.3 Signalling Multiframe
Fig. 4.11 Signalling Multiframe

49
The first four bits in timeslot 16 of the first frame (frame 0) of the signalling multiframe are
used to transmit the Multiframe Alignment Signal (MFAS) = 0 0 0 0. The last four bits contain
the Not Multiframe Alignment Signal (NMFAS) = X Y X X. The signalling multiframe
structure is as shown in the table below:
Table 4.3 Assignments of bits in time slot 16 of a signalling multiframe for channel
associated signalling
4.5.4 Pulse Dialing:
Since only timeslot 16 is used for CAS and 16 PCM frames are linked together to form
a signalling multiframe, it follows that this multiframe has a length of 16 x 125 µs = 2ms. This
means that the signalling information for all 30 subscribers are transmitted in a period of 2ms
and that the signalling information for each subscriber is updated every 2ms. This is sufficient,
since the shortest signalling pulses are the dialing pulses which have a pulse length to pause
ratio of 40 to 60ms which is long in comparison to the 2ms sampling interval.
Fig. 4.12 updating the signalling information at 2ms sampling intervals

50
4.6 CYCLIC REDUNDANCY CHECK (CRC):
With the introduction of ISDN (Integrated Services Digital Network), subscribers are
provided with transparent 64kbit/s channels for speech or data transmission. Transparent in
this sense means that the binary signal transmitted by the subscriber is transmitted over the
entire signal path without being altered in any way by analogue/digital conversion or other
means, with the bit sequence integrity preserved.
There is a danger with this type of data communication that the subscriber may
intentionally or unintentionally transmit the bit pattern 10011011 which corresponds to the
FAS. This may lead to the PCM multiplexer re-synchronizing to these apparent FAS, with the
result that all of the PCM channels will be incorrectly assigned.
To avoid this disastrous malfunction of the system, ITU-T Recommendation G.704
specifies the use of the CRC-4 cyclic redundancy check for 2048kbit/s systems. These are also
known as PCM30C andPCM31C systems.
Fig. 4.13 synchronization caused by simulation of frame alignment signal

51
4.6.1 CRC-4 method:
The transmitting side of the PCM multiplexer forms a CRC check block (block n)
from eight consecutive PCM frames. This block contains 2048 bits (8 x 256 bits). The check
block is multiplied by x4 and then divided by the generator polynomial x4 + x + 1
Example of the CRC-4 calculation:
The remainder from the division process, is also called the system signature, and
comprises of 4 bits. These are written into bit 1 in the frame alignment signals of the next data
block (n + 1) as the bits designated C1, C2, C3 and C4.
Fig. 4.14 Schematic diagram of CRC-4 function

52
After this, data block n is transmitted to the receiving side and again subjected to the same
multiplication and division process from which get a 4 bit remainder.
When data block n+1 is transmitted, the remainder from dividing data block n on the
transmitting side is also transmitted to the receiving side, where it is compared with the
remainder from dividing data block n on the receiving side. If the two remainders are identical,
no bit errors have occurred during transmission. If there is a difference between the two
remainders, it can only mean that the received block has been degraded by one or more bit
errors during transmission.
4.6.2 CRC multiframe:
Transmission of the remainder requires a capacity that is obtained by making use of the
otherwise redundant bit 1 in the FAS of each even-numbered frame. To locate the four check
bits C1, C2, C3, C4 making the remainder, a CRC multiframe is formed.
Fig. 4.15 CRC-4 multiframe

53
The CRC-4 multiframe consists of 16 PCM frames just like the signalling multiframe and
therefore also has duration of 2ms. This multiframe is divided into two 8 framed sub-
multiframe, I and II. A CRC Multiframe Alignment Signal (CRC MFAS) is used to
synchronize the receiving side to this multiframe.
The CRC MFAS is a 6-bit signal of 0 0 1 0 1 1 and is inserted bit-by-bit into the first bit of
the NFAS in frames 1, 3, 5, 7, 9 and 11. The first bits of frames 13 and 15 are called the E bits
and are used to indicate the data blocks with bit errors back to the transmitting side. If the E bit
in frame 13 = 0 it indicates that there is a CRC error in the data contained in sub-multiframe
me and if the E bit in frame 15is 0 it indicates the same situation for sub-multiframe II. These
E bit errors are also called remote or distant CRC errors.
As each CRC sub-multiframe comprises 8 standard PCM frames it is therefore 8 x 125µ s
= 1ms long so the system carries out 1000 CRC comparisons per second. When compared
with the monitoring of the FAS as carried out in systems without CRC, the CRC system has
the advantage of a greater degree of certainty in the detection of possible errors because all of
the transmitted data is monitored.
The system without CRC monitors only a small part of the signal, namely 7 bits for every
505 bits. The CRC method does not, however, detect all possible errors. A multiple error in a
CRC block may lead to the formation of the correct signature, even though the block contains
errors. Since the CRC remainder is a 4-bit word, it follows that 1/16th or 6.25% of the blocks
may contain errors, despite a correct signature. In other words, the certainty with which an
error can be detected is 93.75% of the total number of errors.
The standard procedure used in data communications of repeating any data blocks
containing errors is not possible in PCM transmissions, since the data is not buffered at any
point.

54
The CRC method cannot accurately determine single errors as it is not possible to say how
many errors was the cause of an incorrect remainder in the check sum. The result is therefore a
“greater than” result, which is sufficient, since the continuous monitoring makes it possible to
keep a constant watch on the transmission quality.
4.6.3 Frame Synchronization (with CRC-4):
A transmission system utilizing CRC-4 carries out 1000 CRC comparisons every
second. If the number of negative (incorrect) comparisons exceeds a threshold of 914 in 1000
(91.4%), the system goes out of synchronization. Resynchronization takes place in the
following manner:
1. Normal synchronization of the PCM system
a) Frame alignment signal correctly received
b) Second bit in the NFAS must be 1
c) Next FAS also received correctly.
2. synchronization of the CRC multiframe
Bit position 1 of the NFAS contained in the frames of the CRC multiframe is checked for
the CRC multiframe alignment signal of 0 0 1 0 1 1
CRC multiframe synchronization is achieved when at least 2 CRC MFAS have been
correctly received within a period of 8ms, (4 CRC sub multiframe). Between these two correct
CRC MFAS there must be2ms or a multiple thereof.
Only when the conditions 1 and 2 above are fulfilled is the system synchronized and CRC
calculations commence.
4.6.4 ALARMS:
4.6.4.1 Remote Alarms:
Multiplexers are connected together so the PCM transmissions take place in both directions; it

55
also follows that alarm messages are also transmitted bi-directionally.
Fig. 4.16 Alarm messages
4.6.4.2 Remote Alarm Indication:
The NFAS is used to transmit service information. But 3 of the NFAS indicate a remote (or
distant) alarm:
If Bit 3 is 0 - means undisturbed operation; no alarm.
If 1 - means that one of the following alarm situations has occurred:
Power supply failure
Codec failure
Failure of incoming 2048kbit/s signal
Frame alignment error
Frame alignment signal bit error ratio >1 x 10-3.
The multiplexer located at point B continuously monitors the incoming FAS for bit
errors. The FAS is received in timeslot 0 of alternate frames which is every 250 µ s or 4000
times per second. If the result of the bit error measurement of the FAS is ≤ 1 x 10 -3,
transmission is undisturbed. The NFAS transmitted back to point A will be Si 1 0 1 1 1 1
1.When the FAS bit error ratio reaches a value of greater than 1 x 10 -3, correct operation of
the transmission link is no longer possible and the receiving multiplexer goes out of

56
synchronization. This is indicated by setting the A bit of the NFAS to 1 which results in an
alarm, called a Remote Alarm Indication (RAI) or distant alarm. In this case the NFAS
transmitted back to point A is Si 1 1 1 1 1 1 1.
4.6.4.3 Alarm Indication Signal (AIS):
The multiplexer at point A registers this alarm and then stops transmitting normal speech
or data signals and transmits a continuous sequence of 1s. This causes the multiplexer on point
B to show an 33 AIS alarm. This all 1s signal maintains the clock recovery mechanism in the
regenerators so that resynchronization can be attempted as soon as the FAS bit error ratio
recovers to equal to or less than1 x 10 -3.
ITU-T defines AIS as more than 509 1s in a 512 bit block which is a signal containing less
than3 zeros in a 2 frame period. A signal with all bits in state 1 except for the FAS (001101 = 3
zeros) is not a valid AIS and should be declared as frame sync loss.
4.6.5 Frame sync loss:
Frame sync Loss is declared in PCM30 (PCM31) framing if three consecutive incorrect
FAS words are received or in PCM30C (PCM31C) framing if there more than 914 CRC errors
in one second.
4.6.6 Multiframe sync loss:
If the signalling MFAS is lost then multiframe sync loss alarm is declared.
4.6.7 Distant multiframe alarm:
If multiframe sync loss alarm is declared in one direction the Y bit in the NMFAS (bit 2) in
the opposite direction is set to 1 which results in a distant multiframe alarm.
4.7 LINE CODES:
There are two main functions of line coding:
• To ensure that there is sufficient timing information from the received signal

57
• To prevent ‘droop’
The repeater or DE multiplexer derives the sampling clock from the incoming signal and
the quality of this derived clock depends on the number of transitions of the incoming signal.
Droop is an effect that can occur when conveying data over a circuit which has zero dc
response. The nominal constant voltage levels can drift up or down due to the capacitance of
the transmission line charging and discharging. Droop results in the ‘wandering’ of the signal
levels and is known as baseline wander.
Any zero-mean bipolar waveforms that have long strings of 1s or 0s may result in
droop in the transmitted voltage level as shown above
Fig. 4.17 droop in a waveform
4.7.1 HDB3 code:
HDB3 stands for high density bipolar code in which a maximum of 3 zeros may occur
in sequence. The following rules are used to convert a binary signal into a HDB3 coded signal:
Rule 1: If four 0-bits occur consecutively, the fourth zero is replaced by a violation bit or V-
bit. The V-bit has the same polarity as the preceding 1-bit, which results in a violation of the
AMI rule.
The substitution is thus: 0 0 0 0 becomes 0 0 0 V.
Rule 2:If there is an even number of 1-bits between the violation bit to be inserted and the
previous violation bit, the first zero of the sequence of four zeros is replaced by the so-called

58
B-bit.
The substitution is thus: 0 0 0 0 becomes B 0 0 V.
This leads to an uneven number of 1-bits, which is necessary to ensure that the inserted
violation bit has the opposite polarity to the previous violation bit, so that the code remains
free of any DC component.
The violation bits and B-bits must always be inserted with alternating polarity (AMI) to
preserve the DC-free nature of the code.
Fig. 4.18 Converting binary signals to HDB3
Advantages of the HDB3 code:
• The clock recovery information required for regenerators in the signal path is retained in the
data signal despite long sequences of zeros
• The HDB3 code is DC-free and can therefore be transmitted using balanced, transformer-
coupled circuits.

59
Fig. 4.19 Interface and line codes used for 2048kbit/s
4.8 ITU-T G.703 RECOMMENDATION:
Table 4.4 Interface Requirements

60
CHAPTER 5
DS26521 IC E1 TRANSCEIVER
5.1 GENERAL DESCRIPTION:
The DS26521 is a single-channel framer and line interface unit (LIU) combination for T1,
E1, and J1 applications. Each channel is independently configurable, supporting both long-
haul and short-haul lines.
5.2 FEATURES:
 Complete T1, E1, or J1 Long-Haul/Short-Haul Transceiver (LIU plus Framer)
 Internal Software-Selectable Transmit- and Receive-Side Termination for 100Ω T1
Twisted Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair, and 75Ω E1 Coaxial
Applications
 Crystal-Less Jitter Attenuator can be Selected for Transmit or Receive Path; Jitter
Attenuator Meets ETS CTR 12/13, ITU-T G.736, G.742, G.823, and AT&T Pub 62411
 External Master Clock can be Multiple of 2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted for T1 or E1 Usage in the Host Mode
 Receive-Signal Level Indication from -2.5dB to -36dB in T1 Mode and -2.5dB to -
44dB in E1 Mode in Approximate 2.5dB Increments
 Transmit Open- and Short-Circuit Detection
 LIU LOS in Accordance with G.775, ETS 300 233, and T1.231
 Transmit Synchronizer
 Flexible Signaling Extraction and Insertion Using Either the System Interface or
Microprocessor Port

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 Alarm Detection and Insertion
 T1 Framing Formats of D4, SLC-96, and ESF
 J1 Support
 E1 G.704 and CRC-4 Multiframe
 Controlled by 8-Bit Parallel Port Interface or Serial Peripheral Interface (SPI)
5.3 APPLICATIONS:
 Routers
 Channel Service Units (CSUs)
 Data Service Units (DSUs)
 Muxes
 Switches
 Channel Banks
 T1/E1 Test Equipment
5.4 FUNCTIONAL DIAGRAM:
Fig. 5.1 Functional diagram of DS26521

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5.5 ORDERING INFORMATION:
Table 5.1 Ordering Information
5.6 DETAILED DESCRIPTION:
The DS26521 is a single-channel device that can be software configured for T1, E1, or J1
operation. The DS26521 is composed of a line interface unit (LIU), framer, HDLC controller,
and a TDM back plane interface, and is controlled by either an 8-bit parallel port or a serial
peripheral interface (SPI). Internal impedance matching is provided for both transmit and
receive paths reducing external component count.
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The
transmit interface is responsible for generating the necessary wave shapes for driving the
network and providing the correct source impedance depending on the type of media used.
E1 waveform generation includes G.703 wave shapes for both 75Ω coax and 120Ω
twisted cables. The receive interface provides network termination and recovers clock and data
from the network.
The jitter attenuator removes phase jitter from the transmitted or received signal.
On the transmit side, clock, data, and frame-sync signals are provided to the framer by the
backplane interface section.
5.7 MAJOR OPERATING MODES:
The DS26521 has two major modes of operation: T1 mode and E1 mode. The mode of
operation for the LIU is configured in the LIU Transmit Receive Control register (LTRCR).
The mode of operation for the framer is configured in the Transmit Master Mode register

63
(TMMR) and Receive Master Mode register (RMMR). J1 operation is a special case of T1
operating mode.
5.8 FEATURE HIGHLIGHTS:
General
 Single-port member of the TEX-series transceiver family of devices
 64-pin LQFP package
 3.3V supply with 5V tolerant inputs and outputs.
Line Interface
 Master clock can be 1.544MHz, 2.048MHz, 3.088MHz, 4.096MHz, 6.276MHz,
8.192MHz, 12.552MHz, or 16.384MHz
 Ranges include 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1
 Analog loss-of-signal detection
 AIS generation independent of loop backs
 Transmit open-circuit-detected indication
Clock Synthesizer
 Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
Framer/Formatter
 E1 FAS framing and CRC-4 multiframe per G.704, G.706, and G.732 CAS multiframe
 Transmit mid path CRC recalculate (E1)
System Interface
 Independent two-frame receive and transmit elastic stores
 Independent control and clocking

64
5.9 BLOCK DIAGRAM:
Fig. 5.2 Block diagram of DS26521

65
5.10 DETAILED BLOCK DIAGRAM:
Fig. 5.3 Detailed block diagram of DS26522

66
CHAPTER 6
FRAMED MODE IMPLEMENTATION IN RS232 CONVERTER
6.1 FPGA DESIGN
6.1.1 Inputs:
 RCH_Clk
 RSync
 Framed/Unframed (given to FPGA Sclk pin 1623 Ver 1.1 Layout)
 RSER
6.1.2 Output:
 RSER_FPGA
6.1.3 Functionality
FPGA Hold’s data during Time slot 0 and Time slot 16 with previous time slot data at
receiving side

67
6.1.4 BLOCK DIAGRAM:
Fig. 6.1 Block diagram of FPGA

68
6.2 COUNTER BLOCK
6.2.1 Inputs:
Fig 6.2: Counter block timing diagram
 RCH_Clk
 RSync
6.2.2 Outputs:
 S4,S3,S2,S1,S0
6.2.3 Functionality:
 RSync pulse occurs for every 32 channels & RCH_Clk pulse occurs for every
channel’s LSB Bit time.
 Counter increments for every RCH_Clk pulse and resets whenever RSync occurs
Output of the counter is given to Combinational Logic
6.2.4 Transition Table:
 Refer FPGA Truth tables Counter transition table

69
Table 6.1 Truth Table of counter block
COUNTER BLOCK
INPUTS PRESENT STATE NEXT STATE
RCHCLK RSync S4 S3 S2 S1 S0 S4 S3 S2 S1 S0
X 1 X x x x X 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 1 0 0 0 1 0
1 0 0 0 0 1 0 0 0 0 1 1
1 0 0 0 0 1 1 0 0 1 0 0
1 0 0 0 1 0 0 0 0 1 0 1
1 0 0 0 1 0 1 0 0 1 1 0
1 0 0 0 1 1 0 0 0 1 1 1
1 0 0 0 1 1 1 0 1 0 0 0
1 0 0 1 0 0 0 0 1 0 0 1
1 0 0 1 0 0 1 0 1 0 1 0
1 0 0 1 0 1 0 0 1 0 1 1
1 0 0 1 0 1 1 0 1 1 0 0
1 0 0 1 1 0 0 0 1 1 0 1
1 0 0 1 1 0 1 0 1 1 1 0
1 0 0 1 1 1 0 0 1 1 1 1
1 0 0 1 1 1 1 1 0 0 0 0
1 0 1 0 0 0 0 1 0 0 0 1
1 0 1 0 0 0 1 1 0 0 1 0

70
1 0 1 0 0 1 0 1 0 0 1 1
1 0 1 0 0 1 1 1 0 1 0 0
1 0 1 0 1 0 0 1 0 1 0 1
1 0 1 0 1 0 1 1 0 1 1 0
1 0 1 0 1 1 0 1 0 1 1 1
1 0 1 0 1 1 1 1 1 0 0 0
1 0 1 1 0 0 0 1 1 0 0 1
1 0 1 1 0 0 1 1 1 0 1 0
1 0 1 1 0 1 0 1 1 0 1 1
1 0 1 1 0 1 1 1 1 1 0 0
1 0 1 1 1 0 0 1 1 1 0 1
1 0 1 1 1 0 1 1 1 1 1 0
1 0 1 1 1 1 0 1 1 1 1 1
1 0 1 1 1 1 1 0 0 0 0 0
6.3 COMBINATIONAL LOGIC DESIGN
6.3.1 Inputs:
 Counter’s o/p(S0,S1,S2,S3,S4)
 RCHCLK
6.3.2 Outputs:
 LE ( Latch Enable )
Output LE (Latch Enable) becomes low (Disable) during
 Timeslot 31 RCH_Clk Rising Edge to Timeslot 1 RCH_Clk Falling edge

71
 Timeslot 15 RCH_Clk Rising Edge to Timeslot 17 RCH_Clk Falling edge
And LE will be ‘high’ otherwise
6.3.4 Truth Table
 FPGA Truth table
Table 6.2 Truth table of combinational block
Combinational Block Truth Table
Inputs Outputs
S4 S3 S2 S1 S0 RCHCLK LE
0 0 0 0 0 X 0
0 0 0 0 1 1 0
0 0 0 0 1 0 1
0 0 0 1 0 X 1
0 0 0 1 1 X 1
0 0 1 0 0 X 1
0 0 1 0 1 X 1
0 0 1 1 0 X 1
0 0 1 1 1 X 1
0 1 0 0 0 X 1
0 1 0 0 1 X 1
0 1 0 1 0 X 1
0 1 0 1 1 X 1
0 1 1 0 0 X 1
0 1 1 0 1 X 1

72
0 1 1 1 0 X 1
0 1 1 1 1 X 1
1 0 0 0 0 1 0
1 0 0 0 1 0 0
1 0 0 1 0 X 1
1 0 0 1 1 X 1
1 0 1 0 0 X 1
1 0 1 0 1 X 1
1 0 1 1 0 X 1
1 0 1 1 1 X 1
1 1 0 0 0 X 1
1 1 0 0 1 X 1
1 1 0 1 0 X 1
1 1 0 1 1 X 1
1 1 1 0 0 X 1
1 1 1 0 1 X 1
1 1 1 1 0 X 1
1 1 1 1 1 X 1
6.4 LATCH BLOCK
6.4.1 Inputs:
 LE ( Latch Enable ) ,
 RSER

73
6.4.2 Outputs:
 RSER_FPGA
 Output RSER_FPGA Follows I/p RSER Data whenever LE is Enable(Logic ‘1’) and
Latches to previous data whenever LE is Disable (Logic ‘0’)
6.4.4 Truth Table
 FPGA_ Latch Truth table
Table 6.3 Truth table of FPGA latch
Latch Truth Table
Inputs Outputs
RSER LE RSER_FPGA
1 1 1
0 1 0
1 0 Previous Latched
Data0 0

74
CHAPTER 7
CONCLUSION
Thus, the implementation of FPGA module for Framed and Unframed modes making
use of CRC and without CRC using a combinational block and verifying it using test cases,
that is with Truth tables of Latch and Combinational Block and obtaining the required
functionality is the major task and has been successfully designed and implemented. After
conducting tests at different baud rates for RS-485 cable, it is observed that at higher baud
rates like 57600 and 115200 there exists data corruption at Half and Full Throughputs.

75
REFERENCES
[1] https://www.maximintegrated.com/
[2] http://telecombasics.blogspot.in/2009/06/e1.html
[3] http://www.radio-electronics.com/info/telecommunications_networks/e-carrier/e1-
interface.php
[4] http://www.rfwireless-world.com/Terminology/CAS-vs-CCS.html
[5] http://en.wikipedia.org/wiki/E-carrier
[6] http://maxembedded.com/2013/09/serial-communication-introduction/
[7] http://www.embedded.com/design/connectivity/4023975/Serial-Protocols-
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