This document discusses a simulation framework that aims to eliminate traditional device interfacing overheads and enable standardized accelerator interfacing to Intel SoCs. It achieves performance gains through virtual address-based execution at accelerators as well as hardware scheduling and memory management. The application interface uses an extended OpenCL API, while the Simics-based simulation testbed enables driverless execution with IPMMU-based virtual memory offload and hardware job scheduling.

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SoC Accelerator Interfacing
Simulation Framework
• Eliminate traditional device interfacing overheads and enable
standardized accelerator interfacing to Intel SoCs
• Performance gains achieved through virtual address based
execution at the accelerators as well as hardware
scheduling/memory management.
• Application interface through extended OpenCL API.
Simics based simulation testbed
• Driverless execution with IPMMU based virtual memory offload and
Hardware job scheduling
• OpenCL extended API for offload and OS based IO Page Fault
handling
Simics Simulation Models
Integrated Platforms Research/SoC Platform Architecture
Offload Architecture Components
Core
Memory
Accelerator
OpenCL
extensions
IPMMU
CMD Q
Scheduling
IPMMU enables
accelerator to
be in the same
memory domain
as the core
Extended OpenCL API
allows for standard
interface to
accelerators
CMD Q and
Cache/Buffer
allows for efficiency
in control/data paths