1
Computer Architecture and
Design
Computer Architecture and Design
Computer System
Engineering Department
2
Instruction Code
Embedded System Development
Lecture 1
Lecture 4 Computer Architecture and Design 3
Instruction code
 An instruction code is a group of bits that tells
the computer to perform a specific operation part.
 A computer instruction is a binary code that
specifies a sequence of micro-operations for the
computer.
 Instruction codes and data are stored in memory.
 Computer read each instruction from memory and
places it in a control register.
 Control unit interprets the binary code of the
instruction and proceeds to execute it by issuing a
sequence of micro-operations.
Lecture 4 Computer Architecture and Design 4
Instruction code
 It is divided into two parts operation part and Address
part.
 Operation code
 Group of bits
 Operations
 add
 subtract
 shift
 complement.
 The number of bits required for the operation code
depends on the total number of operations available in
the computer.
 2n
distinct operations  n bit operation code
Lecture 4 Computer Architecture and Design 5
Instruction code
Lecture 4 Computer Architecture and Design 6
Instruction code
Lecture 4 Computer Architecture and Design 7
Instruction code (Addressing)
 Three Addressing Modes used for
address portion of the instruction
code.
Immediate: the operand is given in
the address portion (constant).
Direct: the address points to the
operand stored in the memory.
Indirect: the address points to the
pointer (another address) stored in
the memory that references the
operand in memory.
Lecture 4 Computer Architecture and Design 8
Instruction code (Addressing)
Lecture 4 Computer Architecture and Design 9
Computer Instruction
 Computer instructions are
normally stored in consecutive
memory locations and executed
sequentially one at a time.
 Control unit reads an instruction
from a specific address in memory
and executes it.
 Needs counter to calculate the
address of the next instruction
after execution of the current
instruction is completed.
Lecture 4 Computer Architecture and Design 10
Computer Instruction
 Instruction Register IR is used in
the control unit for storing the
instruction code after it is read from
memory.
 The computer needs processor
registers or Accumulator
register AC for manipulating data
and a register for holding a memory
address.
Lecture 4 Computer Architecture and Design 11
Computer Instruction
Lecture 4 Computer Architecture and Design 12
Instruction format (Memory ref inst)
Lecture 4 Computer Architecture and Design 13
Instruction format (Register ref inst)
Lecture 4 Computer Architecture and Design 14
Instruction format (input - output ref inst)
Lecture 4 Computer Architecture and Design 15
Timing and control
Lecture 4 Computer Architecture and Design 16
Instruction cycle
 Phases of Instruction Cycle :
1- Fetch cycle
2- Execute cycle
3- Indirect cycle
4- Interrupt cycle
 Instruction cycle repeats
indefinitely unless a HALT
instruction is encountered.
Lecture 4 Computer Architecture and Design 17
Fetch cycle
c0T0: MAR PC
←
c0T1: MBR MAR, PC PC+1
← ←
c0T2: OPR MBR(OP),
←
I MBR(I)
←
Lecture 4 Computer Architecture and Design 18
Flow chart Instruction cycle
Lecture 4 Computer Architecture and Design 19
Execution of Memory Ref Inst
Lecture 4 Computer Architecture and Design 20
Execution of Branch and save return
Address (BSA)
M[AR] PC, PC
AR+1
Lecture 4 Computer Architecture and Design 21
Complete Computer Description
Lecture 4 Computer Architecture and Design 22
ALLAH HAFIZ

Computer Architecture notes by Beenish Lecture 4.ppt

  • 1.
    1 Computer Architecture and Design ComputerArchitecture and Design Computer System Engineering Department
  • 2.
  • 3.
    Lecture 4 ComputerArchitecture and Design 3 Instruction code  An instruction code is a group of bits that tells the computer to perform a specific operation part.  A computer instruction is a binary code that specifies a sequence of micro-operations for the computer.  Instruction codes and data are stored in memory.  Computer read each instruction from memory and places it in a control register.  Control unit interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of micro-operations.
  • 4.
    Lecture 4 ComputerArchitecture and Design 4 Instruction code  It is divided into two parts operation part and Address part.  Operation code  Group of bits  Operations  add  subtract  shift  complement.  The number of bits required for the operation code depends on the total number of operations available in the computer.  2n distinct operations  n bit operation code
  • 5.
    Lecture 4 ComputerArchitecture and Design 5 Instruction code
  • 6.
    Lecture 4 ComputerArchitecture and Design 6 Instruction code
  • 7.
    Lecture 4 ComputerArchitecture and Design 7 Instruction code (Addressing)  Three Addressing Modes used for address portion of the instruction code. Immediate: the operand is given in the address portion (constant). Direct: the address points to the operand stored in the memory. Indirect: the address points to the pointer (another address) stored in the memory that references the operand in memory.
  • 8.
    Lecture 4 ComputerArchitecture and Design 8 Instruction code (Addressing)
  • 9.
    Lecture 4 ComputerArchitecture and Design 9 Computer Instruction  Computer instructions are normally stored in consecutive memory locations and executed sequentially one at a time.  Control unit reads an instruction from a specific address in memory and executes it.  Needs counter to calculate the address of the next instruction after execution of the current instruction is completed.
  • 10.
    Lecture 4 ComputerArchitecture and Design 10 Computer Instruction  Instruction Register IR is used in the control unit for storing the instruction code after it is read from memory.  The computer needs processor registers or Accumulator register AC for manipulating data and a register for holding a memory address.
  • 11.
    Lecture 4 ComputerArchitecture and Design 11 Computer Instruction
  • 12.
    Lecture 4 ComputerArchitecture and Design 12 Instruction format (Memory ref inst)
  • 13.
    Lecture 4 ComputerArchitecture and Design 13 Instruction format (Register ref inst)
  • 14.
    Lecture 4 ComputerArchitecture and Design 14 Instruction format (input - output ref inst)
  • 15.
    Lecture 4 ComputerArchitecture and Design 15 Timing and control
  • 16.
    Lecture 4 ComputerArchitecture and Design 16 Instruction cycle  Phases of Instruction Cycle : 1- Fetch cycle 2- Execute cycle 3- Indirect cycle 4- Interrupt cycle  Instruction cycle repeats indefinitely unless a HALT instruction is encountered.
  • 17.
    Lecture 4 ComputerArchitecture and Design 17 Fetch cycle c0T0: MAR PC ← c0T1: MBR MAR, PC PC+1 ← ← c0T2: OPR MBR(OP), ← I MBR(I) ←
  • 18.
    Lecture 4 ComputerArchitecture and Design 18 Flow chart Instruction cycle
  • 19.
    Lecture 4 ComputerArchitecture and Design 19 Execution of Memory Ref Inst
  • 20.
    Lecture 4 ComputerArchitecture and Design 20 Execution of Branch and save return Address (BSA) M[AR] PC, PC AR+1
  • 21.
    Lecture 4 ComputerArchitecture and Design 21 Complete Computer Description
  • 22.
    Lecture 4 ComputerArchitecture and Design 22 ALLAH HAFIZ