The document discusses cache memory mapping types, including direct mapping, fully associative mapping, and k-way set associative mapping, each with their pros and cons. It explains how cache mapping brings content from main memory into cache and provides mechanisms for how CPUs process data via physical addresses. Additionally, the document includes technical details such as the number of bits required for indexing and tag bits in direct mapped cache examples.

1. Prestige Institute of Engineering Management and Research
Presented by :
Sahil Khan
Mansoori
Rohit Rathore
Rupali Roy
Saloni Patel
Presented to :
Dr. Charu Verma
Topic :Cache memory Mapping types

2. Cache Mapping
Cache Mapping types
• Direct Mapping
• Fully Associative Mapping
• K-way Set Associative Mapping
 Pros. And Cons. Of all type of mapping

3. What is Cache Mapping ?
Cache Mapping refers to a technique
using which the content present in the
main memory is brought into the memory
of the cache .

4. What is Cache Mapping ?
CPU
Cache
Memory
RAM SSD
CPU Chip
Primary
Memory
Secondary
Memory
Mapping Virtual
Mapping

5. Types of Cache Mapping
There are three type of Cache Mapping
K-way Set
Associative Mapping
Cache
Mapping
Direct
Mapping
Associative
Mapping

6. What is Direct Mapping ?
In the case of direct mapping, a
certain block of the main memory
would be able to map a cache only up
to a certain line of the cache.

7. What is Direct Mapping ?
B0
B1
B2
B3
B4
B31
L1
L2
L3
L4
128 Word
16 word
Cache Memory
RAM
W0 W1 W2 W3
W4 W5 W6 W7
W8 W9 W10 W11
W12 W13 W14 W15
W16 W17 W18 W19
W124 W125 W126 W127
The total line numbers of cache to which any distinct block
can map :
K mod n
Here, k=Block No. , n = no. of line

8. How CPU Process Data ?
CPU provide an Physical address of data in ram
Block offset (size)
Block No.
This Address is converted into :
Block offset (size)
Line
No.
Tag

9. Question ?
Consider a direct mapped Cache of size 32 KB with block size 32 bytes . The CPU generates 32
bit addresses , find the no. of bits required for line indexing and tag bits respectively
Solve :
Block offset (size)
Tag Line
No.
32 bit
Block size = 32 bytes = 25
which means 5 bit required
Line number = Cache size / block size
= 32 KB / 32 B
= 210
5 bit
Which means
10 bit required
for line no.
10 bit
17 bit

10. What is Associative Mapping ?
The main memory block is capable of
mapping to any given line of the
cache that’s available freely at that
particular moment.

11. What is Associative Mapping ?
B0
B1
B2
B3
B4
B31
L1
L2
L3
L4
128 Word
16 word
Cache Memory
RAM
W0 W1 W2 W3
W4 W5 W6 W7
W8 W9 W10 W11
W12 W13 W14 W15
W16 W17 W18 W19
W124 W125 W126 W127

12. How CPU Process Data ?
CPU provide an Physical address of data in ram
Block offset (size)
Block No.
This Address is converted into :
Block offset (size)
Tag

13. What is K- way Set Associative Mapping ?
The grouping of the cache lines occurs
into various sets where all the sets
consist of k number of lines.
Any given main memory block can
map only to a particular cache set.

14. B0
B1
B2
B3
B4
B31
L1
L2
L3
L4
128 Word
16 word
Cache Memory
RAM
W0 W1 W2 W3
W4 W5 W6 W7
W8 W9 W10 W11
W12 W13 W14 W15
W16 W17 W18 W19
W124 W125 W126 W127
What is K- way Set Associative Mapping ?
S0
S1
The total set numbers of cache to which any distinct block can
map :
k mod n
no. of set = no. of line / K
Here, k=Block No. , n = no. of sets

15. How CPU Process Data ?
CPU provide an Physical address of data in ram
Block offset (size)
Block No.
This Address is converted into :
Block offset (size)
Set
No.
Tag

16. Thank you