The document summarizes a master's thesis on an all-digital semi-blind clock and data recovery system. It includes sections on CDR introduction and OC-192 standards, prior art, the proposed design, and modeling and simulation results. The proposed design uses an all-digital PLL for clock generation, modifies the OSCDR phase picking algorithm, and integrates SBCDR to achieve jitter tolerance of over 800 kHz while limiting jitter transfer to under 120 kHz and generation to 0.03 UIrms, meeting OC-192 requirements.

1. AN ALL-DIGITAL SEMI-BLIND CLOCK AND
DATA RECOVERY SYSTEM
Mina Mofreh Gad Elsayed Abdallah
“Completion of Master degree”
3/8/2015 Master Thesis defense 1

2. TOC
3/8/2015 Master Thesis defense 2
CDR Introduction + OC-192 standard
Prior ART
Proposed Design
Modeling + Simulation

3. CDR INTRODUCTION &
OC-192 STANDARD
CDR definition + CDR metrics + OC-192 requirements
3/8/2015 Master Thesis defense 3

4. • CDR definition:
3/8/2015 Master Thesis defense 4
CDR Introduction + oc-192 standard
[CDR definition]
Serial link
Clock and Data
Recovery

5. • Jitter Definition
– 1 bit period Tb = 1 UI
– Jitter signal defined as Je
3/8/2015 Master Thesis defense 5
CDR Introduction + oc-192 standard
[CDR metrics]

6. • Jitter tolerance (JTo):
– Input jitter ‘Je‘ the CDR can tolerate
3/8/2015 Master Thesis defense 6
CDR Introduction + oc-192 standard
[CDR metrics]

7. • Jitter transfer (JTr):
– Je transferred to the recovered clock
3/8/2015 Master Thesis defense 7
CDR Introduction + oc-192 standard
[CDR metrics]

8. • Jitter generation (JG):
– Jitter generated in the recovered clock @ Je = 0
3/8/2015 Master Thesis defense 8
CDR Introduction + oc-192 standard
[CDR metrics]

9. • Network Configuration: [ITU-T G.783 2006, Telec. GR-253 2000]
3/8/2015 Master Thesis defense 9
CDR Introduction + oc-192 standard
[OC-192 standard]

10. • Requirements JTo – JTr [ref_oc192]:
[JTr BW = 120 KHz, JTo requires BW > 800 KHz]
3/8/2015 Master Thesis defense 11
CDR Introduction + oc-192 standard
[OC-192 standard]

11. • Requirements JG [ref_oc192]:
3/8/2015 Master Thesis defense 13
CDR Introduction + oc-192 standard
[OC-192 standard]
0.03 UIrms
0.01 UIrms

12. TOC
3/8/2015 Master Thesis defense 14
CDR Introduction + OC-192 standard
Prior ART
Proposed Design
Modeling + Simulation

13. PRIOR ART
PLL-CDR + OSCDR + SBCDR
3/8/2015 Master Thesis defense 15

14. • Feed-back CDRs:
Provides a recovered clock that tracks the
input jitter Je.
– PLL CDRs [Scheytt et al. 1999, Muthali et al. 2004]
– DLL CDRs [Maillard et al. 2002]
– Hybrid CDRs [Rhee et al. 2003, Dalton et al. 2005]
– Phase Interpolator/Selector CDRs
[Kreienkamp et al. 2003, Hanumolu et al 2008]
3/8/2015 Master Thesis defense 16
PRIOR-ART
[PLL CDRs]

15. • PLL-CDRs
– Mostly common CDR
– conventionally used for OC-192 [Cao et al. 2002, Henrickson et al.
2003, Werkeret al. 2004, Muthali et al. 2004]
3/8/2015 Master Thesis defense 17
PRIOR-ART
[PLL CDRs]

16. • PLL-CDRs draw-backs
– Analog intensive
– JTo, JTr, and JG are tightly coupled through PLL
bandwidth
[JTr requires BE < 120 KHz, JTo requires BW > 800 KHz,
and JG requires an optimized BW of few 100 KHz for LC oscillator
and few MHz for ring oscillator]
– Does not provide required JTr/JG as a stand-alone
clocking macro
3/8/2015 Master Thesis defense 18
PRIOR-ART
[PLL CDRs]

17. • PLL-CDRs draw-backs
3/8/2015 Master Thesis defense 19
PRIOR-ART
[PLL CDRs]

18. • OSCDR [over-sampling CDR] : [Kim et al. 2003, Kolka et al. 2010]
– Over samples the data, Detects the average transition phase ATP
– Selects the optimum sampling phase
3/8/2015 Master Thesis defense 20
PRIOR-ART
[OSCDR CDRs]

19. • OSCDR JTo [dependent on data scrambling length]:
– Maximum jitter variation ~ 0.5 UI [floor(0.5
OSR)/OSR] between consecutive transitions (NrTb)
– Above FC1(1/2NrTb)
limited to 0.5 UI
– Below FC1 increases
by 1/f
3/8/2015 Master Thesis defense 21
PRIOR-ART
[OSCDR CDRs]

20. • OSCDR JTo [dependent on data scrambling length]:
– Below FC2 limited by FIFO over flow
3/8/2015 Master Thesis defense 22
PRIOR-ART
[OSCDR CDRs]

21. • OSCDR draw-backs:
– Does not provide a recovered clock
– Can not deal with any frequency error between
data and internal clock.
– The OSCDR phase-picking algorithm is complex
to run at muti-giga hertz links.
3/8/2015 Master Thesis defense 23
PRIOR-ART
[OSCDR CDRs]

22. • SBCDR [semi-blind CDR] [Ierssel et al.2007]:
– The sampling/recovered clock tracks the input data
– A hybrid between PLL/OS CDRs
• Extended range
Phase detector
for PLL-CDR
• Phase tracking
capability for
OSCDR
3/8/2015 Master Thesis defense 24
PRIOR-ART
[SBCDR CDRs]

23. • SBCDR [Advantages]:
– The required minimum bandwidth for achieving
JTo is relaxed [The figure shows an example with a 16-bit FIFO]
– The FIFO depth provides
an extra degree of
freedom to compensate
for the required
bandwidth
by the JTr
3/8/2015 Master Thesis defense 25
PRIOR-ART
[SBCDR CDRs]

24. • SBCDR [Draw-backs]:
– The analog nature of the feed-back path.
[PVT dependent and requires over-design]
– The analog filter requires large capacitors
– The JTr and JG are still tightly coupled through
loop bandwidth
– Doe not resolve the OSCDR speed issues
3/8/2015 Master Thesis defense 26
PRIOR-ART
[SBCDR CDRs]

25. TOC
3/8/2015 Master Thesis defense 27
CDR Introduction + OC-192 standard
Prior ART
Proposed Design
Modeling + Simulation

26. PROPOSED ARCHITECTURE
OSCDR algorithm + ADPLL usage + SBCDR integration
3/8/2015 Master Thesis defense 28

27. • Major:
– An ADPLL is used instead of a VCO.
– The OSCDR phase picking algorithm is totally
modified.
• Minor:
– The usage of a DLF
– The usage of OSCDR data + FIFO to control
ADPLL
– TDC Architecture3 within the ADPLL
3/8/2015 Master Thesis defense 29
Proposed Architecture
[Proposed addition for SBCDR]

28. • A block diagram for the proposed design
3/8/2015 Master Thesis defense 30
Proposed Architecture

29. • The advantage of using ADPLL + ring VCO:
– Reduces the die-area due to the removal of analog
filter and the VCO inductor.
– The SBCDR loop dynamics is set by the digital
OSCDR and the digital control of the ADPLL
[N.Fref]
“The SBCDR loop bandwidth is PVT independent”
3/8/2015 Master Thesis defense 31
Proposed Architecture
[ADPLL]

30. • The advantage of using ADPLL + ring VCO:
– The JG is controlled through the ADPLL instead of
the SBCDR loop.
• The SBCDR BW is set to ~100 KHz for JTr
• The ADPLL BW is set to ~1 MHz for JG minimization
– In Addition to reduced JG, the multi-phase nature
of the recovered clock allows for its usage with the
TX serializer directly.
3/8/2015 Master Thesis defense 32
Proposed Architecture
[ADPLL]

31. • Single oscillator for full OC-192 transceiver.
3/8/2015 Master Thesis defense 33
Proposed Architecture
[ADPLL]

32. • ADPLL block diagram.
3/8/2015 Master Thesis defense 34
Proposed Architecture
[ADPLL]

33. • TDC
– PVT independent
gain : 1/20 UI
– No extra hardware
3/8/2015 Master Thesis defense 35
Proposed Architecture
[ADPLL]
Conventional [Staszewski et al. 2006]
Proposed

34. • Ring DCO
– 10 pseudo differential stage (20-phases)
– Required PN @ 1MHz offset -106 dBc/Hz
(assumed power consumption 25 mW, FOM ~ 160
[Hajimiri et al. 1999])
– FOM definition [Tang et al. 2000]
3/8/2015 Master Thesis defense 36
Proposed Architecture
[ADPLL]
𝑭𝑶𝑴 = 𝟏𝟎. 𝒍𝒐𝒈 𝟏𝟎
𝑭 𝒐𝒔𝒄
𝑭 𝒐𝒇𝒇
𝟐
𝟏
𝑷𝒐𝒘𝒆𝒓 𝑾𝒂𝒕𝒕
− 𝑷𝑵 𝒅𝑩𝒄/𝑯𝒛

35. • For conventional PLL CDRs this replaces
three oscillator [assumed FOM : LC 180, Ring 160]
– Power estimattion1,2
3/8/2015 Master Thesis defense 37
Proposed Architecture
[ADPLL]
CDR Cleanup-PLL CMU
Ring 30 mW NA [300 mW] NA [100 mW]
LC 0.3 mW 3 mW 1 mW
1. No power breakdown data available on prior ART
FOM numbers are typical assumed numbers
2. Total OC-192 FE including timing consumes > 1.02.0 W
[Henrickson et al. 2003, Werkeret al. 2004, Muthali et al. 2004]

36. • OSCDR limitation:
Circular nature of phase definition
– Previous cycle result needed for definition, No pipelining allowed
3/8/2015 Master Thesis defense 38
Proposed Architecture
[OSCDR]

37. • OSCDR limitation:
Circular nature of phase definition
– Previous cycle result needed for definition, No pipelining allowed
3/8/2015 Master Thesis defense 39
Proposed Architecture
[OSCDR]

38. • OSCDR limitation
– For interleaving complex averaging operation is
needed.
– This complex operation requires complex
mathematical hardware with limited speed
3/8/2015 Master Thesis defense 40
Proposed Architecture
[OSCDR]

39. • Proposed circular implementation
3/8/2015 Master Thesis defense 41
Proposed Architecture
[OSCDR]

40. • Extensive pipelining allowed
3/8/2015 Master Thesis defense 42
Proposed Architecture
[OSCDR]

41. • Simplified phase exclusion algorithm
3/8/2015 Master Thesis defense 43
Proposed Architecture
[OSCDR]

42. • Tow extra redundant algorithm for exceptions
3/8/2015 Master Thesis defense 44
Proposed Architecture
[OSCDR]

43. • Provide synchronization between OSCDR and
ADPLL
• Provides required attenuation to limit JTr BW
• Contains a programmable integrator
– Enabled during initial locking:
• Fast locking
• Type two loop no residual phase error
– Disabled for normal tracking
• In-band peaking < 0.1 dB
3/8/2015 Master Thesis defense 45
Proposed Architecture
[DLF]

44. • SBCDR transfer function
– Initial locking
3/8/2015 Master Thesis defense 46
Proposed Architecture
[DLF]

45. • SBCDR transfer function
– Continuous tracking
3/8/2015 Master Thesis defense 47
Proposed Architecture
[DLF]

46. TOC
3/8/2015 Master Thesis defense 48
CDR Introduction + OC-192 standard
Prior ART
Proposed Design
Modeling + Simulation

47. MODELING AND SIMULATION
RESULTS
Modeling + Simulation results
3/8/2015 Master Thesis defense 49

48. 3/8/2015 Master Thesis defense 50
Modelling and Simulation
(Model partioning)

49. 3/8/2015 Master Thesis defense 51
Modelling and Simulation
(Simulation time)
• Two main signals:
– 5X data sampling = 0.2 UI
[requires time step Ts < 0.02 UI]
– Clock jitter < 0.03 UIrms
[requires Ts < 0.003 UI]
• A single bit period requires > 333Ts !!!
• 1E8 bits requires 3.3E10 Ts

50. 3/8/2015 Master Thesis defense 52
Modelling and Simulation
(Simulation Time)
• CppSim double_interp signal type used for the clock
– The signal is binary signal [-1,1]
– During transition takes any
arbitrary value between [-1,1]
the value is a linear interpolation.
– Only four samples needed for a
clock cycle: Required Ts < 1 UI.

51. 3/8/2015 Master Thesis defense 53
Modelling and Simulation
(Simulation Time)
• Single phase + relative timing vector used for driving
the samplers

52. 3/8/2015 Master Thesis defense 54
Modelling and Simulation
(Simulation Time)
• The stimulus and channel model is collapsed into the
FE-samplers.
– The 20 data samples values
are calculated once every
single quarter rate
clock cycle
– Required Ts < 4 UI.

53. 3/8/2015 Master Thesis defense 55
Modelling and Simulation
(Simulation Time)
• Summary
– Required Ts < 1 UI, ~ 280X simulation speed enhancement
– For JTo simulation this is not enough:
• Multiple simulations are required for multiple jitter frequency
• At each specific frequency multiple simulation is needed to sweep
for the maximum tolerable Je
• Binary search is used to find this value
• A multi-threading engine is coded to simulate multiple frequencies
concurrently
– A Ts of ~ 0.8 UI is used with a simulation length of 1E8 UI

54. 3/8/2015 Master Thesis defense 56
Modelling and Simulation
(Results)
• Jitter Tolerance for scrambled data through a PRBS with
length 31-bit

55. 3/8/2015 Master Thesis defense 57
Modelling and Simulation
(Results)
• Jitter Transfer

56. 3/8/2015 Master Thesis defense 58
Modelling and Simulation
(Results)
• Jitter generation

57. 3/8/2015 Master Thesis defense 59
Modelling and Simulation
(Results)
• Transient response

58. 3/8/2015 Master Thesis defense 60
Modelling and Simulation
(Results)
• Transient response

59. 3/8/2015 Master Thesis defense 61
Modelling and Simulation
(Results)
• Summary
Specification Parameter (Unit) Value Simulation
FDATA GHz 10 10
JTo
F1 (Hz) A1 (UIPP) 10 2490 PASS
F2 (Hz) A2 (UIPP) 12.1 2490 PASS
F3 (kHz) A3 (UIPP) 2 15 PASS
F4 (kHz) A4 (UIPP) 20 1.5 PASS
F5 (kHz) A5 (UIPP) 400 1.5 PASS
F6 (MHz) A6 (UIPP) 4 0.15 PASS
F7 (MHz) A7 (UIPP) 80 0.15 PASS
JTr
P (dB) 0.1 0.0
FC (kHz) 120 <110
JG
Wide-band JG (UIRMS) 0.03 0.012
High-band JG (UIRMS) 0.01 0.007

60. 3/8/2015 Master Thesis defense 62
Conclusion
• The reduced phase exclusion algorithm of the OSCDR allows for
the usage of the CDR in Multi-Giga hertz links.
• The impeded JG cancellation loop (JG), allows for CDR usage in
synchronous metropolitan networks.
• The inherited JTo enhancement of the conventional SBCDR, again,
allows for CDR usage in synchronous metropolitan networks.
• The power penalty due to the usage of ring oscillator is reduced
through the architecture configuration. Thus, allows for removing all
on chip inductors.

61. 3/8/2015 Master Thesis defense 63
Refernces
[ITU-T G.783 2006] Characteristics of synchronous digital hierarchy (SDH) equipment functional
blocks: G.783, International Telecommunication Union, TELECOMMUNICATION
STANDARDIZATION SECTOR (ITU-T), 2006.
[Telec. GR-253 2000] Synchronous Optical Network (SONET) Transport Systems:GR-253-CORE, Issue
3, Telecordia Technologies., 2000.
[Scheytt et al. 1999] J. C. Scheytt, G. Hanke and U. Langmann, "A 0.155-, 0.622-, and 2.488-Gb/s
Automatic Bit-Rate Selecting Clock and Data Recovery IC for Bit-Rate Transparent
SDH Systems," JSSC, pp. 1935-1943, December 1999.
[Muthali et al. 2004] H. S. Muthali, T. P. Thomas and I. A. Young, "A CMOS 10-Gb/s SONET
Transceiver," JSSC, pp. 1026-1033, July 2004.
[Maillard et al. 2002] X. Maillard and M. Kuijk, "A 900-Mb/s CMOS Data Recovery DLL Using Half-
Frequency Clock," JSSC, pp. 711-715, June 2002.
[Rhee et al. 2003] W. Rhee, H. Ainspan, S. Rylov, A. Rylyakov and M. Beakes, "A lO-Gb/s CMOS
Clock and Data Recovery Circuit Using a Secondary Delay-Locked Loop," in CICC,
2003.
[Dalton et al. 2005] D. Dalton, K. Chai, E. Evans, M. Ferriss and D. Hitchcox, "A 12.5-Mb/s to 2.7-
Gb/s Continuous-Rate CDR With Automatic Frequency Acquisition and Data-Rate
Readback," JSSC, pp. 2713-2725, December 2005.

62. 3/8/2015 Master Thesis defense 64
Refernces
[Kreienkamp et al. 2003] R. Kreienkamp and U. Langmann, "A 10-Gbls CMOS Clock and Data Recovery
Circuit with an Analog Phase Interpolator," in CICC, 2003.
[Hanumolu et al 2008] P. Hanumolu, G.-Y. Wei and U.-K. Moon, "A Wide-Tracking Range Clock and
Data Recovery Circuit," JSSC, pp. 425-439, February 2008.
[Cao et al. 2002] J. Cao, M. Green, A. Momtaz, K. Vakilian, K.-C. Jen, M. Caresosa, X. Wang, W.-G.
Tan, Y. Cai, I. Fujimori and A. Hairapetian, "OC-192 Transmitter and Receiver in
Standard 0.18-um CMOS," JSSC, pp. 1768-1780, DECEMBER 2002.
[Henrickson et al. 2003] L. Henrickson, D. Shen, U. Nellore, A. Ellis, J. Oh, H. Wang, G. Capriglione, A.
Atesoglu, A. Yang, P. Wu, S. Quadri and D. Crosbie, "Low-Power Fully Integrated 10-
Gb/s SONET/SDH Transceiver in 0.13-um CMOS," JSSC, pp. 1595-1601, OCTOBER
2003.
[Werkeret al. 2004] H. Werker, S. Mechnig, C. Holuigue, C. Ebner, G. Mitteregger, E. Romani, F. Roger,
T. Blon, M. Moyal, M. Vena, A. Melodia, J. Fisher, G. d. Mercey and H. Geib, "A
10Gb/s SONET-Compliant CMOS Transceiver with Low Cross-Talk and Intrinsic
Jitter," in ISSCC, 2004.
[Kim et al. 2003] J. Kim and D.-K. Jeong, "Multi-Gigabit-Rate Clock and Data Recovery Based on
Blind Oversampling," MCOMM, pp. 68-74, 2003.
[Kolka et al. 2010] Z. Kolka and M. Kubicek, "Blind Oversampling Data Recovery with Low
Hardware Complexity," RADIO ENGINEERING, pp. 74-78, 2010.

63. 3/8/2015 Master Thesis defense 65
Refernces
[Ierssel et al.2007] M. v. Ierssel, A. Sheikholeslami, H. Tamura and W. W. Walker, "A 3.2 Gb/s CDR
Using Semi-Blind Oversampling to Achieve High Jitter Tolerance," JSSC, pp. 2224-
2234, October 2007.
[Staszewski et al. 2006] R. B. Staszewski, S. Vemulapall, P. Vallur, J. Wallberg and P. T. Balsara, "1.3 V 20
ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS," TCAS-II, pp.
220-224, MARCH 2006.
[Hajimiri et al. 1999] A. Hajimiri, S. Limotyrakis and Thomas H. Lee, "Jitter and Phase Noise in Ring
Oscillators," JSSC, pp. 790-804, JUNE 1999.
[Tang et al. 2000] J. van der Tang, D. Kasperkovit, “Oscillator design efficiency: a new figure of
merit for oscillator benchmarking” in ISCAS, 2000