This document proposes a multi-order harmonic generation architecture for millimeter-wave frequency synthesis. It uses a low-frequency PLL followed by multiple stages of frequency multiplication to generate wideband frequencies up to 40 GHz. A digital harmonic synthesis block and injection-locked LC oscillator generate the multiplied frequencies. Measurement results show locking to the 7th harmonic at 32 GHz with low phase noise. This architecture achieves wide tuning ranges for millimeter-wave applications using low-frequency PLL techniques.

1. Frequency Synthesizers and
Oscillator Architectures Based on
Multi-order Harmonic Generation
Mohammed M. Abdul-Latif,
Advisor: Dr. Edgar Sánchez-Sinencio
Analog and Mixed Signal Center,
Texas A&M University, College Station, TX

2. 08/28/15 2
Outline
 Introduction and Motivation
 A Wideband Millimeter-Wave Frequency
Synthesis Architecture using Multi-Order
Harmonic-Generation
 N-Push Cyclic Coupled Ring Oscillators
 An Adaptive Low-pass Filtering Technique for
Reference-Spur Reduction in Integer-N PLLs
 Conclusion

3. 08/28/15 3
Introduction
 Frequency Synthesizers or Clock generators are
used ubiquitously in most modern electronic
devices

4. 08/28/15 4
Introduction
 Wireless Systems need Local Oscillators (LO) to
down convert higher frequency signals to baseband
frequencies

5. 08/28/15 5
Introduction
Intel Sandy Bridge
Micro-architecture
 Computing Systems need clock generators to provide
timing clocks to the Central Processing Units (CPU)

6. 08/28/15 6
Introduction
Texas Instrument’s TMS320C62x DSP
 Digital Signal Processors also need frequency synthesizers
or Phase Locked Loops (PLLs) for timing

7. 08/28/15 7
Introduction
 Infra-structure devices/networks handle huge
amounts of data at very high speeds

8. 08/28/15 8
Introduction
 This high speed data passes
through PCBs, Ethernet or
optical fiber networks
 A PLL is needed to
synchronize this data

9. 08/28/15 9
Motivation
Frequency synthesizers are used in all modern
electronic devices.
Their performance is critical to future
development of these devices

10. 08/28/15 10
Motivation
 Performance of frequency synthesizer helps determine:
 Bandwidths available in wireless links
 Higher Frequencies  wider bandwidths  higher data rates
 Receiver or transmitter data rates in serial links
 Faster Infra-structure  more data rates
 CPUs/DSPs speeds in computing devices
 Faster computing  more functionality
 Form Factor and battery life
 Less power and area  smaller devices and longer battery life
 Number of data and communication standards integrated on a
single chip
 Wideband frequency synthesizers  more integration

11. 08/28/15 11
Motivation
 This work proposes circuit architectures and designs which
improve the following performance metrics of frequency
synthesizers:
 Oscillation frequency
 Tuning Range
 Phase noise

12. 08/28/15 12
Overview
 We propose a new architecture to frequency synthesizers:
A PLL combined with a frequency multiplier
 We propose a new VCO to be used within the PLL
 We propose a technique to improve PLL performance
 Most famous frequency synthesizer: Phase Locked Loops

13. 08/28/15 13
Overview
 Main theme of the proposed architectures:
Frequency multiplication ≡ Harmonic Generation
Low Frequency Input
 Easier to implement
 Lower Noise
 Narrowband
 Low frequency
 Higher Frequency
 Wideband
 Noise degrades

14. 08/28/15 14
Overview
Project 1 Project 2 Project 3
Goals
• Wide tuning range
• mm-wave freq.
• Wide tuning range
• mm-wave freq.
• Low phase noise
• Low reference
spur
Architecture
Multi-order Multi-
Step Harmonic
Generation
Multi-order
Harmonic Generation
Integer-N charge
pump based PLL
Oscillator LC based oscillator
Coupled Ring
Oscillator
LC –based Oscillator
Implementation
Digital Harmonic
Synthesis and
N-Push
Osc.1: N-Push /M-Push
Osc.2: N-Push
Adaptive Low pass
filtering
Usage Used after a PLL Used within a PLL Used within a PLL

15. 08/28/15 15
Outline
 Introduction and Motivation
 A Wideband Millimeter-Wave Frequency
Synthesis Architecture using Multi-Order
Harmonic-Generation
 N-Push Cyclic Coupled Ring Oscillators
 An Adaptive Low-pass Filtering Technique for
Spur Reduction in Integer-N PLLs
 Conclusion

16. A Multi-Order Harmonic-
Generation Millimeter Wave
Frequency Synthesizer Architecture

17. 08/28/15 17
Motivation
 This frequency synthesizer is required to provide
 Frequency tones for a large frequency tuning range up
to millimeter-wave (mm-wave) frequencies
 Fine channel frequency resolution
 Adequate phase noise performance
 Minimum power consumption
 Application examples
 WiMAX (10-66 GHz) and (2-11GHz) provide
broadband links for voice, video, data, mobile
 WIGIG (57-66 GHz) provides wireless data, display
and audio applications with data rates of 7Gbps

18. 08/28/15 18
Motivation
 Conventional mm-wave PLL problems:
1. Wideband VCOs have a large and varying frequency
sensitivity (KVCO) which:
- Degrades its phase noise.
- Degrades spur suppression.
• Complicates PLL loop design.
2. mm-wave dividers are usually implemented using
injection-locked architectures
1. suffer from narrow band characteristics
2. high power consumption
3. Mismatches between the VCO and the divider tuning
characteristics can reduce the usable portion of the
VCO tuning range significantly

19. 08/28/15 19
Proposed Solution
 Use a relatively Low frequency PLL to synthesize a
scaled down version of the required mm-wave
frequencies
 Well known implementation
 Lower phase noise
 Reasonable tuning range
 Frequency multiplication/Harmonic generation using
different factors 
 Higher operating frequencies
 Wider bandwidths simultaneously
e.g. 1 – 1.25 GHz (tuning range ~ 25 %) x 24 or 30
 24 –37.5 GHz with a tuning range of 45 %.

20. 08/28/15 20
Proposed Solution
 Multi-order Multi-step Harmonic Generation (Frequency
Multiplication)

21. 08/28/15 21
Architecture of Proposed Frequency Synthesizer
Low PLL
Frequency
DHSB N-Phase IL- VCO
Variable N-Push
frequency Multiplier
Output
1 – 1.43 GHz
(TR~35%)
5th
harmonic 5 – 7 GHz
x 1  5 – 10 GHz
x 2  10 – 20 GHz
x 4  20 – 40 GHz
5 – 40 GHz
(TR~155%)
7th
harmonic
7 – 10 GHz

22. 08/28/15 22
Harmonic Generation – N-Push
fo, 2fo, 3fo,..
fo, 2fo, 3fo, …
Oscillator 2
Oscillator 1
fo, 2fo, 3fo,..
∑
0o
φ =
Push-Push
180o
φ =
1 1 2
2 1 2
1 2 2
cos( ) cos(2
cos( ) cos(2( )
2 cos(2
S A t A t
S A t A t
S S A t
ω ω
ω π ω π
ω
= + )
= + + + )
+ = )

23. 08/28/15 23
Harmonic Generation – N-Push
fo, 2fo, 3fo,..
fo, 2fo, 3fo, …..
Oscillator 3
Oscillator 1
fo, 2fo, 3fo,..
Oscillator 2
fo, 2fo, 3fo,..
∑
Triple-Push
0o
φ =
120o
φ =
240o
φ =

24. 08/28/15 24
Harmonic Generation – N-Push
N Phase shifts Preserved
Harmonics
Cancelled
Harmonics
Output
type
2 0o
,180o
2, 4, 6, … 1, 3, 5, … Single
2 0o
, 90o
, 180o
, 270o
2, 4, 6, … 1, 3, 5, … Diff.
2 (0o
, 90o
, 180o
,270o
),
(45o
, 135o
, 225o
, 315o
) 2, 4, 6, … 1, 3, 5, … I, Q
3 0o
,120o
, 240o
3, 6, 9, … 1, 2, 4, 5, … Single
3 0o
, 60o
, 120o
, 180o
240o
,
300o 3, 6, 9, … 1, 2, 4, 5, … Diff.
4 0o
, 90o
, 180o
, 270o
4, 8, 12, … 1, 2, 3, 5, 6, 7,
… Single
5 0o
, 72o
, 144o
, 216o
, 288o
5, 10, 15, … 1, 2, 3, 4, 6, 7, 8,
9, … Single

25. 08/28/15 25
Digital Harmonic Synthesis Block

26. 08/28/15 26
Digital Harmonic Synthesis Block

27. 08/28/15 27
DHSB
1 3 5 7 9 11 13
-60
-50
-40
-30
-20
-10
0
Frequency (GHz)
DHSBOutput(dB)
1 3 5 7 9 11 13
-60
-50
-40
-30
-20
-10
Frequency (GHz)
DHSBOutput(dB)
Simulation results of the output signal spectra from the DHSB
Frequency (GHz)

28. 08/28/15 28
Injection Locked I-Q LC Oscillator

29. 08/28/15 29
Injection Locking/Coupling

30. 08/28/15 300 20 40 60 80 100
4
5
6
7
8
9
10
11
Code Number
VCOOutputFrequency(GHz)
Low Frequency setting
High Frequency setting
Injection Locked I-Q LC Oscillator

31. 08/28/15 31
N-Push Frequency Multiplier

32. 08/28/15 32
N-Push Frequency Multiplier
0 60 120 180 240 300 360
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Conduction Angle (degrees)
FourierCoefficient(mA)
Theory
Simulation
0 0.2 0.4 0.6 0.8 1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
DC Bias (V)
0 60 120 180 240 300 360
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Conduction Angle (degrees)
FourierCoefficient(mA)
Theory
Simulation
0 0.2 0.4 0.6 0.8 1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
DC Bias (V)
Harmonic content versus
conduction angle / input bias point
2nd
Harmonic
4th
Harmonic

33. 08/28/15 33
Measurement Results
2.25 mm
1.15 mm
N-Push
Frequency
multiplier
IL-QVCO Output
Amplifier/Buffer
Digital Harmonic
Synthesis Block
 Fabricated in IBM 90nm CMOS
 Active area 0.6mm2
Chip Micrograph

34. 08/28/15 34
Measurement Results
5 10 15 20 25 30
-120
-100
-80
-60
-40
-20
0
Amplitude(dBm)
5 10 15 20 25 30
-120
-100
-80
-60
-40
-20
0
Frequency (GHz)
PhaseNoise(dBc/Hz)
• Locking to 7th
harmonic
• All lower harmonic are less
than 39dBc
Amplitude
Phase noise @ 1 MHz

35. 08/28/15 35
Measurement Results
Measured output spectrum
26GHz
13GHz
6.5GHz
Output tone at 32GHz
Phase noise plots at
6.5, 13 and 26 GHz

36. 08/28/15 36
Performance Comparison

37. 08/28/15 37
References
1. O. Richard, A. Siligaris, F. Badets, C. Dehos, C. Dufis, P. Busson, P. Vincent, D.
Belot, P. Urard, "A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for
wireless HD applications," ISSCC Dig. Tech. Papers, Feb. 2010, pp. 252-253.
2. S.-A. Yu, Y. Baeyens, J. Weiner, U.-V. Koc, M. Rambaud, F.-R. Liao, Y.-K. Chen,
P. Kinget, "A single-chip 0.125–26GHz signal source in 0.18um SiGe
BiCMOS," IEEE RFIC Symp. Dig., Jun. 2009 pp.427-430.
3. W. L. Chan, J. R. Long, J. J. Pekarik, "A 56-to-65GHz Injection-Locked Frequency
Tripler with Quadrature Outputs in 90nm CMOS," ISSCC Dig. Tech. Papers, Feb.
2008, pp.480-629.
4. S. D. Toso, A. Bevilacqua, M. Tiebout, S. Marsili, C. Sandner, A. Gerosa, A.
Neviani, "UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic
Injection Locking," ISSCC Dig. Tech. Papers, Feb. 2008, pp.124-601.
5. S. A. Osmany, F. Herzel, J. C. Scheytt, "An Integrated 0.6–4.6 GHz, 5–7 GHz, 10–14
GHz, and 20–28 GHz Frequency Synthesizer for Software-Defined Radio
Applications," IEEE J. of Solid-State Circuits, vol.45, no.9, pp.1657-1668, Sept.
2010.
6. T.-Y. Lu, W.-Z. Chen, "A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with
Spurs Reduction for MB-OFDM UWB System," ISSCC Dig. Tech. Papers, Feb.
2008, pp.126-601.
7. S.-A. Yu, P. Kinget, "A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm
CMOS," ISSCC Dig. Tech. Papers, Feb. 2007, pp.304-604.

38. 08/28/15 38
Outline
 Introduction and Motivation
 A Wideband Millimeter-Wave Frequency
Synthesis Architecture using Multi-Order
Harmonic-Generation
 N-Push Cyclic Coupled Ring Oscillators
 An Adaptive Low-pass Filtering Technique for
Spur Reduction in Integer-N PLLs
 Conclusion

39. 08/28/15 39
Overview
Project 1 Project 2 Project 3
Goals
• Wide tuning range
• mm-wave freq.
• Wide tuning range
• mm-wave freq.
• Low phase noise
• Low reference
spur
Architecture
Multi-order Multi-
Step Harmonic
Generation
Multi-order
Harmonic Generation
Integer-N charge
pump based PLL
Oscillator LC based oscillator
Coupled Ring
Oscillator
LC –based Oscillator
Implementation
Digital Harmonic
Synthesis and
N-Push
Osc.1: N-Push /M-Push
Osc.2: N-Push
Adaptive Low pass
filtering
Usage Used after a PLL Used within a PLL Used within a PLL

40. N-Push Cyclic Coupled Ring
Oscillator

41. 08/28/15 41
Motivation
 The oscillator is required to
 Provide wide frequency tuning ranges
 Lower phase noise performance at mm-wave frequency
 Provide Multi-phase outputs used in
 Image Reject receivers
 Time interleaved data sampling
 Work within the conventional PLL structure

42. 08/28/15 42
Ring Oscillators
We propose to use ring oscillators
 Advantages:
 Compatible with the low cost digital CMOS processes.
 Scalable with new technologies promising higher
frequencies.
 Ring oscillators naturally provide different phase shifts
 We propose to combine ring oscillators with N-Push
frequency multiplication
 Advantage:
 Achieve higher frequency of operation

43. 08/28/15 43
Coupled Ring Oscillators
 We need Multi-order Harmonic Generation
 To achieve wide tuning range
 But needs two sets of phases
 We propose to use coupled ring oscillators to
provide a second set of phases
 Phase noise is improved as a bi-product of using
coupled ring oscillators

44. 08/28/15 44
Cyclic Coupled Ring Oscillator
 M coupled ring oscillators
 Each Ring Oscillator has
N-Delay stages
 Coupling stages Dci
 MxN matirx

45. 08/28/15 45
Cyclic Coupled Ring Oscillator
 M Horizontal Oscillators
 N Vertical Oscillators
 k times smaller:
gmH = k gmV
 Each oscillator is injection-
locked to the previous using
progressive multi-phase
injection
 This implementation used
CMOS inverters as the delay
cells

46. 08/28/15 46
Cyclic Coupled Ring Oscillator
 M Horizontal Oscillators
 N Vertical Oscillators
 k times smaller:
gmH= k gmV
 Each oscillator is injection-
locked to the previous using
progressive multi-phase
injection
 This implementation used
CMOS inverters as the delay
cells

47. 08/28/15 47
Circuit Model
 Each transconductor is modeled as an
ideal hard limiter with an RC load
21 22 12 2222
21 22 12 22
sin( ) sin( )1
cos( ) cos( )
osc cp
osc cp
I Id
dt RC I I
θ θ θ θθ
θ θ θ θ
− + −
=
− + −

48. 08/28/15 48
Oscillation Frequency
 Coupling factor
 If all oscillators lock to the same frequency ω0 and
given the symmetry of the system
 Horizontal phase shift
 Vertical phase shift
 Hence,
 Compare to a single RO,
/cp osck I I=
1 0φ θ θ φ−= − =j ij ij
1 0ψ θ θ ψ−= − =i i j ij
0 0
0 0
sin( ) sin( )1
cos( ) cos( )
φ ψ
ω
φ ψ
+
=
+
osc
k
RC k
,single 0
1
tan( )ω φ=osc
RC

49. 08/28/15 49
Phase Shifts
 For the horizontal oscillators (strong oscillators)

 For the vertical oscillators (weak oscillators)

N
π
φ π= +
2
2
( ) where
2
n
M
n M n
M
ψ π
π
ψ
Μ =
= > >
e.g. N=3, M=5

50. 08/28/15 50
Phase Noise
 Circuit model
[ ]
2 2
22 41
1 2
2 2 2 21 2 3 2 1
1 1 2 1 2 2
( ) 8 ( ) 1
( )
2 det( )
m
m N x M M
osc
M M M M
S kT a b
R I b M M
M I M M I M M I M I
θ ω
ω
− − − −
+
= =
+
 × + + + +  
L
L
21 22 12 22 2222
21 22 12 22 22
sin( ) sin( ) sin( )1
cos( ) cos( ) cos( )
osc inj n n
osc inj n n
I I id
dt RC I I i
θ θ θ θ θ θθ
θ θ θ θ θ θ
− + − − −
=
− + − − −

51. 08/28/15 51
Phase Noise
Calculated phase noise plot for the
case of 3x3 CCRO with k=0.1
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-180
-160
-140
-120
-100
-80
-60
-40
Offset Frequency (Hz)
PhaseNoise(dBc/Hz)
10
4
10
5
10
6
10
7
10
8
10
9
10
10
-5
-4
-3
-2
-1
0
1
Offset Frequency (Hz)PhaseNoiseImprovement(dB)
k=0.2
k=0.1
k=0.01
Calculated phase noise difference for
the case of 3x3 CCRO and for
k=0.01, 0.1 and 0.2
 Improvement of 10log10(M)is observed .. Why?
 Improvement is only below a certain bandwidth .. Why?

52. 08/28/15 52
Phase Noise
D. Shaeffer and S. Kudszus
JSSC, July 2003.
 A coupled system has more inertia than a single
system and hence is more resistant to noise.
 Power is increased M2
times
and random noise signals are
increased M times
Phase noise improves
by M times or 10 log10(M) dB

53. 08/28/15 53
Phase Noise
 A perfectly coupled system (k =1) ≡ single oscillator
with M times more power consumption
 All perturbations are corrected
 Phase noise improved for all frequency offsets
 For a weakly coupled system (k <<1)
 Only slow perturbations are corrected, system cannot
respond to fast perturbations
 Phase Noise Improvement is only below a certain
bandwidth

54. 08/28/15 54
N-Push CCRO
N-Push CCROs have several advantages over stand
alone ring oscillators.
 Lower the phase noise by 1/M due to coupling.
 Make use of the multiple phase sets of the CCRO
 The core ring oscillator runs at a lower frequency
 use non-minimum length
 decrease the associated flicker noise
 Decrease phase noise further

55. 08/28/15 55
N-Push CCRO
 We propose two oscillators:
1. A Wideband N-Push/M-Push CCRO which achieves:
1. Wide tuning range
2. Low phase noise
3. Works within a PLL
2. A mm-wave N-Push CCRO which achieves:
1. Mm-wave oscillation frequency
2. Low phase noise
3. Multi-phase output
4. Works within a PLL

56. 08/28/15 56
Wideband N-Push/M-Push CCRO
 Applying N-Push and M-push simultaneously to the two
dimensions of the CCRO provides two output frequency
ranges
 achieve a wideband output using a core oscillator with a
smaller frequency output range.

57. 08/28/15 57
Wideband N-Push/M-Push CCRO
Chip micrograph

58. 08/28/15 58
Measurement Results
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
3
5
7
9
11
13
Frequency(GHz)
VDD (V)
3rd Harmonic
5th Harmonic
2 4 6 8 10 12 14
-106
-105
-104
-103
-102
-101
-100
Frequency (GHz)
PhaseNoise(dBc/Hz)
3rd Harmonic
5th Harmonic
Frequency tuning curve Phase noise at 1MHz offset

59. 08/28/15 59
Measurement Results
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
-50
-40
-30
-20
-10
0
10
VDD (V)
Amplitude(dBm)
3rd Harmonic
2nd Harmonic
Fundamental
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
-60
-50
-40
-30
-20
-10
0
10
VDD (V)
Amplitude(dBm)
5th Harmonic
3rd Harmonic
Fundamental
(a) N-Push output (b) M-Push output
Amplitudes of the fundamental tones and harmonics

60. 08/28/15 60
Measurement Results
3 4 5 6 7 8 9
-108
-106
-104
-102
-100
-98
-96
-94
-92
Frequency (GHz)
PhaseNoise(dBc/Hz)
N-Push CCRO
N-Push Single RO
Phase noise improvement by 8dB ~ 10log(5) due to the
use of 5 coupling ring oscillators

61. 08/28/15 61
Measurement Results
Frequency
(GHz)
TR (%)
Phase noise @ 1MHz
(dBc/Hz)
Power
(mW)
Technology
(CMOS)
FOMT
This
Work
1 – 2.56
3.16 – 12.8
163 -105.5 @ 7.7GHz 13-200 90nm
-184.4 to
-190.4
[1] 1 – 9.4 161.5 -112.3 @ 6GHz * 7.4 130nm -183.33
[2] 0.8 – 10 170.37 -90 @ 6.4GHz 6 120nm -162.97
[3] 1.82 – 10.18 139.4 -88.4 @ 5.65GHz 5 130nm -179.34
[4] 2.5 – 9 113 -85 @ 5GHz 135 180nm -158.7
[5] 3 – 11 114 -88 @ 5GHz 85 180nm -163.8
* Phase noise at 10MHz offset
0
( ) 20log( ) 10log( )
10 1
dc
T
f PTR
FOM f
f mW
= ∆ − +
∆
L

62. 08/28/15 62
References
1. C. Li, J. Lin, "A 1–9GHz Linear-Wide-Tuning-Range Quadrature Ring
Oscillator in 130 nm CMOS for Non-Contact Vital Sign Radar
Application," IEEE Microwave Wireless Compon. Lett., vol.20, no.1, pp.34-
36, Jan. 2010.
2. E. Tatschl-Unterberger, S. Cyrusian, M. Ruegg, "A 2.5GHz phase-switching
PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for
improved jitter/mismatch," IEEE Int. Circuits Syst. Symp., May 2005, pp.
5453- 5456.
3. B. Fahs, W.Y. Ali-Ahmad, P. Gamand, "A Two-Stage Ring Oscillator in
0.13- mm CMOS for UWB Impulse Radio," IEEE Trans. Microwave.
Theory and Tech, vol.57, no.5, pp.1074-1082, May 2009.
4. A. Rezayee and K. Martin, “A coupled two-stage ring oscillator,” in IEEE
Midwest Circuits Syst. Symp., Aug. 2001, pp. 878–881.
5. A. Rezayee and K. Martin, “A 10-Gb/s clock recovery circuit with linear
phase detector and coupled two-stage ring oscillator,” in IEEE Eur. Solid-
State Circuits Conf., Sep. 2002, pp. 419–422.

63. 08/28/15 63
mm-wave N-Push CCRO
 Applying the N-push technique to each of the M sets of N
signals can also provide a multi-phase mm-wave output.
Chip micrograph

64. 08/28/15 64
Measurement Results
Frequency tuning curve Lower order harmonics
0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
5
10
15
20
25
VDD (V)
FRequency(GHz)
N-Push CCRO
Single RO
0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
-50
-45
-40
-35
-30
-25
-20
-15
-10
VDD (V)
HarmonicRejction(dB)
4th Harmonic
3rd Harmonic
2nd Harmonic
Fundamental
Proposed osc.: 13-25GHz
Reference osc.: 7.25-15.3GHz
Rejection > 35dB
 Reference oscillator is 3 stage RO

65. 08/28/15 65
Measurement Results
4 7 10 13 16 19 22 25
-100
-95
-90
-85
-80
-75
-70
Frequency (GHz)
PhaseNoise(dBc/Hz)
N-Push CCRO
Single RO
0.7 0.8 0.9 1 1.1 1.2 1.3 1.4
-165
-160
-155
-150
-145
-140
-135
VDD (V)
FigureofMerit(dBc/Hz)
N-Push CCRO
Single RO
Phase noise
Improvement = 10 – 20dB
FOM noise
Improvement = 8.7-20.4dB
0
( ) 20log( ) 10log( )
1
dcf P
FOM f
f mW
= ∆ − +
∆
L
 Comparison with a reference 3 stage ring oscillator

66. 08/28/15 66
Measurement Results
Frequency
Range
(GHz)
Tuning
Range
(%)
Phase noise @
1MHz (dBc/Hz)
Power
consumption
(mW)
Area
(mm2
)
Technology
fT
(GHz) FOM
This
Work
13-25 63.16% -96.11 @ 25GHz 37-257 0.1350 90nm/140
-159.2 –
-161.8
[1]
28.36-
31.96
11.94 -85.3 @ 31.96GHz 87 0.0108
SiGe
-HBT/120
-156
[2] 22.5-25.5 10.53 -87 @ 25GHz 240 0.0225 SiGe/45 -151.89
[3]
18.33 –
21.19
14.47
-83.33 @ 21.19
GHz
152 0.0180
SiGe- HBT /
120
-148.03
[4] 13.75-21.5 43.97 -90 @ 18.69GHz 130 0.1972
InP – HBT /
100
-154.29
[5]
0.1-65.8 199.4 -86 @ 25GHz 1.2-26.4 0.0168
90nm CMOS
/ 110
-160
0.2-34 197.66 -69.2 @ 34GHz 2-70 0.0247
0.13µm
CMOS / 98
-141.4
[6] 18.5-25 29.89 -85 @ 24.3GHz 105.6 0.1472
0.12µm SiGe
BiCMOS /
200
-152.7

67. 08/28/15 67
References
1. Wei-Min Lance Kuo; Cressler, J.D.; Chen, Y.-J.E.; Joseph, A.J.; , "An inductorless
Ka-band SiGe HBT ring oscillator," Microwave and Wireless Components Letters,
IEEE , vol.15, no.10, pp. 682- 684, Oct. 2005.
2. N. Saniei, H. Djahanshahi, and C. A. T. Salama, “25 GHz inductorless VCO in a 45
GHz SiGe technology,” in IEEE RFIC Symp. Dig., 2003, pp. 269–272.
3. W.-M. L.Kuo, J. D. Cressler,Y.-J. E. Chen, and A. J. Joseph, “Acompact 21 GHz
inductorless differential quadrature ring oscillator implemented in SiGe HBT
technology,” Mater. Sci. Semicond. Process., vol. 8, pp.445–449, Feb. 2005.
4. H. Djahanshahi, N. Saniei, S. P. Voinigescu, M. C. Maliepaard, and C. A. T. Salama,
“A 20-GHz InP-HBT voltage-controlled oscillator with wide frequency tuning
range,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 9, pp. 1566–1572, Sep. 2001.
5. Chung-Chun Chen; Chao-Chieh Li; Bo-Jr Huang; Kun-You Lin; Hen-Wai Tsao; Huei
Wang; , "Ring-Based Triple-Push VCOs With Wide Continuous Tuning
Ranges," Microwave Theory and Techniques, IEEE Transactions on , vol.57, no.9,
pp.2173-2183, Sept. 2009
6. Kodkani, R.M.; Larson, L.E.; , "A 25 GHz quadrature voltage controlled ring
oscillator in 0.12/spl mu/m SiGe HBT," Silicon Monolithic Integrated Circuits in RF
Systems, 2006. Digest of Papers. 2006 Topical Meeting on , vol., no., pp.4 pp., 18-20
Jan. 2006

68. 08/28/15 68
Outline
 Introduction and Motivation
 A Wideband Millimeter-Wave Frequency
Synthesis Architecture using Multi-Order
Harmonic-Generation
 N-Push Cyclic Coupled Ring Oscillators
 An Adaptive Low-pass Filtering Technique for
Spur Reduction in Integer-N PLLs
 Conclusion

69. 08/28/15 69
Overview
Project 1 Project 2 Project 3
Goals
• Wide tuning range
• mm-wave freq.
• Wide tuning range
• mm-wave freq.
• Low phase noise
• Low reference
spur
Architecture
Multi-order Multi-
Step Harmonic
Generation
Multi-order
Harmonic Generation
Integer-N charge
pump based PLL
Oscillator LC based oscillator
Coupled Ring
Oscillator
LC –based Oscillator
Implementation
Digital Harmonic
Synthesis and
N-Push
Osc.1: N-Push /M-Push
Osc.2: N-Push
Adaptive Low pass
filtering
Usage Used after a PLL Used within a PLL Used within a PLL

70. An Adaptive Low-pass Filtering
Technique for Spur Reduction in
Integer-N PLLs

71. 08/28/15 71
Spurious Tone sources in Integer-N FS
 Non-ideal effects in PFD and CP
 Periodic component at ωREF appears at VCO control input
 Appears as a tone at an offset frequency ωREF from the
carrier when the loop is locked
 Spur Amplitude
 Minimize spurs through
 Decreasing VCO gain
 Increasing ωREF
 Minimize ai
,
2
VCO i
sp i
REF
K a
A
iω
=
Type II third order charge pump
based integer- N PLL

72. 08/28/15 72
 Spur suppression is
improved by adding poles
 Additional poles lead to
 Degraded phase margin
 Less stability
 Increased overshoot (ringing)
 Increased settling time
Effect of Higher-order Loop Filter
(a) (b)
10
3
10
4
10
5
10
6
10
7
10
8
-220
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
Magnitude(dB)
Bode Diagram
Frequency (Hz)
Improvement of
Spur suppression
ωc ωSP
(a)
(b)
ωPL

73. 08/28/15 73
Proposed Structure
LF
PFDRef
Lock
Detector
RF
%N
CP VCOLPF
LCK
 LPF is adaptively added after loop is locked
 Single loop structure
 Loop design procedure is the same with a conventional
PLL
 Spur suppression is improved with LPF

74. 08/28/15 74
Building Block (Adaptive LPF)
LCK LCK
BUF BUF
BUF
VCP V1 V2
V1
’
V2
’
LCK
LCK
 When LCK is high, a buffered 2nd
-order LPF is enabled
 When LCK is low, V1 and V2 follow VCP
 V1
’
and V2
’
follow VCP to minimize a glitch on V1 and V2
when LCK goes high due to charge sharing

75. 08/28/15 75
Chip Micrograph

76. 08/28/15 76
Measurement Results (Spur suppression)

77. 08/28/15 77
Measurement Results (Settling time)

78. 08/28/15 78
Measurement Results (Phase Noise)

79. 08/28/15 79
Results Summary

80. 08/28/15 80
Outline
 Introduction and Motivation
 A Wideband Millimeter-Wave Frequency
Synthesis Architecture using Multi-Order
Harmonic-Generation
 N-Push Cyclic Coupled Ring Oscillators
 An Adaptive Low-pass Filtering Technique for
Spur Reduction in Integer-N PLLs
 Conclusion

81. 08/28/15 81
Conclusion
 A new architecture for generating wideband mm-
wave frequency synthesizers is presented
 New N-Push cyclic coupled ring oscillators are
presented
 Analysis of each architecture and its phase noise
performance is shown
 A low reference-spur integer-N PLL is presented
 Measurement results show the superior
performance of the proposed circuits

82. 08/28/15 82
Publications
 Mohammed M. Abdul-Latif, Mohamed M. Elsayed and Edgar Sánchez-
Sinencio, “A Wideband Millimeter-Wave Frequency Synthesis Architecture
using Multi-Order Harmonic-Synthesis and Variable N-Push Frequency
Multiplication” IEEE J. Solid-State Circuit., vol.46, no.6, pp.1265-1283, June
2011
 Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio, “A 3.16 – 12.8 GHz
Low Phase Noise N-Push/M-Push Cyclic Coupled Ring Oscillator”, in IEEE
RFIC Symp. Dig., 2011, pp. 405-408
 Mohamed Elsayed, Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio, “A
Spur-Frequency-Boosting PLL with a -74 dBc Reference-Spur Rejection in
90nm Digital CMOS”, in IEEE RFIC Symp. Dig., 2011, pp. 521-524
 Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio, “N-Push Cyclic-
Coupled Ring Oscillators: A Study”, prepared for submission to IEEE J. Solid-
State Circuit.
 Mohamed Elsayed, Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio, “A
Spur-Frequency-Boosting PLL with a -74 dBc Reference-Spur Rejection in
90nm Digital CMOS”, under preparation for IEEE J. Solid-State Circuit.

83. 08/28/15 83
Thank You!