1. A FAST CRYPTOGRAPHY PIPELINED
HARDWARE DEVELOPED IN FPGA WITH
VHDL
KOTTAM KRUNAKARA REDDY INSTITUTE OF TECHNOLOGY
PRESENTED BY
K.KALPANA
B.DURGA PRASAD
L.SHIVA KRISHNA
B.HARI KRISHNA YADAV

2. CONTENTS
• ABSTRACT
• INTRODUCTION
• AES
• ENCRYPTION BLOCK DIAGRAM
• ARCHITECTURE OF AES
• ADVANTAGES
• DISADVANTAGES
• APPLICATIONS
• CONCLUSION
• FUTURE SCOPE

3. ABSTRACT
• Main objective :
The main objective of the project is to increase the speed of
encryption and decryption by using pipelined hardware
• Pipelined hardware cryptography was used to improve performance in
order to achieve higher throughput and greater parallelism
• By using this we can easily reconfigure AES algorithm to 128,196 or 256
bit keys

4. What is FPGA and why ?
• FPGA stands for field programmable gate array
• FPGA’s are semiconductor devices that are based around a
matrix of configurable logic blocks connected via
programmable inter connects
• Field Programmable Gate Arrays (FPGAs) offer a quicker,
more customizable solution

5. What is pipelined hardware and parallelism?
• Pipelining increases the number of instructions that can be
processed at once
• In parallelism large task originates as a set of independent
programs and these can simply be executed on different
processors

6. INTRODUCTION
• Cryptography is a form of secret writing it is developed in two
standards
1.DES-data encryption standard
2.AES-advanced encryption standard
• Hardware based cryptography is more secure compared to
software based cryptography

7. • The algorithm was implemented using Xilinx spartan-3 and
Xilinx vertex-5 FPGA’s
• When implemented using these Xilinx spartan-3 is 50% faster
than others
• The transformations of both Encryptions and Decryption are
simulated using an iterative design approach in order to
minimize the hardware consumption

8. AES-Advanced encryption standard
• AES is also called as RIJNDAEL algorithm,developed to
replace unsafe DES and low triple DES
• The AES algorithm is a symmetric block cipher that can
encrypt (encipher) and decrypt (decipher) information
• AES has a fixed block size of 128 bits and a key size of 128,
192 or 256 bits

9. • AES operates on a 4 4 array of bytes, termed the state.
• For encryption, each round of AES (except the last round)
consists of four phases
1.Subbytes
2.Shift rows
3.Mix columns
4.Addround key
• For decryption algorithm will use respective inverse operations

10. SubBytes –
A non-linear substitution step where each byte is
replaced with another according to a lookup table (known as S
Box).

11. • ShiftRows –
A transposition step where each row of the state
is shifted cyclically a certain number of steps.

12. • MixColumns –
A mixing operation which operates on the columns
of the state, combining the four bytes in each column using a
linear transformation.
• AddRoundKey –
Each byte of the state is combined with the round
key; each round key is derived from the cipher key using a key
schedule.

13. • Key Expansion operation consists of three operations.
1.RotWord
2.SubWord
3.XOR operations

14. Block diagram of I/O of encryption

15. Block diagram of Encryption

16. Architecture diagram of AES

17. • There are three main blocks in AES architecture.
They are
1.Key expansion
2.Encryption
3.Decryption
• The signals inside hardware are buses used to
transfer the data between the blocks according to aes
mode selection

18. Advantages
• High Performance
• Time to market
• Reprogrammable
• Reconfigurable
• Long term maintenance

19. Disadvantages
• More expensive
• Power consumption is more

21. FUTURE SCOPE
• Micro electronics intends to use this work as part of larger
projects such as smart metering in power systems and
cryptography interface in data communication