Presentation by Larry Zu, Sarcina

1. Consume. Collaborate. Contribute.
PoC Physical Design Elements
1- Multi-Chiplet Package Substrate: (Larry to describe the package design)
• Will be an 8 Layer flip chip ball grid array (FCBGA).
• Will include chiplets, sugar cube optical/electrical network connectors, and decoupling caps
• Long pole in the schedule
2- An Early Software Development Vehicle – PoC Mock Up PCB
• Under discussion and needs sponsorship
• Will speed up the development by decoupling software from hardware.
• Use equivalent chips to build a PCB based system for software and test development

2. sarcinatech.com
All Rights Reserved
© 2019 Sarcina Technology LLCSarcina Confidential & Proprietary
March 27, 2019
Sarcina Service
To ODSA PoC Project
ODSA
PoC

3. sarcinatech.com
All Rights Reserved
© 2019 Sarcina Technology LLCSarcina Confidential & Proprietary
Tasks
ž Package design with ODSA members’ chiplets + O/E cables
ž Package PI & SI model extraction and analysis
ž PI & SI Channel Simulation with chip-package-PCB (skip?)
ž Thermal simulation (may skip)
ž Substrate fabrication
ž Package assembly
ž Final test (may skip. Tested on a line card or eval board)
ž Submit a report to ODSA
3

4. sarcinatech.com
All Rights Reserved
© 2019 Sarcina Technology LLCSarcina Confidential & Proprietary
Schedule For Packaging
ž Assembly can be reduced to 2 weeks if pay 3X quick turn charge
ž DFM review time with substrate/assembly suppliers can’t be reduced
ž Fabricate a 3-2-3 8L substrate. If 5-2-5, may increase to 12 weeks
4
Task Week -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10
Wafer fabrication Wafer fabrication
Silicon tape out
1st silicon chip ship out to Customer
Package prototyping assembly Assembly
Package substrate fabrication Substrate fabrication
Package tape out
Package tape out review with Customer
Package DFM tape out review DFM review
Electrical simulation for PI/SI Electrical Simulation
Package Design & Layout Package Design
Customer delivers final netlist (100%) 100%
Customer sends DDR4 IBIS/PCB/MEM Eye
Customer sends SerDes IBIS-AMI/PCB Eye
Customer delivers initial netlist (95%) 95%
Customer sends Rdie/Cdie/I(t)/PCB/VRM Core DDR
Package selection