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Similar to Intel Core i7 Microarchitecture Guide
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Intel Core i7 Microarchitecture Guide
- 1. I7’s Core Jon Ross & Philip Cosgrave
- 2. Intel’s Core i7 Jon Ross & Philip Cosgrave
- 3. Content • Overview • Socket • SSE 4.2 Instruction Set • Cores – Intel Quickpath Interconnect – Nehalem - new micro-architecture – EP, EX socket – 3 to 2 chip solution
- 4. Over View • Released November 2008 • CPU clock • Cache • Turbo Boost
- 5. Socket • Known as the LGA 1366 or Socket B • Contact points
- 6. Instruction Set • Backwards support • Added SSE 4.2 Instruction set – CRC32 – PCMPESTRI – PCMPESTRM – PCMPISTRI – PCMPISTRM – PCMPGTQ – POPCNT
- 7. Core: Over View • 4 Physical, 8 logical from H/T • 3 channel memory
- 8. Core: Intel Quickpath Interconnect • Intel X58 Arch • Replaced front side bus • Max width: 20 bit • Max bandwidth: 16GB/s Unidirectional • I7 920, 940 – 16 bit and 4.8 GT/s = 19.2 GB/s • I7 965XE – 16 bit and 6.4 GT/s = 25.6GB/s
- 9. Core: Nehalem – 45nm architecture – Scalable performance for from one-to-16 (or more) threads and from one-to-eight (or more) cores. – Power usage
- 10. Core: EP & EX • EP is for 2 sockets (the base layout) • EX is for 4 and 8 sockets – Is the EP duplicated with more interconnects
- 13. Core: 3 to 2 chip solution • Named Westmere • Moved GPU functionality from the Northbridge onto the CPU • Enables full disk encryption
- 16. Other Fun Info
- 17. More Extra Info
- 18. References • Crysis Benchmark: http://www.pcgameshardware.com/aid,665558/Intel-Core-i7-Nehalem-CPUs-reviewed/Reviews/? page=5 • Pin set: Intel Core i7 Extreme Edition and Intel Core i7 Processor and LGA1366 Socket http://download.intel.com/design/processor/designex/320837.pdf • Intel Overclock: http://www.engadget.com/2008/12/03/intels-core-i7-extreme-edition-965-overclocked-to-5-5ghz/ • Intel Nehalem Arch http://download.intel.com/pressroom/kits/events/idffall_2008/SSmith_briefing_roadmap.pdf • 2 vs 3 chip solution http://www.neoseeker.com/Articles/Hardware/Reviews/intel_32nm/4.html • Intel i7 homepage http://www.intel.com/products/processor/corei7/index.htm • Intel Quickpath http://www.intel.com/technology/quickpath/introduction.pdf • Intel Turboboost http://www.intel.com/technology/turboboost/index.htm • Nehalem Arch http://www.intel.com/technology/architecture-silicon/next-gen/whitepaper.pdf
Editor's Notes
- Clock speed 2.66 GHz – 3.33GHz Cache 32 KB L1 instruction and 32 KB L1 data cache per core 256 KB L2 cache (combined instruction and data) per core 8 MB L3 (combined instruction and data) "inclusive", shared by all cores
- Successor to the LGA 775 and completely incompatible I7 is the first to use the LGA 1366
- x86, x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 SSE4.2 CRC32 - Accumulate CRC32C value using the polynomial 0x11EDC6F41 (or, without the high order bit, 0x1EDC6F41) PCMPESTRI - Packed Compare Explicit Length Strings, Return Index PCMPESTRM - Packed Compare Explicit Length Strings, Return Mask PCMPISTRI - Packed Compare Implicit Length Strings, Return Index PCMPISTRM - Packed Compare Implicit Length String, Return Mask PCMPGTQ - Compare Packed Signed 64-bit data For Greater Than POPCNT - Population count (count number of bits set to 1) - bit manipulation; shares the same opcode for JMPE, the instruction used in Itanium CPUs to escape from IA-32 mode. POPCNT instruction may also be implemented in some processors that do not support the other SSE4 instructions and a separate bit can be tested to confirm POPCNT presence.
- Power Usage Faster Synchronization Primitives Faster Handling of Branch Mispredictions Improved Hardware Prefetch and Better Load-Store Scheduling Improved Virtualization Performance. http://www.intel.com/technology/architecture-silicon/next-gen/whitepaper.pdf