2. Bawar A. Abdalla, Azhi A. Faraj and Zhenar Sh. Faeq
http://www.iaeme.com/IJECET/index.asp 2 editor@iaeme.com
2015, pp. 01-06.
http://www.iaeme.com/IJECET/issues.asp?JTypeIJECET&VType=6&IType=8
1. INTRODUCTION
Digital logic circuits are widely used in modern technologies. These circuits are
becoming more popular because of their high performances and low consuming
power. They are also used in the design of flip flops [1]. Moreover, Flip Flops are the
essential elements of designing the semiconductor devices [2]. These Flip Flops can
be used to design and implement counters. It is known that counters are the
fundamental function of digital circuits which can count from zero to a specified
maximum number or vice versa additionally they can be used to generate specific
patterns [3]. Counters can be used in many areas of practical applications such as
microcontrollers, frequency synthesizers, analog to digital converters, digital clocks
and timing circuits and circuits used in communication systems [4].
The number of states that a counter goes through to complete its counting cycle is
called the modulus of the counter in which after completing the cycle; the counter
returns back to its initial state [5]. In addition, the modulus of a counter can be
determined through the number of bits used in the counter’s circuit. So that, a counter
with n bits can have 2n
states [6].
As mentioned earlier, Flip Flops can be used to design counters in a way that each
Flip Flop represents a single bit in the counter [2]. There are many types of Flip Flops
such as SR, D, T and JK. They can be properly grouped together to perform the
function of a counter. Furthermore, the connection of the Flip Flops together and the
way they are clocked classifies the counters to asynchronous and synchronous
counters. In asynchronous counters each Flip Flop receives clock pulse from the
previous Flip Flop. This makes the internal circuit needless of the entire clock circuit,
while in the synchronous counters all the Flip Flops are clocked simultaneously [6].
However, this feature gives the advantage of decreasing the propagation time delay in
synchronous counter compared to asynchronous counter.
2. BACKGROUND
2.1. J-K FLIP FLOP
The J-K flip flop is versatile and is a widely used type of flip-flop [6]. The
functioning of the J-K flip flop is the same as the S-R flip-flop in the SET and
RESET conditions in such a way as long as J and K are different the output follows
the J input. Furthermore, they are similar in no-change condition when both J and K
inputs are low. The difference is that the J-K flip-flop toggles the output while both J
and K are high [6, 7]. Table below shows the truth table of J-K Flip Flop.
Table 1 J-K Flip Flop Truth Table.
3. Proposing A Mechanism and Internal Design of Synchronous Counters For Displaying
Decimal Values on Seven Segment Displays
http://www.iaeme.com/IJECET/index.asp 3 editor@iaeme.com
2.2 PARTIAL DECODING
It is known that the total number of states of a direct counter is 2n
where n is the total
number of flip flops. For example, the number of states of a counter which is made of
3 flip flops is 23
which are 8 states and it can count from zero to seven. However, in
some real life applications counters need to have irregular states that are not in the 2n
sequences. In this case, a mechanism should be applied to reset the counter in a
desired state and this mechanism is called partial decoding [6]. For example, if it is
required to design a modulus 5 counter which needs to count from zero to four, the
partial decoding mechanism should be applied to reset the counter at the state of five
[10]. This can be seen in the figure 1. However, partial decoding mechanism is not
practical to be used in designing down counters; it is only aimed to be used to reset an
up counter in a desired state [9].
Figure 1 Modulus 5 Synchronous Up Counter.
As can be seen from the above figure, the counter is made of a group of three Flip
Flops which is the minimum required number of Flip Flops to satisfy the desired
modulus. In addition, the first flip flop from the left belongs to the least significant bit
while the first one from the right represents the most significant bit [6]. Moreover, the
counting states can be displayed using decoded seven segment display which is
provided by the Electronic WorkBench software. However, this display is showing
the outputs in Hexadecimal values in such away when the value is ten in decimal it
converts it to A in Hexadecimal. On the account of this reason, there should be a
proposed way to show the decimal output values greater than 9 in this decoded seven
segment display. In this particular case, two counters can be cascaded together to
display both decimal digits on two different seven segment displays properly. For
example, a display for the tens position while the other one for the ones position. The
aim of this paper is to implement and design a practical high performance counter to
count from zero to a desired two decimal digits number, modulus 65 as a case study
by using Electronic Workbench Software.
In this paper, Electronics Workbench software has been used to design the desired
circuit because it is companionable to use and fast in response [8]. It provides
switching circuits to indicate whether the input is high or low. It also provides an
output circuit which is called decoded seven segment display to display the states in
decimal values.
4. Bawar A. Abdalla, Azhi A. Faraj and Zhenar Sh. Faeq
http://www.iaeme.com/IJECET/index.asp 4 editor@iaeme.com
3. DESIGN AND IMPLEMENTATION OF MODULUS 65 UP
COUNTER
To design the modulus 65 synchronous up counter there needs to be two counters
cascaded together. The first counter is for ones decimal digit and the second one for
the tens digit. To start with, the first counter should be cleared after each 9 clock
pulses because it is modulus 9 which is aimed to count from 0 to 9. However, the
other counter which is aimed to count the values in the tens decimal digit is required
to count from 0 to 6 because the maximum value of this counter is 6. Moreover, both
counters need to be cleared when the count is 65. This can be done by taking the value
of 66 and decoding it using partial decoding mechanism.
An external synchronous clock is applied to the ones digit counter to count from 0
to 9. However, the tens digit counter receives its clock pulse after the last state of the
first counter in such a way the first counter’s 11th state which is 10 in decimal has to
be partially decoded to reset itself and generate an input synchronous clock pulse to
the tens digit counter. This is called cascaded connection of counters [6]. The state
after the last state of the desired modulus 65 counter should be taken to clear both
counters. This can be done by decoding the 6th state of both counters by a logic AND
gate to clear both counters. Finally, the counter will return to its initial state. The
design can be seen in figure 2.
Figure 2 Modulus 65 Synchronous Up Counter (Initial State).
As can be seen from figure 2, the design of modulus 65 counter is implemented by
using electronic workbench software. The counter is in initial state which 00 appears
on both decoded seven segment displays. In addition, the seven segment displays are
labeled as unit and ten. However, if a clock pulse is applied, the ones counter will
change its state to 1 while the tens counter will remain zero on its output display. If
second clock pulse is applied the ones digit will changes its state to 2. This counting
will continue until the first display reaches decimal 9. After this, it will return back to
0 and the tens digit counter changes its state to 1 by receiving a synchronous clock
pulse from the ones counter to make the circuit show decimal number 10 on its
displays. This state can be seen in figure 3.
5. Proposing A Mechanism and Internal Design of Synchronous Counters For Displaying
Decimal Values on Seven Segment Displays
http://www.iaeme.com/IJECET/index.asp 5 editor@iaeme.com
Figure 3 Modulus 65 Synchronous Up Counter to show 10 in decimal.
Finally, the last state of the counter is 65 which can be seen in figure 4. After this
state, the counter will return to its initial state meaning 00 appears on the displays.
Figure 4 Modulus 65 Synchronous Up Counter to show 65 in decimal.
4. CONCLUSION
To conclude, practical high performance cascaded modulus 65 counter were designed
by using J-K Flip Flops. The partial decoding mechanism were sufficient and
practical to design the desired counter in such away each counter could be partially
decoded to generate its desired states separately as well as to clear the entire circuit
simultaneously. The proposed counter was implemented by using electronic
workbench software which is friendly and its environment is close to real life
implementation. The states of the counter initially starts from 0 and increases one by
one up to 65 then it returns back to its initial state. It can be said that, this mechanism
is practical to design any modulus of up counters which are aimed to show only
decimal values on the seven segment displays. However, partial decoding mechanism
is not practical to design down counters.
6. Bawar A. Abdalla, Azhi A. Faraj and Zhenar Sh. Faeq
http://www.iaeme.com/IJECET/index.asp 6 editor@iaeme.com
REFERENCES
[1] Woo Jin Kim, Yong-Bin Kim, ―A Localized Self-Resetting Gate Design
Methodology for Low Power‖ IEEE 2001.
[2] J. Tschanz, S. Narendra, Z. Chen, S. Borkar,M. Sachdev, V. De. Comparative
delay and energy of single edge triggered and dual edgetriggered pulsed flip-flops
for high performance microprocessors, In Proc.ISPLED, 2001, pp. 207–212.
[3] H, Yogita. K.L, Akalpita. J. S. Baligar. Design and Implementation of
Synchronous 4-bitup Counter Using 180NM CMOS Process Technology.
International Journal of Research in Engineering and Technology. 3(5), 2014.
[4] Dibal, P.Y., Design and Implementation of Mod-6 Synchronous Counter Using
VHDL. Arid Zone Journal of Engineering, Technology and Environment. 9,
pp17-26
[5] Anil, KM. 2007. Digital Electronics Principles: Devices and Applications.
Sussex: John Wiley & Sons.
[6] T. L. Floyd, Digital Fundamentals, Fourth Edition, Macmillan Publishing, 1990,
p.395.
[7] Varun I., Gupta T.K., Ultra - low power NAND based multiplexer and flip flop.
IEEE International Conference, pp. 1-5, 2013.
[8] Aissi, C. and D. Kazakos, A review of chaotic circuits, simulation and
implementation, in Proceedings of the 10th WSEAS international conference on
Circuits2006, World Scientific and Engineering Academy and Society (WSEAS):
Athens, Greece. p. 125-131.
[9] Bawar A. Abdalla, Zhenar Sh. Faeq, and Zrar Kh. Abdul, 2015. Exploiting
Design Of Synchronous Counters Method To Design And Implement Mod 6
Direct Down Counter. International journal of Electronics and Communication
Engineering &Technology 6(7), pp 31-37.
[10] B. Somanathan, Digital Electronics and Logic Design, Sixth Printing, Asoke k.
Gosh, 2006, p.138
![Bawar A. Abdalla, Azhi A. Faraj and Zhenar Sh. Faeq
http://www.iaeme.com/IJECET/index.asp 2 editor@iaeme.com
2015, pp. 01-06.
http://www.iaeme.com/IJECET/issues.asp?JTypeIJECET&VType=6&IType=8
1. INTRODUCTION
Digital logic circuits are widely used in modern technologies. These circuits are
becoming more popular because of their high performances and low consuming
power. They are also used in the design of flip flops [1]. Moreover, Flip Flops are the
essential elements of designing the semiconductor devices [2]. These Flip Flops can
be used to design and implement counters. It is known that counters are the
fundamental function of digital circuits which can count from zero to a specified
maximum number or vice versa additionally they can be used to generate specific
patterns [3]. Counters can be used in many areas of practical applications such as
microcontrollers, frequency synthesizers, analog to digital converters, digital clocks
and timing circuits and circuits used in communication systems [4].
The number of states that a counter goes through to complete its counting cycle is
called the modulus of the counter in which after completing the cycle; the counter
returns back to its initial state [5]. In addition, the modulus of a counter can be
determined through the number of bits used in the counter’s circuit. So that, a counter
with n bits can have 2n
states [6].
As mentioned earlier, Flip Flops can be used to design counters in a way that each
Flip Flop represents a single bit in the counter [2]. There are many types of Flip Flops
such as SR, D, T and JK. They can be properly grouped together to perform the
function of a counter. Furthermore, the connection of the Flip Flops together and the
way they are clocked classifies the counters to asynchronous and synchronous
counters. In asynchronous counters each Flip Flop receives clock pulse from the
previous Flip Flop. This makes the internal circuit needless of the entire clock circuit,
while in the synchronous counters all the Flip Flops are clocked simultaneously [6].
However, this feature gives the advantage of decreasing the propagation time delay in
synchronous counter compared to asynchronous counter.
2. BACKGROUND
2.1. J-K FLIP FLOP
The J-K flip flop is versatile and is a widely used type of flip-flop [6]. The
functioning of the J-K flip flop is the same as the S-R flip-flop in the SET and
RESET conditions in such a way as long as J and K are different the output follows
the J input. Furthermore, they are similar in no-change condition when both J and K
inputs are low. The difference is that the J-K flip-flop toggles the output while both J
and K are high [6, 7]. Table below shows the truth table of J-K Flip Flop.
Table 1 J-K Flip Flop Truth Table.](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)