digital aluc and shift register important content

1. ALU:
module alu(a,b,s,y);
input[3:0]a;
input[3:0]b;
input[2:0]s;
output[7:0]y;
reg[7:0]y;
always@(a,b,s)
begin
case(s)
3'b000:y=a+b;
3'b001:y=a-b;
3'b010:y=a&b;
3'b011:y=a|b;
3'b100:y=4'b1111^a;
3'b101:y=(4'b1111^a)+1'b1;
3'b110:y=a*b;
3'b111:begin y=a;
y=y>>1'b1;
end
endcase
end
endmodule
TESTBENCH:
initial begin
a=4'b1101; b=4'b1001;
s=3'b000;
#100 s=3'b001;
#100 s=3'b010;
#100 s=3'b011;
#100 s=3'b100;
#100 s=3'b101;
#100 s=3'b110;
#100 s=3'b111;
end
initial
#1000 $stop;
Endmodule
SISO:
module siso(clk,rst,a,q);
input a;
input clk,rst;
output q;
reg q;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
q<=1'b0;

2. else
q<=a;
end
endmodule
TESTBENCH:
initial
clk=1'b1;
always #10 clk=~clk;
initial begin
a=1'b0;rst=1'b1;
#100 rst=1'b0;
#100 a=1'b1;
#100 rst=1'b1;
#100 rst=1'b0;
end
initial
#1000 $stop;
Endmodule
PIPO:
module pipo(clk,rst,a,q);
input clk,rst;
input[3:0]a;
output[3:0]q;
reg[3:0]q;
always@(posedge clk,posedge rst)
begin
if (rst==1'b1)
q<=4'b0000;
else
q<=a;
end
endmodule
TESTBENCH:
initial
clk='b1;
always #10 clk=~clk;
initial begin
a=4'b1101;rst=1'b1;
#100 rst=1'b0;
#100 a=4'b1000;
#100 rst=1'b1;
#100 rst=1'b0;
end
initial
#600 $stop;
Endmodule
SIPO:

3. module sipo(a,clk,rst,q);
input clk,rst;
input a;
output [3:0]q;
wire [3:0]q;
reg [3:0]temp;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
temp<=4'b0000;
else
begin
temp<=temp<<1'b1;
temp[0]<=a;
end
end
assign q=temp;
endmodule
TESTBENCH:
initial
clk=1'b0;
always #10 clk=~clk;
initial begin
rst=1'b1; a=1'b1;
#500 rst=1'b0;
#100 a=1'b0;
#100 a=1'b1;
#100 a=1'b0;
#100 a=1'b0;
#100 a=1'b1;
#100 a=1'b0;
end
initial
#1300 $stop;
endmodule
PISO:
module piso(clk,rst,a,q);
input clk,rst;
input [3:0]a;
output q;
reg q;
reg [3:0]temp;
always@(posedge clk,posedge rst)
begin
if(rst==1'b1)
begin
q<=1'b0;
temp<=a;
end

4. else
begin
q<=temp[0];
temp <= temp>>1'b1;
end
end
endmodule
TESTBENCH:
initial
clk=1'b1;
always #10 clk=~clk;
initial begin
rst=1'b1; a=4'b1101;
#300 rst=1'b0;
#200 rst=1'b1;
#200 rst=1'b0;
end
initial
#1000 $stop;