(a)Suppose the main memory of the Pep8 were completely filled with

1. (a)Suppose the main memory of the Pep/8 were completely
filled with unary instruc- tions. How many instructions would it
contain? (b)What is the maximum number of instructions that
would fit in the main memory if none of the instructions is
unary? (c) Suppose the main memory is completely filled with
an equal number of unary and nonunary instructions. How many
total instructions would it contain?
Solution
The Pep/8 Computer
• Simulated computer system
• Has features in common with many real
architectures
• Illustrates fundamental concepts that apply
to most systems
Pep/8 “hardware” components
• CPU
• Main memory
• I/O devices
• Bus
Pep/8 CPU
• “Electronics” that comprise the Pep/8
instruction set:

2. – ALU
– Control unit
• Registers: specialized high-speed memory
locations
Main memory
• Aka core memory
• 65,536 8-bit bytes, addressed from 0000
(top address) to FFFF (bottom address)
• Word: specific # of bytes, usual working
storage unit size
– Pep/8 has 16-bit word; this accounts for the
size of most of the registers
– Address of a word is the lower (in value) of
the two bytes
Input devices
• Pep/8 simulates 2:
– Keyboard
– File
• In a particular program, you can use
either, but not both
Output devices
• Same sort of rules as input; 2 supported,
but only one at a time:
– Screen
– Textspecifier

3. Instructions
• In general, the instruction set is wired into the
CPU:
– Varies among manufacturers
– May also vary within a specific manufacturer’s set of
platforms (e.g. IBM)
• Pep/8 Instruction set
– 32 instructions; 1 or 2-part
– All instructions have a 1-byte instruction specifier; 2-
part instructions have this, plus a 16-bit operand
specifier
Pep/8 Instruction Specifier Format
• Each instruction specifier is composed of:
– 4-bit opcode: determines which instruction will
be executed
– 1-bit register specifier: determines whether
the instruction affects the accumulator (O=A)
or index register (1=X)
– 3-bit addressing mode specifier (ignored if
instruction is unary)
B)
6 registers of the CPU
NZVC, A, X, PC, SP, IR
A
accumumlator, 16 bit

4. NZVC
status bit, 4 bit
X
index, 16 bit
PC
Program Counter, 16 bit
SP
Stack pointer, 16 bit
IR
Instruction register, 24 bit
Instruction Register
holds an instruction after it has been accessed from memory
X, PC, SP
3 registers that help the CPU access info in main memory
Core memory
another name for main memory
Top of Memory
bytes with small addresses
Bottom of Memory
Bytes with large addresses
2 output devices of pep/8
text file and screen
Solid lines
data flow lines
dashed lines

5. control lines
39
How many instructions does pep/8 have in its instruction set?
opcode
first part of 8 bit instruction specifier
'a'
can be either a 1 or a 0
machine language
a binary sequence that the CPU interprets according to the
opcodes of its instruction set
direct addressing
The CPU interprets the operand specifier as the address in main
memory of the cell that contains the operand - 001.
Stop Command
0000 0000 , makes the Computer stop
Load instruction
loads one word from a memory location inot accumulator of
index, based on r value
1100 raaa
load instruction
Store instruction
stores one word from either the accumulator or the index
register to a memory location
1110 raaa
store instruction

6. Add instruction
a word from main meory is added to the content of the register r
0111 raaa
add instruction
Subtract instruction
the operand is subtracted from the register, the result is placed
in register and the operand is unchanged
1000 raaa
subtract instruction
And instruction
Performs a logical operation on the register, useful for masking
out undesired 1 bits from a pattern, affects N & Z
1001 raaa
and instruction
Or instruction
Performs a logical operaton on the register, useful for inserting
1 bits into a bit pattern, affects N & Z
1010 raaa
or instruction
Invert instruction
Performs the NOT operation on the register, affects N & Z
0001 100r
invert instruction
Negate instruction
interprets the register as a signed integer and negates it, affects

7. N, Z, V bits
0001 101r
negate instruction
byte instructions
operate on a single byte of info instead of a word
Load byte instruction
loads the operand into the right half of either the accumulator or
index, affects N &Z
1101 raaa
load byte instruction
Store byte instruction
stores the right half of either the accumulator or index into a
one byte memory location and doesn't affect any status bits
1111 raaa
store byte instruction
Character input instruction
Takes the next ASCII char from the input device and stores the
corresponding binary code in main memory
0100 1aaa
character input instruction
Character Output instruction
Sends the content of a byte in memory to the output device
0101 0aaa
character output instruction
do loop

8. aka vonNeumann execution cycle
5 operations of vonNeuman cycle
Fetch, Decode, Increment, Execute, Repeat
0000
What is the lowest hexadecimal address in PEP/8 memory?
FFFF
What is the highest hexadecimal address in PEP/8 memory?
Unary Instruction Specifiers
no operand specifier, example: 0010 0000, 0000 0000
r <--- -r; N <--- r<0, Z <--- r=0, V<---{overflow}
In pep/8 the following RTL specification is for the negate
instruction.
ISA
Instruction Set Architecture
r <--- Oprnd; N <--- r<0, Z <--- r=0
In pep/8 the following RTL specification is for the load
instruction
machine cannot distinguish instructions from data
What is both an advantage and a disadvatnage of the von
Neumann execution cycle?
registers
The pep/8 CPU contains six specialized memory locations
called?
r[8..15]<--- byte Oprnd; N <--- r<0, Z <--- r=0
In pep/8 the following RTL specification is for the load byte

9. instruction
byte Operand <--- r[8..15]
In pep/8 the following RTL specification is for the store byte
instruction
r <--- -r; N <--- r<0, Z <--- r=0
In pep/8 the following RTL specification is for the invert
instruction
r <--- r / Oprnd; N <--- r<0, Z <--- r=0
In pep/8 the following RTL specification is for the And
instruction
r <--- r / Oprnd; N <--- r<0, Z <--- r=0
In pep/8 the following RTL specification is for the Or
instruction
r <--- r - Oprnd; N <--- r<0, Z <--- r=0, V{overflow}, C{carry}
In pep/8 the following RTL specification is for the Subtract
instruction
r <--- r + Oprnd; N <--- r<0, Z <--- r=0, V{overflow}, C{carry}
In pep/8 the following RTL specification is for the Add
instruction
C)Mnemonic,
modeHexBinaryInstructionLoad/storeLDA,iC0110b r000Load
into AC from immediateLDA,dC1110b r001Load into AC from
memory addressSTA,iE01110 r000[ILLEGAL
INSTRUCTION]STA,dE1111b r001Store from AC into
memoryIf "r" bit is 1, use X(index) register; else

10. (accumulator)
If "b" bit is 1, one bye only.Arithmetic
instructionsADDA,i700111 r000Add AC + immediate (into
AC)ADDA,d710111 0001Add AC + memory (into
AC)SUBA,i801000 r000Subtract AC - immediate (into
AC)SUBA,d811000 r001Subtract AC - memory (into
AC)Logical instructionsANDA,i901001 r000AND AC +
immediate (into AC)ANDA,d911001 r001AND AC + memory
(into AC)ORA,iA01010 r000OR AC + immediate (into
AC)ORA,dA11010 r001OR AC + memory (into
AC)CPA,iB01011 r000Compare AC with
immediateCPA,dB11011 r001Compare AC with
memoryNOTA180001 100rInvert every bit (1-s
complement)NEGA1A0001 101rNegate the value (2-s
complement)ASLA1C0001 110rArithmetic shift left (with sign
ext.)ASRA1E0001 111rArithmetic shift right (end-
off).ROLA200010 000rRotate leftRORA220010 001rRotate
rightI/O instructionsCHARI,d490100 1001Character input to
memoryCHARO,i500100 1000Character output from
immediateCHARO,d510101 1001Character output from
memoryDECI,d310011 0001Read a decimal number into
memory.DECO,i380011 1000Write a decimal number from
immediate.DECO,d390011 1001Write a decimal number from
memory.STRO400100 0000String output trapBranch
instructionsSTOP000000 0000Stop the computer!BR040000

11. 010xBranch to specified addressBRLE060000 011xBranch if
less-than-or-equalBRLT080000 100xBranch if less-
thanBREQ0A0000 101xBranch if equalBRNE0C0000
110xBranch if not equalBRGE0E0000 111xBranch if greater-or-
equalBRGT000000 000xBranch if greaterBRV020000
001xBranch if overflowBRC040000 010xBranch if
carryCALL060000 011xCall subroutineRETn580101
1nnnReturn from subroutine (with n bytes)If "x" bit is 1, use
X(index) register; else immediate.Stack and other
instructionsADDSP600110 0000Add to stack
pointerSUBSP610110 0001Subtract from stack
pointerMOVSPA020000 0010Move stack pointer to
AMOVFLGA030000 0011Move flags (NZVC) to
ARETTR010000 0001Return from trapNOP2n0010 nnnnUnary
and non-unary no-op trap