A short summary of the manual. Chapter on ePWM

1. ePWM 101
wrt 0L_sensing.c

2. Submodules and Signal Connections for an
ePWM Module

3. Submodule Block Diagram

4. Time Base (TB) Submodule
● Has a dedicated 16-bit counter along with built-in synchronization logic to allow multiple
ePWM modules to work together as a single system.
● A clock prescaler divides the ePWM clock to the counter.
● A period register is used to control the frequency and period of the generated waveform.
● Counter operates in three modes-- up count, down count, and up/down count
● The up count and down count modes are used to generate asymmetrical waveforms.
● The up/down count mode is used to generate symmetrical waveforms.

5. Counter Compare (CC) Submodule
● Continuously compares the time-base count value to four counter compare registers--
Compare A, Compare B, Compare C, and Compare D
● Compare event is fed to the action qualifier and event trigger submodules
● All four compare registers can be used to start an ADC conversion or generate an ePWM
interrupt
● For the up count and down count modes, the count matches or occur only once per cycle.
● However, for the up/down count mode, a count match occurs twice per cycle, since there is a
match on the up count and down count.

6. Action Qualifier (AQ) Submodule
● Responsible for constructing and generating the switched PWM waveforms
● Utilizes match events from the time-base and counter compare submodules for
performing actions on the ePWMxA and ePWMxB output pins
● These actions are do nothing to the pin, clear the pin low, set the pin high, or toggle the
pin based independently on count up and count down time-base match events
● The match events are:
○ time based counter equals zero,
○ the time-base counter equals Compare A,
○ the time-base counter equals Compare B,
○ the time-base counter equals the period register value,
○ or a trigger event T1 and T2 based on a comparator, trip, or synchronization signal

7. Dead Band (DB) submodule
● Provides a classical approach for delaying the switching action of a power device
● Since power switching devices turn on faster than they turn off, a delay is needed to
prevent having a momentary short circuit path from supply rail to ground
● This submodule supports independently programmable rising edge and falling edge
delays with various options for generating the appropriate signal outputs on ePWMxA
and ePWMxB

8. PWM Chopper (PC) Submodule
● Modulates a high frequency carrier signal with the PWM waveform that is generated by
the action qualifier and dead band submodules
● Its purpose is to control the power switching elements used with pulse transformer-
based gate drivers.
● The high frequency carrier signal is logically ended with the ePWM outputs
● Programmable options are available to support the magnetic properties and
characteristics of the transformer and associated circuitry

9. Trip Zone (TZ) Submodule
● Provides a protection mechanism to protect the output pins from abnormalities, such as
overvoltage, overcurrent, and excessive temperature rise
● A fast clock-independent logic mechanism is utilized to quickly handle fault conditions by
forcing the ePWMxA and ePWMxB outputs to a safe state, such as high, low, or high
impedance
● The trip zone signals can be generated externally from any GPIO pin which is mapped
through the input cross-bar, internally from an eQEP error signal, system clock failure, or
emulation stop output from the CPU
● Numerous trip zone source signals can be generated from the digital compare submodule

10. Digital Compare (DC) Submodule
● Digital compare submodule expands the capabilities of the trip zone submodule by comparing
signals external to the ePWM module, such as a signal from the comparator subsystem analog
comparators, to directly generate PWM events or actions which are then used by the time-
base, event trigger, and trip zone submodules
● These compare events along with the submodules can generate PWM synchronization,
generate an ADC start of conversion, trip the output, or generate a trip interrupt.
● A compare event is generated when one or more of its inputs are either high or low. The signals
can originate from any external GPIO pin which is mapped through the input cross-bar and
from various internal peripherals which are mapped through the ePWM cross-bar.

11. Event Trigger (ET) Submodule
● Manages the events generated by the time-base, counter compare, and digital compare
submodules for generating an interrupt to the CPU and/or a start of conversion pulse to
the ADC when selected events occur.
● These event triggers can occur when the time-base counter equals
○ Zero,
○ Period,
○ Zero or period,
○ The up or down count match of a Compare A, B, C, or D register.

12. Code references

13. EPwm1Regs.TBCTL.bit.CLKDIV = 0;
● The value set to CLKDIV is 1
● TBCLK (Time Base Clock frequency)
= SYSCLKOUT (150 MHz) / 1 x HSPCLKDIV

14. EPwm1Regs.TBCTL.bit.HSPCLKDIV = 1;
● HSPCLKDIV value set is 2
● Time Base Clock frequency is 150 / 2 x 1 = 75 MHz

15. EPwm2Regs.TBCTL.bit.CTRMODE = 2;

16. EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;

17. EPwm1Regs.TBPRD = 3750;
● Time Base Period is set to 3750
● This was done in hindsight of the fact that the PWM frequency had to be set to 10KHz
● PWM period = 2 x TBPRD x TBCLK period
● Hence TBPRD for 10 KHz frequency = 75 M/ 2 x 10K = 3750
EPwm1Regs.DBRED = 0;
EPwm1Regs.DBFED = 0;
● Rising Edge delay = DBRED x TBCLK Period = 0
● Falling edge delay = DBFED x TBCLK period = 0

18. EPwm1Regs.DBCTL.bit.OUT_MODE = 3;

19. EPwm1Regs.DBCTL.bit.POLSEL = 2;
● Need to invert ePWMxB as it controls the complementary switch in a single leg of the
inverter.
● Closing of both switches in a leg will lead to a short circuit.

20. EPwm1Regs.DBCTL.bit.IN_MODE = 0;