1. RIADUL ISLAM
701 Beach St. Apt# 302 Santa Cruz California 95060 USA.
(831) · 419 · 8272 rislam@ucsc.edu LinkedIN {Riadul Islam} Personal Webpage
SUMMARY
· Seeking a full-time/intern position in the area of Digital Circuit Design, ASIC, FPGA, CAD, Design Automa-
tion of VLSI, Memory/Interconnect Architecture, and On-Chip Signal Integrity.
EDUCATION
University of California Santa Cruz September 2012 - Present
Ph.D. Candidate, Computer Engineering, Expected graduation date: March 2017
Dissertation: Current-Mode Clocking and Synthesis Considering Low-Power and Skew.
Supervisor: Matthew R. Guthaus
Concordia University August 2011
Master of Applied Science in Electrical & Computer Engineering
Dissertation: High-speed Energy-efficient Soft Error Tolerant Flip-flops.
Supervisor: S. M. Jahinuzzaman
Bangladesh University of Engineering & Technology June 2007
B.S. in Electrical & Electronic Engineering
Major: Electronics, Digital Communication
RESEARCH EXPERIENCE
VLSI-DA Lab at UCSC September 2012 - Present
Graduate Research Assistant Santa Cruz, CA
· Developed an automated tool for clock routing, optimization using novel current-mode flip-flop by applying
low-power digital circuit design and CAD methodologies.
Research Internship at ISR Technologies May 2012 - August 2012
Graduate Research Intern Montreal, Canada
· FPGA based fault measurement using MATLAB, C, and vhdl code.
VLSI Lab, ECE, at Concordia University September 2009 - August 2011
Graduate Research Assistant Montreal, Canada
· Designed highly reliable energy-efficient soft error tolerant flip-flops.
KEY ACADEMIC GRADUATE LEVEL PROJECTS
· Implemented 64-bit pipeline adder using Synopsys ICC with TSMC 65nm tech. library, worst delay <1ns.
· A high-gain folded cascode opamp for s/h circuit with cmosisp18 tech., DC gain:64dB, UGB:167MHz, ST:8.5ns.
· A 8 × 8 bit multiplier-accumulator using VHDL, Verified the functionality of the design using ModelSim and
synthesized the design using Synopsis Design Compiler.
· Configurable cache block, 64 bits address, 32 bytes per cache line (1024 lines). Implemented hash function,
SRAM, hit/miss and signed extension units using Pyrope: a HDL developed by UCSC MASC group.
· 256 bytes (256 lines × 8 bits word) SRAM design using cmos 45nm technology. Implemented 6-T SRAM
cell array with read/write circuitry, sense amplifier, write data path using Cadence virtuoso and simulated
structure using HSPICE.
i

2. riadul islam resume
TECHNICAL STRENGTHS
Computer Languages C++, Python, Verilog, Tcl, MATLAB
Simulation Cadence Virtuoso, Synopsys IC Compiler, Xilinx ISE, HSpice
Utilities Latex, Git, SVN, Vim, Unix, MIPS, HTML
RELATED GRADUATE LEVEL COURSES
Advanced VLSI, Digital System Design and Synthesis, ASIC Design, Computer Architecture, CMOS RF
Circuit Design, Analysis of Algorithms, Power Management, Introduction to Analog VLSI.
FELLOWSHIPS & AWARDS
· 2014 IEEE International Symposium on Circuits and Systems (ISCAS) Student Travel Award, Australia.
· Richard Newton Young Fellow award, 2013 Design Automation Conference (DAC), Austin, USA.
· 2012-2013 UCSC Regents Fellowship, USA.
· Partial Tuition Graduate Scholarship for Int. Students, (5–Terms), Concordia University, 2009-2011, Canada.
PATENTS
· M. Guthaus and R. Islam, Current-mode clock distribution. Application no. PCT/US2015/013572, Publica-
tion no. WO2015116843 A3.
TEACHING EXPERIENCE
· Graduate Student Instructor (Lecturer) at UCSC, January 2017 - March 2017. Serving as a teaching
faculty for the Computer Architecture course, enrollment 200 students. 3 hours lecture per week and 2 hours
office hour per week. Supervise 2 Teaching Assistant and 2 graders.
· Lecturer at University of Asia Pacific, Bangladesh, October 2007 - August 2009. Taught two theory
course (VLSI-I, Digital Communication) and instructed multiple laboratory courses (electronic I-II).
PEER-REVIEWED PUBLICATIONS & PRESENTATIONS
· R. Islam and M. Guthaus, ‘CMCS: Current-Mode Clock Synthesis,’ Design Automation Conference (DAC),
WIP session, Austin, Tx, USA, June 2016.
· R. Islam, H. Fahmy, P. Lin and M. Guthaus, ‘Differential Current-Mode Clock Distribution,’ IEEE Midwest
Symposium on Circuits and Systems (MWSCAS), Fort Collins, USA, August 25, 2015.
· R. Islam and M. Guthaus, ‘CMCS: Current-Mode Clock Synthesis,’ in IEEE Tran. on VLSI, Sep 15, 2016.
· R. Islam and M. Guthaus, ‘Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop,’ IEEE
Transactions on Circuits and Systems I (TCASI), Volume: 62, Issue: 4, March 27, 2015.
· P. Lin, H. Fahmy, R. Islam and M. Guthaus, ‘LC Resonant Clock Resource Minimization using Compensation
Capacitance,’ IEEE International Symposium on Circuits and Systems (ISCAS), Portugal, May 24–27, 2015.
· H. Fahmy, P. Lin, R. Islam and M. Guthaus, ‘Switched Capacitor Quasi Adiabatic Clock,’ IEEE International
Symposium on Circuits and Systems (ISCAS), Portugal, May 24–27, 2015.
· R. Islam and M. Guthaus, ‘Current-Mode Clock Distribution,’ IEEE International Symposium on Circuits
and Systems (ISCAS), Australia, June 1–5, 2014.
· R. Islam, ‘A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop,’ Inter-
national Symposium on Quality Electronic Design (ISQED), California, USA, March 19–21, 2012.
· R. Islam, S. E. Esmaeili, and T. Islam, ‘A High Performance Clocked Precharge SEU Hardened Flip-flop,’
IEEE International Conference on ASIC (ASICON), Xiamen, China, October 25-28, 2011.
· S. M. Jahinuzzaman and R. Islam, ‘TSPC-DICE: A Single Phase Clock High Performance SEU Hardened
Flip-Flop,’ IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Seattle, USA, August 1-4, 2010.
Page ii of iii