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TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 11, NOVEMBER 2014 New Three-Phase Multilevel Inverter With Reduced Number of Power Electronic Components Ammar Masaoud, Hew Wooi Ping, Member, IEEE, Saad Mekhilef, Senior Member, IEEE, and Ayoub Suliman Taallah Abstract—In this paper, a new configuration of a three-phase five-level multilevel voltage-source inverter is introduced. The pro- posed topology constitutes the conventional three-phase two-level bridge with three bidirectional switches. A multilevel dc link using fixed dc voltage supply and cascaded half-bridge is connected in such a way that the proposed inverter outputs the required output voltage levels. The fundamental frequency staircase modulation technique is easily used to generate the appropriate switching gate signals. For the purpose of increasing the number of voltage levels with fewer number of power electronic components, the structure of the proposed inverter is extended and different methods to deter- mine the magnitudes of utilized dc voltage supplies are suggested. Moreover, the prototype of the suggested configuration is manu- factured as the obtained simulation and hardware results ensured the feasibility of the configuration and the compatibility of the modulation technique is accurately noted. Index Terms—Bidirectional switch, fundamental frequency staircase modulation, multilevel inverter. I. INTRODUCTION MULTILEVEL inverters consist of a group of switching devices and dc voltage supplies, the output of which pro- duces voltages with stepped waveforms. Multilevel technology has started with the three-level converter followed by numerous multilevel converter topologies. Different topologies and wide variety of control methods have been developed in the recent literature [1]–[3]. The most common multilevel inverter config- urations are neutral point clamped (NPC), the flying capacitor (FC), and the cascaded H-bridge (CHB). The deviating voltage of neutral-point voltage in NPC, the unbalanced voltage in the dc link of FC, and the large number of separated dc supplies in CHB are considered the main drawbacks of these topolo- gies [4], [5]. Apart from these three main topologies, other Manuscript received March 13, 2013; revised June 26, 2013, September 23, 2013 and October 23, 2013; accepted December 10, 2013. Date of publication January 9, 2014; date of current version July 8, 2014. This work was supported by the University of Malaya’s provision of the High Impact Research under Grant D000022-16001 funding the Hybrid Solar Energy Research Suitable for Rural Electrification and UMRG project RP015 A-13AET. Recommended for publication by Associate Editor P. Barbosa. A. Masaoud is with the Department of Electrical Engineering, University of Malaya, Kuala Lumpur 50603, Malaysia (e-mail: ammarshz@yahoo.com). H. W. Ping is with UMPEDAC, University of Malaya, 59990 Kuala Lumpur, Malaysia (e-mail: wphew@um.edu.my). S. Mekhilef and A. S. Taallah are with the Power Electronics and Renewable Energy Research Laboratory, Department of Electrical Engineering, Univer- sity of Malaya, Kuala Lumpur 50603, Malaysia (e-mail: saad@um.edu.my; tech_youb@yahoo.fr). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2014.2298616 topologies are introduced [6]–[17]. Recently, asymmetrical and hybrid multistage topologies are becoming one of the most in- terested research area. In the asymmetrical configurations, the magnitudes of dc voltage supplies are unequal. These topologies reduce the cost and size of the inverter and improve the reliability since minimum number of power electronic components, capac- itors, and dc supplies are used. The hybrid multistage convert- ers consist of different multilevel configurations with unequal dc voltage supplies. With such converters, different modulation strategies and power electronic components technologies are needed [18]–[26]. On the other hand, for the purpose of improv- ing the performance of the conventional single- and three-phase inverters, different topologies employing different types of bidi- rectional switches have been suggested in [27]–[29]. Comparing to the unidirectional one, bidirectional switch is able to con- duct the current and withstanding the voltage in both directions. Bidirectional switches with an appropriate control technique can improve the performance of multilevel inverters in terms of reducing the number of semiconductor components, minimiz- ing the withstanding voltage and achieving the desired output voltage with higher levels [30]–[34]. Based on this technical background, this paper suggests a novel topology for a three- phase five-level multilevel inverter. The number of switching devices, insulated-gate driver circuits, and installation area and cost are significantly reduced. The magnitudes of the utilized dc voltage supplies have been selected in a way that brings the high number of voltage level with an effective application of a fun- damental frequency staircase modulation technique. Extended structure for N-level is also presented and compared with the conventional well-known multilevel inverters. Simulation and hardware results are given and explained. II. PROPOSED TOPOLOGY Fig. 1(a) and (b) shows the typical configuration of the pro- posed three-phase five-level multilevel inverter. Three bidirec- tional switches (S1–S6, Da1–Dc2), two switches–two diodes type, are added to the conventional three-phase two-level bridge (Q1–Q6). The function of these bidirectional switches is to block the higher voltage and ease current flow to and from the mid- point (o). A multilevel dc link built by a single dc voltage supply with fixed magnitude of 4Vdc and CHB having two unequal dc voltage supplies of Vdc and 2Vdc are connected to (+, –, o) bridge terminals. Based on the desired number of output volt- age levels, a number of CHB cells are used. Since the proposed inverter is designed to achieve five voltage levels, the power circuit of the CHB makes use of two series cells having two unequal dc voltage supplies. In each cell, the two switches are 0885-8993 © 2014 IEEE. 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