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Three Phase Diode Clamped Multilevel DC Link Inverter with Multi Reference
Modulation Techniques
Article  in  Journal of Advanced Research in Dynamical and Control Systems · January 2018
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Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 09-Special Issue, 2018
1793
*Corresponding Author: Nagaraja Rao
Article History: Received: May 15, 2018, Revised: June 10, 2018, Accepted: July 04, 2018
Three Phase Diode Clamped Multilevel DC
Link Inverter with Multi Reference
Modulation Techniques
1*
S. Nagaraja Rao, Assistant Professor, Dept. of Electrical Engineering, M.S.Ramaiah University of Applied Sciences, Bangalore
2
Kiran Kumar B M, Dept. of Electrical Engineering, M.S.Ramaiah University of Applied Sciences, Bangalore
3
Pranupa S, Dept. of Electrical Engineering, M.S.Ramaiah University of Applied Sciences, Bangalore
Abstract- Use of multilevel inverters have been widely accepted as an effective solution for high power and
high voltage applications. The performance of a multilevel inverter is superior to that of traditional inverters due to
their advantages such as, reduced THD, less switching stress, lower EMI. Different types of topologies and
modulation techniques for multilevel inverters have been discussed in the recent literature. In this paper three phase
multilevel inverter based on Diode Clamped Multilevel DC Link (DC-MLDCL) and full bridge inverter has been
proposed to reduce switch count and THD using multi reference based modulation techniques. The proposed multi
reference modulation techniques are based on sinusoidal and third harmonic reference wave compared with U-type
carrier wave. The performance parameters for the proposed DC-MLDCL inverter are analyzed in terms of THD,
fundamental output line voltage and output line current for R and RL loads. The results are verified through
MATLAB/simulation tool to verify the results of the proposed three phase seven level DC-MLDCL inverter
.Keywords— High-gain DC-DC converter, Asymmetric MLI, Grid Integration, Distributed Generation, THD
I. INTRODUCTION
Multilevel inverters are an emerging trend in recent decades as they are more suitable for high power utility
and industry applications [1]. Also, with several voltage levels at output, harmonics can be considerably reduced in
the output voltage even at the same switching frequency [2]. In recent times, multilevel inverter topology has been
applied to low voltage applications. The usefulness of multilevel inverter topologies incorporate, reduction in the
power ratings of the switches and cost.
Fig. 1 shows the schematic of inverter with one phase leg having various number of levels to understand
the working of multilevel converters. The representation of single leg 2-level inverter is depicted in Fig. 1(a) shows
to generate the voltage levels either ‘0’ or ‘E’ with respect to the negative terminal of the capacitor. The voltage
output of a 3-level inverter leg depicted in Fig. 1(b) to generate the voltage levels: 0, E or 2E. The generalized m-
level inverter leg depicted in Fig. 1(c) provides ‘n’ different levels of voltage at the output.
Fig. 1. Concept of multilevel inverter (a) two level (b) three level and (c) m- level
An interest on multilevel inverters was proposed by Nabae et al. [3]. The most important multilevel
topologies are categorized as (1) diode-clamped inverter [3, 4], (2) capacitor-clamped [4, 8], and (3) cascaded

Three Phase Diode Clamped Multilevel DC Link Inverter with Multi Reference Modulation Techniques
1794
inverter with separate dc sources [3]. As the number of levels increases, additional number of steps at the output
leads to stepped waveform (Fig. 2) results in reduced harmonic distortion [4].
Fig. 2. Example multilevel sinusoidal approximation using 11-levels
Fig. 2 demonstrates the generation of 11-level inverter output voltage waveform. Using multiple levels, the
multilevel inverter can yield operating characteristics such as high power levels, high voltages and high efficiency
by exclusion of the transformers. Various control strategies and modulations for multilevel inverters have been
discussed in the literature [4-7]. Most of the converters proposed in literature suffers from drawbacks related to
Electro Magnetic Interference (EMI) and switching losses which requires further filter circuits to minimize the EMI.
A converter to produce any type of voltage and current waveforms, basically a Pulse Width Modulation (PWM)
technique is used in most of the applications, which also includes DC source connection to the grid [9]. There are
other types of inverters which operates at higher frequencies has been proposed in [10], but they still need EMI
filters to minimize the distortions in the injected current. In [11], a concept of hybrid inverter with combination of
GTO and IGBT semiconductor based inverter is proposed, a hybrid modulation strategy with lower switching
frequency for GTO and higher switching frequency for IGBT is presented which results in the improvement in the
quality of the output waveform. Low frequency commutation based three phase inverter with an auxiliary circuit
added to the inverter to reduce distortion and improve the quality of an output waveform is proposed in [12]. Also,
use of EMI filters are eliminated as the inverters operates at line frequency. A new cascaded multilevel inverter with
less number of switches and insulated gate drive proposed in [13], uses a fundamental frequency switching
techniques results in less error in the output voltage with respect to the reference voltage. The importance were
given to reduce the size of the inverter, minimize the cost and simple control techniques. But, elimination of the
selected harmonics and THD is not addressed in the work.
This paper presents three phase seven level multilevel inverter based on DC-MLDCL and a bridge inverter
using multiple reference modulation techniques with sinusoidal and third harmonic reference wave using U-type
carrier wave. The proposed DC-MLDCL inverter can considerably reduce the switch count and the number of gate
drivers compared to the existing multilevel inverters. For ‘m’ levels, the proposed inverter needs ‘m+3’ switches,
Simulation has been carried out to validate the performance of the proposed DC-MLDCL inverters [14].
II. PROPOSED DC-MLDCL INVERTER TOPOLOGY
The configuration of proposed three phase DC-MLDCL is shown in Fig. 3. For simplicity, one leg is
considered to explain the operation and analysis of DC-MLDCL. The phase leg of DC-MLDCL, consisting of single
DC source, ten switches, eight clamping diodes and five capacitors, which provides seven voltage levels at the
output of bridge inverter. The switching table for one leg of proposed DC-MLDCL is shown in Table. 1. In this
structure, all the magnitudes of voltage across each capacitors are equal (Vc1 = Vc2 = Vc3). The maximum output
phase voltage is the sum of voltages across the capacitors and is given in (1).
𝑉 , = ∑ 𝑉 (1)
Equations (1) illustrate the phase voltage output level of the proposed DC-MLDCL inverter. By using the H-bridge
inverter the positive and negative levels are synthesized. The synthesized stepped output phase voltage level will be
obtained using (2) and (3).

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V , max = ∑ + V , If S , S = 1 (2)
V , max = ∑ − V , If S , S = 1 (3)
The number of output phase voltage levels can be obtained by the following equation:
NLevels, phase = (2C + 1) H (4)
Where ‘C’ is the number of voltage splitting capacitors and ‘H’ is the number of H-bridge inverter circuits.
The number of output line voltage levels for the three phase ‘m’ level DC-MLDCL inverter can be obtained by the
following equation:
NLevels, line = 2m-1 (5)
The switch count for the proposed three phase DC-MLDCL inverter can be estimated as follows:
NS = 6 (C1+C2+……Cn) + 4 (6)
Fig. 3. Proposed three phase seven level DC-MLDCL inverter
Table II provides a comparison of the number of components such as, DC sources, switches, clamping
diodes and voltage-splitting capacitors required to produce a 7-level phase voltage for the single phase and 13-level
output line voltage for the three phase DC-MLDCL inverter. From the table, it is clear that, the proposed structure
requires less number of components when compared with existing counterparts. Further, it has been observed that,
the substantial savings in components by increasing the number of voltage levels.
Sa7
Sa10
Sa9
Sa8
Sa1
Sa2
Sa3
Sa4
Sa5
Sa6
Da1
Da2
Da3
Da4
Ca1
Ca2
Ca3
Vdc
Sb7 Sb9
Sb8
Sb1
Sb2
Sb3
Sb4
Sb5
Sb6
Db1
Db2
Db3
Db4
Cb1
Cb2
Cb3
Vdc
Sc7
Sc10
Sc9
Sc8
Sc1
Sc2
Sc3
Sc4
Sc5
Sc6
Dc1
Dc2
Dc3
Dc4
Cc1
Cc2
Cc3
Vdc
Three Phase Load
Phase 'a' Phase 'b' Phase 'c'

1796
TABLE I. SWITCHING TABLE FOR ONE LEG OF DC-MLDCL INVERTER
Sl.No
Diode Clamped Phase leg Single Phase Full Bridge Voltage
Levels
On Switches Off Switches On Switches Off Switches
1 Sa1, Sa2, Sa3 Sa4, Sa5,Sa6 Sa7, Sa8 Sa9, Sa10 +3 Vdc
2 Sa2, Sa3, Sa4 Sa1,Sa5,Sa6 Sa7, Sa8 Sa9, Sa10 +2 Vdc
3 Sa3, Sa4, Sa5 Sa1. Sa2, Sa6 Sa7, Sa8 Sa9, Sa10 + Vdc
4 Sa4, Sa5,Sa6 Sa1, Sa2, Sa3 Sa7, Sa8 Sa9, Sa10 0
5 Sa3, Sa4, Sa5 Sa1. Sa2, Sa6 Sa9, Sa10 Sa7, Sa8 - Vdc
6 Sa2, Sa3, Sa4 Sa1,Sa5,Sa6 Sa9, Sa10 Sa7, Sa8 -2 Vdc
7 Sa1, Sa2, Sa3 Sa4, Sa5,Sa6 Sa9, Sa10 Sa7, Sa8 -3 Vdc
TABLE II. COMPONENTS COUNT COMPARISON
Components
Existing Proposed
Single Phase Three Phase Single Phase Three Phase
Switches 12 36 10 30
Main diodes 12 36 10 30
Clamping diodes 8 24 4 12
Capacitors 6 18 3 9
III. MODULATION TECHNIQUES
This paper also presents multiple reference modulation techniques based on sinusoidal and third harmonic
reference wave with U-type carrier for the proposed DC-MLDCL inverter [15]. To generate m-level output, the
proposed DC-MLDCL inverter requires (m-1/2) references. Therefore, for one leg of the proposed inverter requires
three reference signals (Vref1, Vref2 and Vref3) to generate a seven level output phase voltage. These signals are
compared with U-type carrier wave (Vcarrier) to generate the pulses. Ideally, for a multiple reference based
modulation techniques, the modulation index (M) is given as
𝑀 = ( )
∗
(7)
Where ‘m’ represents the number of levels, hence for the one leg of the proposed DC-MLDCL inverter, the
modulation index (M) is given as
𝑀 =
∗
(8)
To demonstrate the principle of the proposed modulation technique, a seven-level inverter at M = 0.9 and mf = 20 is
shown in Fig. 4 and 5, for the multiple reference sinusoidal and third harmonic modulation signals respectively.

1797
Fig. 4. Multiple reference waveform using sinusoidal with U-type carrier
Fig. 5. Multiple reference waveform using third harmonic with U-type carrier
IV. SIMULATION RESULTS AND ANALYSIS
Simulation has been carried out to analyze the performance of the three phase sevel-level DC-MLDCL
inverter using multiple reference modulation techniques based on sinusoidal and third harmonic reference wave with
U-type carrier. The system parameters used to model and simulate the proposed DC-MLDCL inverter are shown in
Table III.
TABLE III. SYSTEM PARAMETERS
Parameter Value
Resistance Load 20 Ω
Inductance Load 10 mH
DC-Link voltage to MLI 440 V
Capacitor values 100 µF

1798
Switching frequency 5 kHz
Modulation index 0.7 to 0.9
A. Multiple reference modulation technique based on sinusoidal reference wave with U-type carrier:
Simulation results of proposed DC-MLDCL inverter using multiple reference based SPWM for three-phase inverter
for R and RL loads are shown in Figures 6-11 with a modulation index of 0.9.
i. For R load:
Fig. 6. Output line voltage of three phase DC-MLDCL inverter using SPWM
Fig. 7. Harmonic analysis of output line voltage for three phase using SPWM

1799
Fig. 8. Output line current of three phase DC-MLDCL inverter using SPWM
Fig. 9. Harmonic analysis of output line current for three phase using SPWM
Fig. 6 and 8 shows the three phase output line voltage and line current of proposed DC-MLDCL inverter with a
modulation index of 0.9 and Fig.7 and 9 shows the corresponding harmonic analysis, from the Fig’s 7 and 9 it is
observed that the harmonic distortion of 17.02 % is present in line voltage and line current of proposed DC-MLDCL
inverter using multiple reference based SPWM fed R-load.
ii. For R load:
Fig. 10. Output line current of three phase DC-MLDCL inverter using SPWM

1800
Fig. 11. Harmonic analysis of output line current for three phase using SPWM
Fig. 10 and 11 shows the three phase output line current and corresponding harmonic analysis of proposed
DC-MLDCL inverter with a modulation index of 0.9 fed RL-load using multiple reference based SPWM, from the
Fig’s 10 and 11 it is observed that the harmonic distortion of 2.91 % is present in line current of proposed DC-
MLDCL inverter.
B. Multiple reference modulation technique based on third harmonic reference wave with U-type carrier:
Simulation results of proposed DC-MLDCL inverter using multiple reference based third harmonic for
three-phase inverter for R and RL loads are shown in Figures 12-17 with a modulation index of 0.9.
i. For R load:
Fig.12. Output line voltage of three phase DC-MLDCL inverter using third harmonic
Fig. 13. Harmonic analysis of output line voltage for three phase using third harmonic

1801
Fig. 14. Output line current of three phase DC-MLDCL inverter using third harmonic
Fig. 15. Harmonic analysis of output line current for three phase using third harmonic
Fig. 12 and 14 shows the output line voltage and line current of proposed three phase DC-MLDCL inverter
with a modulation index of 0.9 and Fig.13 and 15 shows the corresponding harmonic analysis, from the Fig’s 13 and
15 it is observed that the harmonic distortion of 14.92 % is present in line voltage and line current of proposed DC-
MLDCL inverter using multiple reference based third harmonic reference fed R-load.
ii. For RL load:
Fig. 16. Output line current of three phase DC-MLDCL inverter using third harmonic

1802
Fig. 17. Harmonic analysis of output line current for three phase using third harmonic
Fig. 16 and 17 shows the three phase output line current and corresponding harmonic analysis of proposed
DC-MLDCL inverter with a modulation index of 0.9 fed RL-load using multiple reference based third harmonic
reference, from the Fig’s 16 and 17 it is observed that the harmonic distortion of 2.40 % is present in line current of
proposed DC-MLDCL inverter.
C. Comparison of simulation results and discussion:
In this study, simulation analysis of three phase output line voltage waveforms, line current waveforms and
corresponding harmonic analysis of proposed DC-MLDCL inverter fed R and RL loads using multiple reference
based SPWM and third harmonic reference modulation techniques are depicted in figs. 6 to 17 with a modulation
index of 0.9. Tables IV and Table V shows the fundamental components of three phase output line voltage (Vrms)
and output line current (Irms) fed R and RL loads for various modulation indices using proposed modulation
techniques. Tables VI and Table VII shows the corresponding harmonic analysis of three phase output line voltage
(Vrms) and output line current (Irms) fed R and RL loads for various modulation indices using proposed modulation
techniques.
TABLE IV. FUNDAMENTAL COMPONENTS OF VRMS AND IRMS FOR PROPOSED THREE PHASE DC-MLDCL INVERTER USING
MULTIPLE REFERENCE SPWM
Modulation
Index (M)
Fundamental Voltage (V) Fundamental Current (A)
R-load RL-load R-load RL-load
0.9 364.4 364.3 18.22 18.05
0.8 328.6 328.8 16.43 16.21
0.7 284.8 284.7 14.24 14.04
TABLE V. FUNDAMENTAL COMPONENTS OF VRMS AND IRMS FOR PROPOSED THREE PHASE DC-MLDCL INVERTER USING
MULTIPLE REFERENCE SPWM
Modulation
Index (M)
Fundamental Voltage (V) Fundamental Current (A)
0.9 415 415 20.75 20.61
0.8 379.1 379.1 18.96 18.81
0.7 329.5 329.6 16.47 16.36

1803
TABLE VI. HARMONIC DISTORTION OF VRMS AND IRMS FOR PROPOSED THREE PHASE DC-MLDCL INVERTER USING
MULTIPLE REFERENCE THIRD HARMONIC
Modulation
Index (M)
Voltage THD (%) Current THD (%)
0.9 17.02 17.07 17.02 2.91
0.8 18.62 18.64 18.62 3.52
0.7 21.68 21.76 21.68 3.92
TABLE VII. HARMONIC DISTORTION OF VRMS AND IRMS FOR PROPOSED THREE PHASE DC-MLDCL INVERTER USING
MULTIPLE REFERENCE THIRD HARMONIC
Modulation
Index (M)
Voltage THD (%) Current THD (%)
0.9 14.92 14.97 14.92 2.40
0.8 17.17 17.18 17.17 2.61
0.7 18.60 18.58 18.60 3.15
The proposed three phase DC-MLDCL inverter has been simulated and analysed for various modulation
indices for R and RL-loads. The simulation results with corresponding harmonic spectrum are presented and the
corresponding results are shown in Table IV to VII for the proposed three-phase DC-MLDCL inverter with different
modulation indices and it is found that, the harmonic level of output phase voltage and output phase currents are
increased by increasing modulation index and the number of levels are decreased by increasing the modulation
index. From the detailed harmonic analysis, it is inferred that the minimum THD is obtained for a modulation index
of 0.9.
D. Comparison of switching devices and number of levels:
The number of components required for m-level in a host of inverter topologies to obtain a required level of
output is presented in Table VIII to bring out the importance of proposed DC-MLDCL topology. Fig. 18 gives the
graphical representation for the comparison of required number of switches between the proposed DC-MLDCL and
the existing MLI topologies. From the simulation and comparative analysis it can be concluded that the proposed
DC-MLDCL inverter has superior advantages over existing MLI topologies.
TABLE VII. COMPONENT COUNT COMPARISON FOR THREE PHASE MLI’S
Topologies/
Components
Existing MLI Topologies
Proposed
DC-MLDCL
Diode Clamped Capacitor Clamped
Cascaded
H-Bridge
Main Switches 6(m-1) 6(m-1) 6(m-1) 3(m+3)
Main Diodes 6(m-1) 6(m-1) 6(m-1) 3(m+3)
Clamping diodes 6(m-3) 0 0 3(m-3)
Balancing capacitors 0 3(m-2) 0 0
DC bus capacitors 3(m-1) 0 3(m-1)/2 3(m-1)/2

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Fig.18. Comparison of required number of switches
VIII. CONCLUSION
The proposed three phase DC-MLDCL inverter can eliminate roughly half the number of
switches, clamping diodes, voltage splitting capacitors and gate drivers compared with their existing MLI
counterparts. The proposed DC-MLDCL inverter could still cost less due to less number of gate drivers because of
the extensively reduced number of components, which also leads to a less installation area and volume. The
proposed DC-MLDCL inverter used in power applications such as photovoltaic systems, back to back converters,
HVDC, FACTS, Reactive power compensation, UPS, etc.
ACKNOWLEDGEMENT
Authors would like to sincerely thank the Vice Chancellor and Management of M.S.Ramaiah University of
Applied Sciences, Bangalore for providing all facilities required to carry out this research work.
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