Nanotechnological Enhancement to Moore's Law

COMSATS University Islamabad
Department of Physics
Nanoenhancement to Moore’s Law
Mirza Akbar Ali
SP18-BPH-078
Introduction to Nanoscience and Technology
Dr. Hamza Qayyum
June 19, 2021

Contents
1. Introduction
Moore’s Law
History of Moore’s Law
2. Current Barriers to Moore’s Law
Power and Heat Sink
Tunneling Effect
Quantum Limit to Moore’s Law
3. Nanoenhancement to Moore’s Law
DNA Scaffolding Tiny Circuit Board
3D Trigate FinFet
Spintronics
Single Atom Transistor
4. Future of Moore’s Law
Key Future Technologies
Past, Present and Future of Moore’s Law
Conclusion
Mirza Akbar Ali SP18-BPH-078 Nanoenhancement to Moore’s Law 2 / 20

Introduction
Current Barriers to Moore’s Law
Future of Moore’s Law
Moore’s Law
Moore’s Law
Figure 1: Gordon Earle Moore cofounder of Intel

Introduction
Moore’s Law
Invention of ENIAC in 1946 (Electronic Numerical Integrator and
Computer)
Need of faster computers
Invention of Transistor in 1947
Invension of TRADIC in 1954 (TRAnsistor DIgital Computer or
TRansistorized Airborne DIgital Computer)
The complexity for minimum component costs has increased at a rate
of roughly a factor of two per year.
Moore observed trend of increase in computation power over a decade
from 1965 to 1975

Introduction
Moore’s Law
Number of transistors on a chip doubles every 2 years
Not a Natural Law
Based on observation and production of more advanced chips
In 1995, Moore observed that semiconductor cannot continue its
growth indefinitely
Moore’s law set goals for semiconductor and computer industry
Moore said in 2008, a decade more or a decade and a half. We would
hit something fundamental

Introduction
Power and Heat Sink
Tunneling Effect
Power and Heat Sink
Chips are used in all intelligent devices
Being electronic devices they require power supply
Mobile devices require power storage devices
Hand held devices are required to have low weight which impose
restriction on size of device and ultimately on chip and battery
Mobile devices must produce minimum heat possible to function
efficiently
Production of more power storage devices with light weight and low
heat production imposes a barrier on Moore’s law

Introduction
Power and Heat Sink
Tunneling Effect
Tunneling Effect
It was predicted by Zhirnov et al. that semiconductor makers will not
be able to shrink size of transistor after 20211
Currently 5 nm and 7 nm chips are being produced and used
Apple hopes to start batch production of 3 nm chips by the end of 2021
Size of transistor on chip decreased from 32 nm in 2012 to 5 nm in 2020
Decreasing the size of gate beyond 5nm causes quantum tunneling
effect
Electron will simply pass through the gate without needing any voltage
because the width of gate will be very small
1Victor V Zhirnov et al. “Limits to binary logic switch scaling-a gedanken model”. In: Proceedings
of the IEEE 91.11 (2003), pp. 1934–1939

Introduction
Power and Heat Sink
Tunneling Effect
2D Planer Gate Example
Figure 2: Schematic Diagram of 2D planer transistor2
2Schematic diagram not to scale

Introduction
Power and Heat Sink
Tunneling Effect
Moore’s Law can be written in mathematical form as
n2 = n12[(y2−y1)/2]
(1)
This equation predicts the number n2 of transistors in any given year
y2 from the number n1 of transistors in any other earlier year y1.
Characteristic dimension or length L of a transistor is inversely
proportional to the number of transistors on an IC.
Equation 1 can be re written as
1
L2
=

1
L1

2[(y2−y1)/2]
(2)

Introduction
Power and Heat Sink
Tunneling Effect
Smallest element in a typical transistor is an electron. Characteristic
length of electron can be calculated as
λc = h/mec = 2.4263 × 10−12
m (3)
L2 = λc, L1 = 5 nm and y1 = 2021
Putting ∆y = y2 − 2021 and solving for ∆y by taking natural log gives
∆y = 22.0179
y2 = ∆y + y1 = 22.0179 + 2021 ≈ 2043
2036 was predicted as quantum limit year to Moore’s law by Powell in
his proceedings in 20083
if electrons were implemented as the smallest
quantum computing transistor element.
3James R Powell. “The quantum limit to Moore’s law”. In: Proceedings of the IEEE 96.8 (2008),
pp. 1247–1248

Introduction
3D Trigate FinFet
Spintronics
A semiconductor chip cannot exist without printed circuit board (PCB)
Figure 3: IBM tiny circuit board showing low concentration of triangular DNA origami binding to
wide lines on a lithographic patterned surface with 500 nm scale bar4.
4Ryan J Kershner et al. “Placement and orientation of individual DNA shapes on lithographically
patterned surfaces”. In: Nature Nanotechnology 4.9 (2009)

Introduction
3D Trigate FinFet
Spintronics
3D Trigate FinFet
Figure 4: Planer 2D transistor(32 nm) on left and 3D Tri-Gate FinFet(22 nm) on right5.
5Jerry Wu et al. “A nanotechnology enhancement to Moore’s law”. In: Applied Computational
Intelligence and Soft Computing 2013 (2013)

Introduction
3D Trigate FinFet
Spintronics
FinFet Performance
Figure 5: The measurement results show 37 % increase in performance at low voltage when compared
to 32 nm 2D transistors and consume half the power at the same performance level as 32 nm 2D
transistors. 6
6Wu et al., “A nanotechnology enhancement to Moore’s law”

Introduction
3D Trigate FinFet
Spintronics
Spintronics
All our devices are working on charge of electron
Spintronics technology make use of electronic spin or magnetic field
that results from electronic spin.
Figure 6: Spin Transistor used in MRAM 7

Introduction
3D Trigate FinFet
Spintronics
Electronics vs Spintronics
Electronic Devices Spintronic Devices
Based on the properties of
charge of electron
Based on intrinsic property
of spin of electron
Classical Property Quantum Property
Materials: Conductors and
Semiconductors
Materials: Ferromagnetic
Materials
Speed is limited and power
dissipation is high
Based on direction of spin
and spin coupling, high
speed
Table 1: Difference between Electronic and Spintronic Devices

Introduction
3D Trigate FinFet
Spintronics
Our current semiconductor industry is based on shrinking the size of
transistor
How much we can shrink the size of a transistor?
Fuechsle et al. devised single atom transistor by making use of
scanning tunneling microscopy and hydrogen resist lithography
Figure 7: Schematic diagram of single atom transistor. One blue sphere is 0.2 nm across.
7Martin Fuechsle et al. “A single-atom transistor”. In: Nature nanotechnology 7.4 (2012),
pp. 242–246

Introduction
Conclusion
Device Advantage Disadvantage
3D Transistor Small Size,
Low Power
Will face tunneling effect is-
sue
Spintronics Small Size,
Low Power
Control of magnetic field vs
spin polarized current
CNT Small Size,
High Speed
Placement of nanotubes in a
circuit is difficult, control of
electrical properties of CNTs
is difficult
SET Small Size,
Low Power
Sensitive to background
charge instability. High
resistance and low drive
current.

Introduction
Conclusion
Device Advantage Disadvantage
Quantum
Dots
Small Size,
High Speed
Difficult to make multi-
ple levels of interconnec-
tion over long distances.
Room temperature opera-
tion is difficult. New com-
putation algorithm required.
No method to set the initial
state of the system yet. Sin-
gle defect in line of dots will
stop propagation.
Quantum
Computing
High comput-
ing speed for
some certain
problems
Time frame for which infor-
mation may exist might not
be long enough to be pro-
cessed.

Introduction
Conclusion
Figure 8: Moore’s law history, possible future, limiting factors and Dow Jones Industrial Average from
1971 to 2011 8.

Introduction
Conclusion
Conclusion
Moore’s law is not a physical law
It is based on observations and industrial progress
We discussed Moore’s law as matter of transistor density on a chip
We could end this law here by increasing the area of chip and placing
more transistors on it
But we have focused on scientific barriers
Will Moore’s law end?

Nanotechnological Enhancement to Moore's Law

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