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 Here we present methods in teaching advanced
computer architecture courses. These methods
include presenting fundamental computer
architecture issues using e-learning; employing
visual aids to teach fundamentals concepts like
Caches, pipelining and scheduling.
2
 Advance Computer Architecture usually combines software and
hardware approaches that increase the performance of
microprocessor design.
 Main concepts in this courses includes measuring performance,
Instruction Set Design, Memory Hierarchy and Caches, Pipelining
and its Hazards, Instruction Level Parallelism, I/O storage, and
latest contemporary computer architecture issues.
 By using these concepts this course also presents the quantitative
approaches to measure the feasibility.
3
 These approaches also measure the performance emphasizing on
the differences between hardware and software approaches.
 There are several books available on Computer Architecture
concepts.
 Hennessy and Patterson’s are the one who gives a comprehensive
documentation on most of computer architecture topics.
4
Concepts for e-learning are
 Cache Associativity
 Superscalar microprocessors.
 Dynamic scheduling algorithms.
5
 Definition
 It is the easy control of direct mapping cache and a fully associative
cache.
 Each cache location can have more than one pair of tag and data
item that resides at same location in cache memory.
 If one cache location is holding two pair of tag and data item that is
called two-way set associative cache.
6
 A 2-way set associative cache
having 8 lines will have 4 sets
and each set has two lines.
 Figures show the set
associativity explain
 This approach presents the
cache to be split into number of
sets and each set has equal
number of lines.
7
Visual aid made the concepts easy to understand and we
can easily explained our point by adding visual aids and
graphics
 Pipelining and its hazards
 Superscalar design
 Instruction Level Parallelism
 Dynamic Scheduling.
8
 Pipelining
 A Pipelining is a series of stages, where some work is done at each
stage in parallel.
 The stages are connected one to the next to form a pipe
instructions enter at one end, progress through the stages, and exit
at the other end.
 pipelining hazards
 Prevent the next instruction in the instruction stream from
being executing during its designated clock cycle.
 Hazards reduce the performance from the ideal speedup
gained by pipelining
9
 DLX is simple pipelining
architecture for CPU.
 This is the seven clock cycle
that is required to execute the
instruction
K+(n-1) cycle
 The pipeline could be also
shown in terms of cycles,
meaning display the events at
each clock cycle
DLX pipeline Starting stage
DLX pipeline 2nd instruction
10
Pipelining hazards
 For pipeline hazards, the visual aid could show bubbles
inserted in the pipeline figure show bubbles and data
forwarded using arrows.
11
 The concept of superscalars can also be explained with the
visual aids.
 This figure show a 2-way issues for a DLX superscalar
machine
 where one pipeline is assigned for integer and the other for
floating-point operations. Note that floating-point operation
takes 3 cycles to execute.
12
 Definition
 Instruction level parallelism (ILP) is a measure of how
many of the instructions in a computer program can
be executed simultaneously.
 In Dynamic scheduling hardware determines which
instructions to execute,
 ILP and Dynamic Scheduling is made easy by using
visual aid.
13
Tomasula’s algorithm
 It is a computer architecture hardware algorithm for
dynamic scheduling of instructions.
 It allows out-of-order execution and enables more efficient
use of multiple execution units.
 At cycle =0 five instructions
scheduled
 Student re-write each cycle
result.
 This idea involve the
student in the process of
learning and solving the
problem.
14
 Advanced Computer Architecture is
rich with new topics that are in the
research stage.
 The student must be aware of these
topics before completing any advanced
computer architecture course.
15
 Advanced Computer Architecture is rich with
advanced topics. The most advanced way of
learning is through visual aids and e-learning.
Future trends in teaching Computer Architecture
may lead to e-learning at a distance.
16
 http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/ha
zards.html
 https://en.wikipedia.org/wiki/Tomasulo_algorithm
 https://kb.iu.edu/d/aett
 http://www.pcguide.com/ref/mbsys/cache/funcMapping-
c.html
17

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Integrating research and e learning in advance computer architecture

  • 1.
  • 2.  Here we present methods in teaching advanced computer architecture courses. These methods include presenting fundamental computer architecture issues using e-learning; employing visual aids to teach fundamentals concepts like Caches, pipelining and scheduling. 2
  • 3.  Advance Computer Architecture usually combines software and hardware approaches that increase the performance of microprocessor design.  Main concepts in this courses includes measuring performance, Instruction Set Design, Memory Hierarchy and Caches, Pipelining and its Hazards, Instruction Level Parallelism, I/O storage, and latest contemporary computer architecture issues.  By using these concepts this course also presents the quantitative approaches to measure the feasibility. 3
  • 4.  These approaches also measure the performance emphasizing on the differences between hardware and software approaches.  There are several books available on Computer Architecture concepts.  Hennessy and Patterson’s are the one who gives a comprehensive documentation on most of computer architecture topics. 4
  • 5. Concepts for e-learning are  Cache Associativity  Superscalar microprocessors.  Dynamic scheduling algorithms. 5
  • 6.  Definition  It is the easy control of direct mapping cache and a fully associative cache.  Each cache location can have more than one pair of tag and data item that resides at same location in cache memory.  If one cache location is holding two pair of tag and data item that is called two-way set associative cache. 6
  • 7.  A 2-way set associative cache having 8 lines will have 4 sets and each set has two lines.  Figures show the set associativity explain  This approach presents the cache to be split into number of sets and each set has equal number of lines. 7
  • 8. Visual aid made the concepts easy to understand and we can easily explained our point by adding visual aids and graphics  Pipelining and its hazards  Superscalar design  Instruction Level Parallelism  Dynamic Scheduling. 8
  • 9.  Pipelining  A Pipelining is a series of stages, where some work is done at each stage in parallel.  The stages are connected one to the next to form a pipe instructions enter at one end, progress through the stages, and exit at the other end.  pipelining hazards  Prevent the next instruction in the instruction stream from being executing during its designated clock cycle.  Hazards reduce the performance from the ideal speedup gained by pipelining 9
  • 10.  DLX is simple pipelining architecture for CPU.  This is the seven clock cycle that is required to execute the instruction K+(n-1) cycle  The pipeline could be also shown in terms of cycles, meaning display the events at each clock cycle DLX pipeline Starting stage DLX pipeline 2nd instruction 10
  • 11. Pipelining hazards  For pipeline hazards, the visual aid could show bubbles inserted in the pipeline figure show bubbles and data forwarded using arrows. 11
  • 12.  The concept of superscalars can also be explained with the visual aids.  This figure show a 2-way issues for a DLX superscalar machine  where one pipeline is assigned for integer and the other for floating-point operations. Note that floating-point operation takes 3 cycles to execute. 12
  • 13.  Definition  Instruction level parallelism (ILP) is a measure of how many of the instructions in a computer program can be executed simultaneously.  In Dynamic scheduling hardware determines which instructions to execute,  ILP and Dynamic Scheduling is made easy by using visual aid. 13
  • 14. Tomasula’s algorithm  It is a computer architecture hardware algorithm for dynamic scheduling of instructions.  It allows out-of-order execution and enables more efficient use of multiple execution units.  At cycle =0 five instructions scheduled  Student re-write each cycle result.  This idea involve the student in the process of learning and solving the problem. 14
  • 15.  Advanced Computer Architecture is rich with new topics that are in the research stage.  The student must be aware of these topics before completing any advanced computer architecture course. 15
  • 16.  Advanced Computer Architecture is rich with advanced topics. The most advanced way of learning is through visual aids and e-learning. Future trends in teaching Computer Architecture may lead to e-learning at a distance. 16
  • 17.  http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/ha zards.html  https://en.wikipedia.org/wiki/Tomasulo_algorithm  https://kb.iu.edu/d/aett  http://www.pcguide.com/ref/mbsys/cache/funcMapping- c.html 17