5. FPGA Definition
• Field-Programmable Gate Arrays (FPGAs) are a recent kind of
programmable logic devices. They allow the implementation
of integrated digital electronic circuits without requiring the
complex optical, chemical and mechanical processes used in a
conventional chip fabrication
• FPGAs can be embedded in traditional system design flows to
perform prototyping and emulation tasks. In addition, they
also enable novel applications such as configurable computers
with hardware dynamically adaptable to a specific problem
• FPGA: Circuits that can be modified or configured by an end-
user
7. Basic CLB structure
• Four slices are grouped by pairs, and each pair is organized in a
column with independent carry chain
• Configurable switch matrix: There are connections between the
horizontal and vertical routing resources to allow signals to
change their routing direction
The basic building block of a Configurable Logic Block
8. Basic LC structure
Look Up Tables (LUT) are the kind of logic that is used in
SRAM based FPGAs. Basically, each LUT is a collection of
single bit memory cells storing individual bit values in each of
the cells
LUT
9. I/O Blocks
IOBs provide a bidirectional programmable interface between
the output and the internal structure of the FPGA device
Routing possibilities for an I/O Blocks
• Input signal
• Output signal
• High impedance signal
Each signal has two storage elements that can be used as
registers or latches
Block RAM
The BRAM is a configurable memory module that attaches to
a variety of BRAM interface controllers [1]. The BRAM can
be used to store big amounts of data
10. Run-time Reconfiguration Tools for Xilinx FPGAs
Xilinx ISE
• Partially configurable circuits can be implemented using
Modular Designs
• Special macros and constraints must be applied to
partially reconfigurable circuits
• Xilinx recommends using modular designs with
simple circuits only
11. Advantages of Run-time Reconfiguration
Run-time Reconfiguration benefits :
• Reduced power consumption
• Hardware reuse (E.g reduced memory requirements)
• Obsolescence avoidance
• Flexibility
• Reduced time to reconfigure
• Application Portability
12. Advantages of Run-time Reconfiguration
Obsolescence avoidance
One of the most touted advantages of FPGAs in military
designs is the ability to “future proof” applications through
the careful application of hardware and software design, and
the careful use of third-party application program interfaces
(APIs) and design applications
Application Portability
One of the goals of a run-time configurable system is to
encapsulate the reconfigurable system into a portable
application or avionics pod
13. Xilinx PR Implementation Flow
HDL Design Description
HDL Synthesis
Set Design Constraints
Placement Analysis
Implement Static Design and
PR Modules
Merge
Final Bitsreams
Manual
steps
PRR Challenges
• Complicated design flow
• Requires manual intervention and
knowledge about target device
• Can decrease the performance of the
system as compared to full
configuration if system design is not
carefully considered.
Partial Run-time
Reconfiguration (PRR)
Challenges
14. • Run-time reconfigurable systems utilize reconfigurable
hardware better
• Hardware and software based techniques can be applied to
minimize reconfiguration overhead
• Still, a considerable research effort is onging to improve the
tools to provide an ever increasing efficieny and ease of use
• Open area for optimization exist for different aspects, such
as power consumption, hardware reuse, Flexibility, Reduced
time to reconfigure, Application Portability and small bit-
stream files
CONCLUSION
Editor's Notes
RTR support in Xilinx ISE
Smaller Bitstreams sizes will help in
Reduced power consumption
Reduced memory requirements
Reduced time to reconfigure
Draw backs of run-time reconfiguration
Entire fabric is reconfigured even for slight design changes
System execution stalls completely
Time be load a design onto the fabric from the external memory (reconfiguration time) increases with bitsream size
Run-time reconfiguration is enhanced by run-time partial reconfiguration which mitigate these drawbacks
1. Device too small for complex designs
2. Big full bitstreams (long reconfiguration time)
3. Complete system opera tion is halted prior to reconfiguration
Application Portability
Complicated chip load and reload schemes both negate portability and lower the
reliability of a system where chip reconfiguration relies on time-critical interaction with external processors.
Requires manual intervention and knowledge about the target device