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Danmarks tekniske Universitet, Afdelingen for Elektroteknik og Fysik,
har den?. ? 2000 indstilletdenne Ph.D.-afhandlingtilo entligt forsvar.
Forsvaret nder sted den 30. 6 2000 kl. ? i Auditorium ? pa DTU.
c 2000 Eddie Hjelm Pedersen
ISBN
Printed by Druk. Tan Heck, Delft, The Netherlands
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Contents
5. Conclusion 111
Acknowledgements 113
Bibliography 115
A. Glossary 137
B. Process sequences 139
B.1. First electroplating process scheme . . . . . . . . . . . . 140
B.2. Second electroplating process scheme . . . . . . . . . . . 141
B.3. Evaporation scheme . . . . . . . . . . . . . . . . . . . . 143
C. Evolver model 145
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Resume in English
Motivated by the ongoing development of a Si-based microphone for
a Complete-In-the-Ear-Canal hearing-aid device, this thesis describes
the research and development of a uxless ip-chip soldering techno-
logy for hybrid microsystem integration.
The concept of microsystem integration and packaging are discussed
together with an evaluation of solder bump ip-chip technology.
Fluxless ip-chip soldering is essential for MEMS and for photonic
devices as uxes and their cleaning agents may clog small objects
like membranes, or ventilation holes, or contaminate optical facets
in micro-opto-electronic devices. In addition, uxes and their cleaning
agents expose a serious threat to the environment.
However, uxless ip-chip technology can not use the tackyness of
uxes to keep aligned and stacked components together prior to re-
ow soldering. The development of a prebondingscheme whichenables
mechanically stable bonds, thereby markedly enhancing chip handling
and transportation, is realized and presented in this thesis.
Self-alignment by surface tension forces of molten solder bumps is an
attractive feature of ip-chip assembly since it reduces the required
accuracy of pick-and-place bonding to typically 25 m. Fluxes are
used in the ip-chip industry as self-alignment is impeded by oxides
covering the solder surface. Flux-assisted and uxless ip-chip tech-
nologies are compared and evaluated in this work in order to reveal
di erences in the self-alignment characteristics. First trial transferral
of uxless self-alignment experiments from laboratory conditions to
nitrogen purged industrial re ow is presented.
Surface science techniques is used to obtain a deeper understanding of
the properties of solder oxide obtain a deeper understanding . High de-
positionrates and low pressure proves to be very important parameters
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Abstract in English
in order to avoid oxidation of solder during evaporation. Evaporated
solder is re own in high vacuum and a native oxide is formed on the
surface when exposed to air. The growth properties of solder oxide
during subsequent heating in air is investigated by sputter depth pro-
ling. The native oxide formed on solder, when evaporated at high
rates and at a low pressure, protects the surface from further oxida-
tion during subsequent re ow in air.
X-ray spectroscopy show that plasma assisted dry solder treatment
converts solder oxide into oxy uoride. But sputter depth pro ling
proves at the same time that the extreme thin shell like native solder
oxide surface is destroyed during plasma treatment and that uor and
oxygen are incorporated several m into the solder surface.
A hermetic sealing is of high importance for many microelectrome-
chanical systems. The simulation and characterization of a hermetic
solder seal ring for a Si-based microphone is presented using the above
mentioned new uxless prebonding technology.
Computer simulations indicate in accordance with experiments that
the geometry of the seal ring metallization proves to be a crucial factor
in order to prevent local accumulation of solder during re ow. Various
seal ring designs are evaluated in order to nd a stable geometry.
Design rules based on computer simulation, regarding optimal seal
ring parameters in order to compensate for di erences in solder height,
are proposed.Experiments and simulations reveal that the solder ring
is stable during re ow when it wets top and bottom metallization of
the joined parts simultaneously. Hermetic packages are thus formed
by prebondingas-deposited electroplated solder, followed by re ow sol-
dering in an inert ambient, without using liquid or gaseous uxes. The
elemental composition of prebonding residues are investigated with
scanning Auger microscopy. Hermeticity of the micro-packages after
re ow is proven using MIL-STD-883E.
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Resume pa dansk
Denne Ph.D.-afhandling er udarbejdet som led i erhvervelsen af Ph.D.-
graden ved Danmarks Tekniske Universitet. Afhandlingen beskriver
forskningog udviklingaf usmiddelfri( uxless) ip-chipsolder-teknologi
til integration af hybride mikroelektromekaniske systemer (MEMS).
Arbejdet er motiveret af udviklingen af en silicium-baseret mikrofon
der skal indga i et h reapparat som sidder helt inde i rekanalen pa
brugeren.
Arbejdet er udf rt ved Mikroelektrionic Centret, Danmarks Tekniske
Universitet, i perioden fra d. 1 marts 1997 til d. 31 August 2000
i samarbejde med ere industrielle partnere og forskningsinstitutter.
Arbejdet har endvidere v ret relateret til to EU-projekter, ben vnt
henholdsvis Mikrosystem Centret (MSC) og High Performance Inter-
connect and Stacking (HISTACK).
Konceptet vedr rende integrering samt pakningaf mikrosystemer bliver
indledningsvist diskuteret sammen med en evaluering af solder bump
ip-chip teknologi.
Flusmiddelfri ip-chip soldering har afg rende betydning for MEMS
og optiske componenter. Dette skyldes at usmidler, og de hermed
associerede rensemidler, kan tilstoppe sma objekter som membraner
eller ventileringshuller i mirosystemer, samt forurene optiske facetter
i mikro-elektrooptiske komponenter. Flusmidler og deres rensemidler
udg r ydermere en potentiel fare for milj et.
Men, usmiddelfri ip-chip teknologi besv rlig res betydeligt af at
usmidlers kl bee ekt, der normalt benyttes til at holde stakkede og
oplignede (aligned) komponenter sammen inden termisk re ow solder-
ing (smeltning), ma undv res. Udviklingen af en methode, ben vnt
prebonding,der frembringermekaniskstablilemetalbindingerved hj lp
af tryk og varme, der er lavere end smeltepunktet af solder-metallet,
presenteres i denne afhandling. Metoden forenkler handteringen og
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Resume pa dansk
transport af usmiddelfri ip-chip stakkede komponenter betydeligt.
Auto-opligning (self-alignment) af usmiddel-baseret og usmiddelfri
ip-chip teknologi sammenlignes og evalueres for at unders ge forskelle
i auto-opligningsegenskaberne. Indledende fors g pa at overf re us-
middelfri auto-opligningseksperimenter fra laboratorieforhold til in-
dustrielle N2-ovne diskuteres.
En hermetiskforseglinger af afg rende betydningfor mange mikroelek-
tromekaniske systemer. I den f rn vnte silicium-baserede mikrofon
indgar en solder forseglings-ring som beskyttelse imod korroderende
omgivelser samt for at skabe et akustisk referencekammer. Simulering
og karakterisering af en hermetisk solder-forsegling, konstrueret vha.
den i dette arbejde etablerede usmiddelfri prebonding-teknologi gen-
nemgas.
Computersimuleringer viser i overensstemmelse med eksperimenter at
geometrien af forseglingsrings-metalliseringen er en afg rende faktor
for at forhindre lokal akkumulering af solder under termisk re ow.
Forskellige geometrier bliver evalueret i fors get pa at nde et stabilt
design. Eksperimenter og simuleringer paviser at solder-forseglingsrin-
gen er stabil nar solderen er i kontakt med metalliseringenpa bade chip
og substrat samtidigt. Hermetiske mikropakker bliver derfor realiseret
ved at prebonde elektropletteret solder, efterfulgt af re ow soldering
i en inert atmof re, uden at anvende ydende eller gasformige us-
midler. Grundstof-sammens tningen af prebonding-aftryk unders ges
vha. skanning Auger mikroskopi, og hermeticiteten af mikro-pakkerne
testes efter re ow if lge MIL-STD-883E.
Designregler baseret pa computersimulationer, vedr rende de opti-
male forseglingsrings-parametre, frems ttes som en metode til at kom-
pensere for forskelle i h jden af henholdsvis solder bumps og solder
forseglingsringe.
Egenskaberne af solder oxid analyseres med diverse surface science
teknikker. H je deponeringsrater og et lavt tryk viser sig at v re
afg rende parametre i for get pa at undga oxidering af solder under
padampning. Padampet solder bliver smeltet i h jt vakuum og et na-
tivt oxid dannes pa over aden nar denne efterf lgende uds ttes for
luft. V ksten af solder-oxidet under efterf lgende re ow i luft un-
ders ges med Argon-ion dybdepro lering.
R ntgenspektroskopi (XPS) viser at plasma assisteret t r solder be-
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D
handling (PADS) omdanner solder oxid til oxy uorid. Ar-ion dybde-
pro lering viser dog samtidig at savel uor som oxygen bliver indar-
bejdet ere i solder-over aden under PADS behandling hvorved det
beskyttende oxid ndres.
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Preface
This thesis has been written as a partial ful llment of the require-
ments for obtaining the Ph.D.-degree at the Technical University of
Denmark (DTU). The Ph.D.-project has been conducted at Mikroelek-
tronik Centret (MIC) at DTU in the period from 1. March 1997 to
31. August 2000.
The Ph.D-project has been carried out at MIC in collaboration with
several industrial partners and research institutes. These include De-
partment of Physics 1] and Department of Manufacturing Engi-
neering 2] at DTU, and the company Grundfos DK A/S 3]. The
work has furthermore been related with two projects named Microsys-
tem Centret (MSC) and High Performance Interconnect and Stacking
(HISTACK) respectively. MSC, which ended in October 1999, was a
danish private/public collaboration project involving the hearing aid
components manufacturer Microtronic A/S 4], the technology ser-
vice institute DELTA (Danish Electronics, Lights & Acoustics) 5]
and Mikroelektronik Centret 6] as a research center for microtech-
nologies.
The HISTACK project, which is funded by the European Union under
the ESPRIT programme, was initiated during the MSC project. HIS-
TACK involves MIC, Microtronic A/S, DELTA, CSEM (Centre Suisse
dElectronique et de Microtechnique) in Neuch^atel, Switzerland 7],
LETI (Laboratoire dElectronique de Technologie et dInstrumentation)
in Grenoble, France 8] and the company BALTEADISK in Arnad,
Italy 9].
Part of the work has been performed during a research stay from June
to September 1999 at LETI in Grenoble, France.
The Ph.D.-project has been supervised by:
Dr. Siebe Bouwstra: Main supervisor for the project.
Dr. Jochen Kuhmann: Co-supervisor.
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Preface
Part of the results obtained within the project have been presented in
the following publications:
E.H. Pedersen and J.F. Kuhmann. A New Approach to Fluxless
Flip-Chip Soldering. EuPac '98, Nurnberg, Germany, June
1998: 40{42. (Oral presentation)
J.F. Kuhmann and E.H. Pedersen. Fluxless FC-soldering in O2-
purged ambient. 1998 Proceedings. 48th ECTC: 256-258.
P.T. Tang, E.H. Pedersen, G. Bech-Nielsen and J.F. Kuhmann.
Tin-Silver Alloys for Flip-Chip Bonding Studied with a Rotating
Cylinder Electrode. Electrochem Soc. of Japan, 196th meeting
of the Electrochemical Society. Honolulu, 17-22 October (1999):
256-258.
E.H. Pedersen, P. Rombach, M. Heschel and J.F. Kuhmann.
Flip-Chip Hermetic Packaging for MEMS. Eurosensors 2000.
Copenhagen, 27-30 August (2000): 247-248
Best Poster Award, 2nd price.
Eddie Hjelm Pedersen
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Symbol index
In the following list are included symbols of constants, variables and
functions used in this thesis.
Symbol Description
ai Activity
Optical ber axis o -set
d Collision diameter
Df Wetting driving force
EK Chemical energy shift in Auger spectra
E Energy of excitation source
E0 Standard electrode potential
Ea Activation energy
EF The Fermi level
e Electronic charge
F Faradays constant
Surface tension
hI As-deposited solder height
hR Solder height after re ow
Wetting angle
k Rate constant
kB Boltzmann's constant
Mean free path
Coupling loss
m Mass of a single molecule or atom
MW Molar mass
NA Avogadro's constant
Ng Gas density
NX Concentration of element X
P Pressure
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Preface
Symbol Description
P Pressure
Q Reaction quotient
R Ideal gas constant
s Density of adsorption sites
Collision cross-section
SX Relative atomic sensitivity factor
T Temperature
m Monolayer deposition time
v Mean speed
w Width of under bump metallization
Wa Work of adhesion
z Ionic valence
Z Gas ux
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1. Introduction
This thesis is divided into 5 chapters.
Chapter 1 describes the concept of uxless ip-chip (FC) soldering for
hybrid microsystem integration. The chapter starts with a presenta-
tion of microelectromechanical systems, hybrid microsystems, and a
brief description of packaging functions and levels. This is followed by
a description of the characteristics regarding monolithic and hybrid
integration of microsystems. FC for microsystems is discussed in the
3rd section of this chapter, together with an introduction to the con-
cept of FC soldering and the involved technologies. Finally are the
motivation and goals for this Ph.D.-project outlined.
The subsequent chapters 2 to 4 present the results achieved during
the project. All chapters start with a brief survey of relevent results
obtained by other researchers.
Chapter 2 describes the results obtained regarding prebonding and re-
ow soldering. A scheme by which a soldered chip can be cold welded
to metallized substrate with matching footprints is presented and eval-
uated. The self-alignment properties of solder bumps under various
conditions and deposition technologies are furthermore investigated
and discussed.
The simulation and characterization of a hermetic seal ring is outlined
in chapter 3. Using Surface Evolver various seal ring geometries are
evaluated, and design rules regarding dependency of re own solder
height on wettable footprint geometry are proposed. The realization
of a hermetic solder seal ring using chip-to-wafer prebonding and re-
ow soldering is presented.
Surface science investigations applied to ip-chip soldering is described
in chapter 4. The protective properties of native solder oxide is illu-
minated as well as the oxide conversion of SF6-plasma treated solder
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Introduction
surfaces. The in uence of di erent substrates on solder dewetting
properties is nally analyzed.
The thesis is summarized in chapter 5.
1.1. Hybrid integration for microsystem
packaging
Microelectromechanical systems (MEMS) consist in the most general
form of independent microdevices combining electrical and mechani-
cal components, that convert physical parameters to or from electrical
signals 10]. More speci cally microfabrication technology enables mi-
crodevices, which individually can sense, control and actuate on the
micro scale.
Hybrid microsystems result from integration of independent MEMS
devices with application speci c integrated circuits (ASIC) to create
increasingly complex systems, with dimensions ranging from subcen-
timeters to submicrometers, that can accomplish advanced functions.
However, fabrication of hybrid microsystems is not only about minia-
turization. The technology has introduced a new paradigm for design-
ing devices and systems and is a highly interdisciplinary eld involving
many areas of science and engineering 11{13].
Fabrication of MEMS comprises the use of a set of manufacturing tools
based on batch thin and thick lm lithography, techniques which are
commonly used for silicon processing of integrated circuit (IC), as well
as surface and bulk micromachining fabrication techniques 1.
The advantages of MEMS devices over their macro-world counterparts
are outstanding:
Using microfabricationtechnology, MEMS are inherentlysmaller,
lighter and faster than their macroscopic counterparts.
Local intelligence can be integrated directly on the MEMS de-
vice.
Due to the short electrical leads and close loops, electrical para-
sitics are decreased and operational speed is increased.
1M. Madou has published an excellent book covering these techniques 14].
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1.1. Hybrid integration for microsystem packaging
Batch processing of devices minimizes single die handling and
makes MEMS potentially highly cost competitive to convention-
ally manufactured devices that perform the same functions.
1.1.1. Packaging functions
The achievement of microsystems will depend primarily on the phys-
ical performance of internal elements. However, like in the integrated
circuit (IC) industry it is not the MEMS alone that determines the
performance, and size, of the microsystem. The way in which the de-
vice is packaged, and how it communicates with surroundings through
an input/output (I/O) system of interconnects equally in uences per-
formance, size and price. Challenges related to the development of
new packaging, assembly, and testing technologies must consequently
be overcome before success with commercial products is achieved.
IC packaging provides the following functionality to devices ( g. 1.1):
provide a path for the electrical current that powers the circuits
on the chip
distribute the signals on and o -chip
remove the heat generated by the devices
electromagnetic shielding
mechanical support and protection of the chip from hostile en-
vironments, vibration and during handing
MEMS devices must furthermore frequently physically interact with
the environment. The encapsulation must therefore also provide a de-
ned access for sound, electromagnetic elds, gases, uids and chemi-
cals. During their use MEMS will often be exposed to harsh operating
conditions. The delicate MEMS and its embedded circuitry are thus
very dependent on the package for support and protection. Finally,
MEMS are application speci c, and the packaging and assembly cost
can account for 50-90 % of the MEMS manufacturing cost 16]. Re-
search e orts in microsystem integration, and particularly in the area
of microassembly and packaging are consequently of high importance
for achievement of commercial success.
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Introduction
Figure 1.1.: Four major functions of a package. From 15, Chapter 1].
1.1.2. Packaging levels
To illustrate the di erent packaging levels in general, an example of
the package hierachy in a computer is given in g. 1.2. MEMS packag-
ing today is still very diverse but includes all these levels of packaging
as well.
Packaging is considered to begin at the interfaces to the outer surfaces
of the MEMS device, referred to as a rst-level-packaging. This is the
most important and diversi ed level of packaging. It consist of the sig-
nal and power/ground wires provided between the chips and the com-
mon circuit base, which is referred to as the second-level-packaging
2, onto which the MEMS devices are assembled. The third-level-
packaging may either be the outer shell on a small piece of equipment
(hand-held calculators, mobile phones etc.) or a pluggable unit to en-
hance funtions of larger equipment (the mother board in a desktop
computers for instance).
2Often printed circuit boards (PCB) or card.
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1.2. Monolithic and hybrid integration
Figure 1.2.: The rst three levels of electronic packaging. (COB): chip-on-board.
From 17, Chapter 1]).
1.2. Monolithic and hybrid integration
In most MEMS devices the interconnection between the transducer
and the electronics for output signal treatment is either done by hy-
brid or monolithic integration 3. The following subsections describes
in brief the two di erent approaches and illustrate advantages and
disadvantages.
1.2.1. The monolithic approach
The transducers andelectronics are fabricated on the same Si-substrate
in the monolithic approach using a dedicated process ow. This pro-
3Also referred to as the embedded approach.
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Introduction
vides an excellent electrical performance due to short on-chip intercon-
nections. Parasitic loads are thus minimized resulting in high opera-
tional speeds. The monolithic approach bene ts in addition from cost
saving batch fabrication. This is possible because many transducers
are fabricated using the same planar thin lm processing technology as
microelectronics. Di erent methods of combining the complementary
metal-oxide semiconductor (CMOS) and MEMS processing as well as
micro-opto-electro-mechanical systems (MOEMS) has been presented
in the literature. Examples include accelerometers 18{21], minia-
ture ink nozzles and containers 22,23], electrostatic de ectable mi-
cromirrors 24], uncooled infrared imagers 25] and combination of
electro-optic waveguide switching devices with heterojunction bipo-
lar transistors 26]. Reviews regarding co-integration of MEMS and
CMOS technology can be found in 27{30].
However, the electronics and MEMS are fabricated on the same sub-
strate and the processes must be compatible. This introduces seri-
ous technology constrains because thermal budget for micromachined
transducers in most cases are incompatible with processing of CMOS
circuits. Process techniques, like KOH-etching, are often also not com-
patible with CMOS processing. Beside these aspects, CMOS technol-
ogy depends on atness of surfaces. The results can be compromises
in terms of reduced design exibility and system performance as well
as and very complex processes, which will increase development e orts
time with negative impact on cost and yield.
1.2.2. The hybrid approach
The hybrid approach bypasses these obstacles by allowing all individ-
ual parts to be produced separately at di erent foundries, with subse-
quent integration using various interconnection technologies. Hybrid
integration o er the best performance as dedicated materials and op-
timized processes can be used. The processes may in addition be
modi ed at all stages without a ecting one another. This simpli es
the fabrication and o ers exibility in the choice of the MEMS/CMOS
process and substrate. Hybrid integration o ers also the possibility for
testing prior to assembling in order to obtain known-good-die (KGD).
Finally, it is possible to vertically assemble the separate components
in a stack. Valueable space on the chip is thus saved resulting in min-
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1.2. Monolithic and hybrid integration
imum volume and weight. These are important factors for small sized
systems required for bio-medical products, mobile consumer products,
avionic and space applications.
In order to determine between hybrid or monolithic approach, as the
optimal choice for a given application, is actually a question of whether
the application is dedicated or standard. The monolithic solution, with
slightly decreased performance but better price-to-performance ratio,
can be achieved if high volume markets are anticipated. Dedicated
hybrid processes will always o er better performance than the stan-
dard ones, but the initial development cost and time are not always
acceptable and often regarded as too risky.
Wirebonding hybrid integration is still the dominating interconnection
technology used in the MEMS industry ( g. 1.4) 4. This principle is
used for accelerometers used in automobile crash sensors 32], 33]
( g. 1.3 A), angular rate sensors 34] and pressure sensors 35]( g.
1.3 B), 36]. WB hybrid approach is also used in biomedical applica-
tions 37] and in microgyroscopes for space applications 38].
Wirebonding is essentially a welding process. It is a CMOS compatible
technology, but it di ers from other interconnection techniques in that
electrical packages connections are created at this assembly stage by
attaching a ne wire between each chip I/O and its associated package
pin, as opposed to attaching prefabricated patterns of interconnecting
materials. Conventional WB approach takes consequently up an ap-
preciable amount of chip real-estate due to the electrical wire loops.
To circumvent this obstacle components can be stacked on top of each
other in the stacking WB approach which is advantageous for space
constrained applications ( g. 1.4 A).
4See 31, Chapter 8] for an thorough introduction to WB technology.
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Introduction
Figure 1.3.: Hybrid wirebonded microsystems. (A): Accelerometer, Cortesy of
Ford Microelectronics, Inc. (B): Pressure sensor, Cortesy of Sen-
soNor asa.
However, WB packages tend to be bulky and the technology is based
on single die handling, with only one chip-to-package wirebond can
be made at a time, in contrast to the monolithic approach in which
hundreds to thousands of microsystems are processed in the same pro-
cess batch. For some applications, like radio frequency (RF) MEMS,
parasitic e ects like inductive losses in wires pose a problem. All the
interfaces must nally face the same direction, thereby imposing limits
on the MEMS design.
FC assembly technology o ers an alternative reliable and advanced
packaging approach for hybrid integration of micromachined compo-
nents. Flip-chip soldering and some of the most important involved
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1.3. Flip-chip for microsystems
Figure 1.4.: Wire bond hybrid integration for MEMS principle. (A): Planar hy-
brid WB integration. Organic material are usually used as die attach.
(B): Vertical hybrid WB integration.
technologies will be explained in the next section, together with the
concept of hybrid FC integration.
1.3. Flip-chip for microsystems
1.3.1. Solder bump ip-chip technology
Solder bump ip-chip is a chip-to-substrate bonding technology in
which one chip is placed face down ( ipped) on to the substrate and
soldered through bumps that provide both mechanical and electrical
connection 39] ( g. 1.5).
Solder bump FC technology was developed when researchers from IBM
in the early 1960s discovered that the surface tension of molten solder
were able to counterbalance the weight of the chip 5. FC was intro-
duced as an alternative interconnection technology in the IC industry
for the at that time expensive and unreliable wirebonding (WB) tech-
nology. But the continuously improving high-speed semi-automatic
wire bonders have met the needs of the semiconductor device to the
next-level package and repeatedly regained the advantage.
However, the relentless requirements for higher I/O density, higher
clock frequencies, lower weight and price in the electronic industry
has resulted in considerable research and development e orts during
5Also referred to as the Controlled Collapse Chip Connection (C4) process 40].
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Introduction
the last decades. FC-technology and the associated infrastructure has
consequently evolved to become a true state-of-the-art interconnection
technology in the IC packaging industry today.
Figure 1.5.: The fundamental principle in the ip-chip bonding process. UBM:
underbump metallization. TSM: top-surface metallization.
FC technology o ers excellent performance compared to other inter-
connection technologies:
Shortest possibleelectrical leads resulting inlowest electrical par-
asitics
Smaller device footprints, lower size and weight
Smallest pad size and spacing (pitch) resulting in extraordinary
high chip I/O density.
Simultaneous establishment of a large number of interconnects
Short electrical leads o ers several important electrical advantages like
low resistance (1-20 m ), low capacitance (0.1-0.3 pF) and low induc-
tance in the corresponding circuit6 (0.03-0.06 nH) 39, section 5.6] 41]
and high frequency potential. These advantages makes it therefore
6A typical leaded package will contribute resistance in the order of a few m and
inductance in the order of 5-10 nH 39, section 5.6].
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possibleto manufacture lighter, smaller, and higher-performance prod-
ucts.
Furthermore, FC-bonding provides the possibility for self-alignment
during assembly which reduces requirements for placement accuracies
to 20-25 m readily achieved by standard pick and place equipment
(chapter 2). This technology holds thus signi cant promises to be-
come a competitive low-cost passive technique for optoelectronic high-
precision alignment (see section 1.3.6 for a more thorough discussion).
Finally, in relation to MEMS fabrication, FC is a low temperature
CMOS compatible process by which electrical interconnections and a
hermetic sealing can achieved simultaneously in the same bonding step
(chapter 3).
1.3.2. Thin lm metallization
One of the key components of FC-technology is the anchoring of a
solder bump to the metallurgy on top of a I/O contact. The contact
metallurgy is termed ball-limiting metallurgy (BLM) or under-bump
metallization (UBM). It de nes the region of terminal metallurgy on
the top surface of the chip that is wetted by the solder (see section
1.3.6). The UBM consists of several layers with a composition and
complexity depending on the speci c application and on the solder
deposition method 42{48].
In this Ph.D.-work, several di erent UBM metallization schemes have
been utilized depending on the application and solder deposition tech-
nique. The characteristics of the di erent layers are discussed in sec-
tion 2.2.1 and the process-sequences used for fabrication of the layers
are explained in detail in appendix B).
1.3.3. Bumping technologies
FC is a very versatile technology where bumping can be accomplished
in several ways. The most used bumpingmethods includestencil print-
ingusing conductive adhesives, stud bumping, electroplating and phys-
ical vapor deposition (PVD) 15,39].
Major advantages associated with stencil printing are low cost, easy
bumping, no use of heat or ultra sound (US) etc., and the fact that a
lot of metallurgies are available.
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Drawbacks with stencil printing are relatively large bump sizes (sten-
cil/screen mask holes) and pitches (> 200-150 m 49,50]), and that
there is no possibility for single chip bumping. A major di erence
between conductive adhesives and solder bumps is that conductive
adhesives have no self-aligning tendency. The adhesive bumps will not
ow but only soften and therefore not exert surface tension forces.
High-precision alignment equipment must therefore be used to align
the bumps precisely onto the bond pads of a substrate.
Stud bumping is performed essentially as WB using standard wire
bonders and can be bonded to substrates using adhesives or utilizing
thermo compression and US energy. The process of stud-bump for-
mation is economical and reliable, but as each bond is made one at a
time this technique is not suitable for large production.
A comparison of di erent solder bumping technologies has been pub-
lished by Wolf et. al 51].
Thermal evaporation Physical Vapor Deposition (PVD) techniques
encompasses several deposition processes in which atoms are removed
by physical means from a source and deposited on a substrate. These
methods include thermal evaporation and sputtering.
Even though sputtering o ers better deposition uniformity, step cov-
erage, adhesion to the substrate and thickness control than thermal
evaporation, it is not an appropriate technique to deposit thick lay-
ers in the order of several m. The sputter equipment, and source
material targets, are furthermore very expensive. Ion radiation and
particle damage of the substrate is also a disadvantage. A comparison
of evaporation and sputtering technology can be found in 14, table
3.7].
Electron-beam induced thermal evaporation has been chosen for the
deposition of thin lm (Ti, Cr, Au and Pt), and for thick lm Sn depo-
sition (together with electroplating which will be discussed in section
1.3.3), in this thesis.
Evaporation is a successfully bump formation technique according to
a survey of the FC industry by Rinne from MCNC, and is used by
several companies and research institutes 52].
Evaporation of solder bumps can be accomplished with deposition
through a molybdenium metal shadowmask (IBM C4 process) aligned
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with the input/output (I/O) pad pattern, or by common photoresist
patterning and lift-o . It is possible to deposit several m of solder
53, 54], but the equipment is expensive and complex, and the de-
position time is large compared to other deposition techniques, like
electroplating.
Electrodeposition Electrochemical deposition (in microelectronicfab-
rication) concerns the deposition of metals or alloys on top of a elec-
tronically conductive surface from a water based salt solution (elec-
trolyte) containing metallic ions. The term electrochemical deposition
covers electrochemical plating (electroplating), in which an external
voltage is applied to electrolyte, as well as chemical plating (electro-
less plating), in which the deposition of results from an autocatalytic
reduction of a metal ions without the need for an applied voltage.
Figure 1.6.: Schematic drawing of the Sn-electroplating plating bath at IPT. The
tank contains 25 liters and has continious agitation and ltering
through a 1 m Siebec MC4 lter.
In this work electroplating has been used for the deposition of Cu, Ni,
Sn and SnAg(96.5/3.5 wt%) at IPT and SnPb(60/40 wt%) at LETI
(chapter 2). The metal is deposited by passing an electrical current
through the anode, and the electrolyte, by which the metal ions di use
to the cathode, - in this case the wafer ( g. 1.6).
The intermediate chip which were to be soldered (see section 1.4) con-
tained through holes. It was therefore necessary to used an electrode-
postiable photoresist7 (EDPR) since it is not possible to spin ordinary
resist on wafers containing etched holes 55]. The plating baths were
7Shipley Eagle 2100.
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most commonly operated at room temperature (Cu, Sn, SnAg and
SnPb) but also at elevated temperatures (Ni is plated at 40 C).
Sn can be electrodeposited from a number of plating baths. The
most common of these are stannous sulfate, stannous uoroborate
and methanesulfonic acid plating baths. However, these baths are
very acidic having low pH-values and are as such not compatible with
the EDPR which will resolve in acidic solutions 55]. In this work
we used a new commercial stannous sulfate/gluconate plating solution
having a neutral pH-value.
A comprehensive survey of electrochemical deposition in general and
plating of Cu and Ni can be found in a Ph.D.-thesis by T. Tang 56].
For wafer bumping, electroplating o ers greater exibility in the rapid
application of a wide range of bump sizes. With a well-controlled
plating process, electrolytic deposition o ers the advantages of high
throughput, excellent volumetric and compositional uniformity, and
relative freedom from pitch limitations. Solder bumps as small as 20
m in diameter have been fabricated at MCNC. For solder selection,
electroplating allows the use of many types of solders 57].
1.3.4. FC hybrid integration of MEMS
The number of sensor patents in combination with ip-chip technology
has grown considerably since 1985 48], and ip chip hybrid integra-
tion of MEMS and MOEMS has emerged as an excellent alternative
to the monolithic and wirebonding hybrid approach.
This method involves fabricating the electronics and MEMS as sepa-
rate parts and then stacking them vertically with solder bumps. Since
ip chip allows the IC to be placed directly over a MEMS device,
there is little or no area penalty. FC leads thus to very compact sys-
tems, having almost the same size as the individual component. The
electronics are moreover electrically much closer to the MEMS thus im-
proving performance as discussed in section 1.3.1. And, as with WB
hybrid integration, FC packaging allows buildingof the electronics and
MEMS on substrate types other than silicon and provides complete
process independence of the MEMS and the electronics. This allows
the manufacturer to optimize the performance of each component sep-
arately. But the electrical contacts must always face the substrate
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onto which the components are bonded.
The concept of planar hybrid FC integration for MEMS has been uti-
lized by LETI and Balteadisk ApS for the assembly of an integrated
print head device 12] ( g.1.7 A). Berkeley Sensor & Actuator Center
reports to have integrated MEMS to electronics using using FC gold
bump compression bonding at room temperature (cold weld) 58,59].
Researchers at University of Colorado used FC thermosonic bonding
to transfer MEMS to substrates containing microwave coplanar wave
guides 60]. Other examples of assembling MEMS and dedicated
electronics using hybrid FC integration include packaging of MEMS-
based radiofrequency (RF) components 61]. Hybrid FC integration
of MOEMS has furthermore been accomplished by using chip-to-chip
thermocompression bonding and simultaneously re ow soldering 62]
and by a self-aligning scheme for an edge-emitting laser and a micro-
Fresnel lens) 63]. FC technology is also used to attach 2-D arrays of
optical devices to submicron CMOS VLSI circuits in optoelectronics
VLSI 64].
FC bonding in combination with vertical electrical feedthroughs makes
it possible to physically decouple and protect the electronics from the
sensing or actuating side of the transducer which can then be exposed
to a aggressive media 11,13,65] ( g.1.7 B).
Figure 1.7.: Flip-chip hybrid integration for MEMS principle. (A): Planar hybrid
FC integration. (B): Vertical hybrid FC integration.
Finally, and maybe most important for MEMS, FC bonding o ers the
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Introduction
possibility to establish all interconnections and a protective solder seal
ring simultaneously in the same bonding process 66{68](chapter 3).
A review of di erent stacking technologies can be found in 69{71].
1.3.5. Solder metallurgy
The decision to use a particular material as solder is largely based on
its chemical and physical properties, and the cost. The materials ther-
mal conductivity, expansion coe cient, resistivity, tensile strength,
wettability and the toxic potential of the solder are thus important
factors. The material most commonly used in the electronics industry
is a tin-lead alloy.
When an alloy is heated it typically goes thorough multiple phases:
From a solid state to what is known as a pasty stage, and then to a
liquid state. In soldering it is di cult to work with a substance that
goes through a pasty stage. Eutectic solder is an alloy that goes di-
rectly from a solid state to a liquid state (and the reverse when cooled)
without a pasty stage. This makes it possible to form solid solder joints
very quickly. The melting point of the eutectic alloys is furthermore
low ( g. 1.8).
In industry tin lead alloy with eutectic or near eutectic compositions
are used. The eutectic tin-lead alloy is made up of 63% tin and
37% lead with a melting point at 183 C ( g. 1.8). Sn/Pb(60/40
wt%), a near-eutectic tin-lead alloy with a relatively low melting point.
Lead/Tin (95/5 wt%)-solder are also widely used because the higher
melting point ( 315 C) which allows the application of near-eutectic
lead/tin solder in consecutive steps of system packaging 51,72,73].
Lead is also a very compliant metal which increases the reliability of
the solder interconnection during thermal cycling. Finally, lead is a
cheap and abundant metal, so the cost of a tin-lead solder is primarily
controlled by the cost of the tin. But due to the toxic nature of lead,
environmental considerations have during the recent years led to in-
creased research e orts concerning lead-free solder materials like SnBi
74], Au-Sn 46,75,76], SnAg 77,78] or even pure Sn 79] which is
used in this project.
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1.3. Flip-chip for microsystems
Figure 1.8.: Sn-Pb phase diagram. From 80].
Pure Sn has a low melting point (232 C), retains its solderability and
has a storage life longer than unfused Sn/Pb 79].
Two possible latent defects has been reported when pure Sn was used
as solder nishing 81]:
Tin whiskers, which may cause electrical shorting between the
bumps
Formation of -Tin (gray tin or tin pest) which theoretically
transforms the solder into a powdery structure at temperatures
lower than 13 C.
However, it has been reported that the chances for the formation of
whiskers are rare when using Cu as wettable metallization and even
less when using Ni 82] as in this project. Furthermore, it has been
reported that temperatures near -40 C were required to produce the
transformation, through an nucleation process 83].
When tin-based or pure tin solder is used, the tin reacts with the
base metal to form an intermetallic alloy. This intermediate layer of
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metal ranges from a high concentration of tin on the solder side to an
increasing concentration of the base metal on the other side. These
intermetallic alloys are typically brittle which means that interface be-
tween the solder joint and the metallization is the "weak link", and is
susceptible to mechanical failure due to stress or vibration.
In order to reduce the likelihood of failure, the intermetallic alloy needs
to be as thin as possible. The intermetallic layer has a negligible
growth rate at room temperature which accelerates as the tempera-
ture is increased. It is therefore advantageous to solder at the lowest
possible temperature, typically just above the solder melting point. A
shorter time of contact between the solder and base metal at an ele-
vated temperature results in a thinner intermetallic layer. This means
that soldering should be done as quickly as possible. Another way
to get a thinner intermetallic layer is to slow its growth. A lower tin
content in the solder results in slower growth 84].
1.3.6. Re ow soldering and self-alignment
The wettability of a solid by a liquid is indicated by the contact angle
de ned in g. 1.9:
Figure 1.9.: De nition of the contact angle at a solid-liquid interface.
The angle between the surface tension forces 8 of the solid-vapor
( SV ), solid-liquid ( SL ) and liquid-vapor ( LV ) interfaces according
8Surface tension may be interpreted as a force per unit length, acting perpendic-
ular to the surface.
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1.3. Flip-chip for microsystems
to Young's equation:
LV cos + SL = SV ) (1.1)
cos = SV SL
LV
A liquid is said to wet a solid surface when cos > 0, that is, when
SV > SL . The driving force for wetting, Df, is de ned in a review
by Delannay et. al. 85] as
Df = SV SL (1.2)
When Df LV , = 0 and the liquid spreads out across the solid
surface and the liquidissaid to completely wet the solid. Thissituation
occurs when the atoms of the liquid prefer to contact to the solid
surface instead of forming an interface to the surrounding gas phase.
Inhigh vacuum the work of adhesion 9, Wa , can furthermorebe de ned
as
Wa = SV + LV SL (1.3)
which is a measure of the strength of the binding between two phases.
Hence, in a vacuum and when there is no adsorption of the liquid
components at the surface of the solid ( SV = SL ) one can rewrite
equation (1.2) and see that the driving force for wetting is only a ected
by the surface tension of the liquid and the strength of the solid liquid
interface:
Df = ( LV Wa ) (1.4)
The condition for wetting under vacuum becomes consequently Wa >
LV , which implies that a liquid only wets a solid if the energy of the
bond that are created across the interface exceeds the surface tension
of the liquid.
Re ow soldering is the preferred method of soldering surface mount
components 84]. In a re ow bonding process the FC attached compo-
nents are heated to elevate the temperature of the base metals, re ow
(melt) the solder and activate the ux (section 1.3.8). Surface tension
forces are the dominant factor in determining the solder surface geom-
etry at the -scale, typical of solder joints. Any system will be driven
9The work that must be performed in order to separate one unit area of the two
phases.
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towards a minimum energy state, equilibrium, by the forces acting
within it. A liquid solder joint will thus be driven towards a shape
which has minimum surface area, where the surface tension is exactly
balanced by the internal pressure of the solder and the gravitational
forces.
Good electrical contact and mechanical bonding are ensured by ( g.
1.10):
dewetting from the substrate onto the metallization
self-alignment of the molten solder metal
Figure 1.10.: Principle in self-aligning FC solder bonding. (A): Chip with de-
posited solder bumps is aligned to substrate previous to re ow.
(B): Re ow bonding of chip to substrate by applying heat. (C):
self-alignment due to the surface tension forces of the molten sol-
der.
Self-alignment of the solder is a promising cost e ective method to
achieve a high positioning accuracy of photonic devices, which is nec-
essary for high coupling e ciencies. This can be seen from the rela-
tionship between coupling loss, , in dB and an optical axis o set, d,
in m 86]:
= 0:13 d2
(1.5)
Hence, less that 0.8 m o set is necessary in order to obtain coupling
loss less than 0.1 dB. This is within the tolerance for single coupling
light in multimode bers, but two to three times too large for single
mode bers 87]. Consequently, a signi cant portion of optoelectronic
R&D is currently invested in improving alignment accuracy and min-
imizing packaging cost of optical components using various alignment
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technologies.
These trials include two-dimensional electrostatic driven micro-actu-
ation 86], bulk Si micromachined aligning pits combined with exible
holding elements 88]. However, passive self-alignment using FC sol-
der bump technology combined with uxes, reducing gases or plasmas
is most often reported 62,75,87,89{94].
Furthermore, a number of researchers have reported that, the reliabil-
ity of solder joints depends highly - among other parameters - on the
solder joint geometry 95{99].
Therefore, to achieve a satisfactory alignment and to avoid unreliable
interconnections, modeling tools are used in order to obtain a quanti-
tative estimation of the solder geometry and height after re ow.
1.3.7. Surface Evolver
Even apparently simple problems of predicting the shape of liquid sol-
der requires numerical solutions of the relevant equations. Before the
emergence of the public domain software Surface Evolver 100] most
e orts have been problem-speci c and the algorithms that have been
developed are not easily applied to other geometries. Surface Evolver
is an interactive nite element program for the simulation of surfaces
whose geometry is determined by surface tension, gravity and other
forces. Based on vertices and edges a surface is implemented as a
union of facets that all have outward normal. Given an initial sur-
face, with the solder and pad metallization geometry, solder volume,
constraints, and energy attributes described in a ASCII data le the
program evolves the surface towards minimal energy by a gradient-
decent method.
A variety of solder meniscus problems using Surface Evolver as mod-
eling tool have been presented in the literature: Harsh et. al. 101]
and Kladitis et. al 102] calculate the solder volume in order to as-
semble MEMS to precise positions. Design rules regarding optimum
pad geometry and solder volume for precise self-alignment have been
proposed by Zhu et. al. 93], Koschel et. al. 91], Deering et. al. 103]
and Lin et. al. 104].
Surface Evolver has also been used to predict failure modes and in-
vestigate reliability issues for soldered components. These simulations
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include force and torque analysis for determining tombstone e ects
causing solder join failure during leadless component re ow process
(Wu et. al.) 105]. Chiang et. al. compare the in uence of di erent
circular and elliptic pad shape respectively on thermal stress/strain
behaviour 106]. Whalley simulate the formation of shorts between
adjacent open circuit joints 107], and Tower et. al. have developed a
model to determine the assembly yield and the solder height of every
joint in a large number of connections 108].
Evolver is limited to predicting the equilibrium shape of surfaces,
as it cannot model dynamic situations where, for example, viscosity,
thermal capacities and heat transfer rates are important factors in
determining the nal equilibrium conditions. However, Evolver si-
mulated surfaces have been imported into the nite element program
ANSYS for stress/strain analysis by Wu et. al. 109] and imported
into PHYSICA to simulate uid ow, heat transfer, solidi cation and
stress evolution on solder joints by Bailey et. al. 110].
Heinrich 111] have publisheda review article in the area of solder joint
geometry modeling.
1.3.8. Fluxes for soldering
The presence of an oxide layer on the metallic solder bumpswillimpede
the surface tension forces of the molten solder and obstruct the self-
alignment. A surface oxide will in addition weaken the bond between
the pad metallization and the solder. It is found empirically that most
metals are oxidized at a very accelerated rate when the temperature
T is increased. That is, for many reactions it is found that a plot of
the natural logarithm of the rate constants, lnk, against 1/T gives a
straight line according to the Arrhenius law:
lnk = lnA Ea
RT (1.6)
where Ea is the activation energy. This creates a particular problem,
since the chemical reactions associated with solderingrequire hightem-
peratures. In table 1.1 is presented some activation energies for the
oxidation of various solders:
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Solder
composition 99.4Sn-0.6Al 91Sn-9Zn 63Sn-37Pb Sn
Ea
(kJ/mole) 27.7 23.3 20.5 19.8
Table 1.1.: Activation energies for the oxidation of various solders. It appears
from the values of Ea that Sn oxidizes most easily of these solders.
From 112].
As a consequence, uxes are traditionally being used in combination
with soldering to remove and prevent further oxidation of the metal.
In addition uxes provide tacking of the components to the substrate,
and promote heat transfer during soldering.
Flux is often applied as a liquid to the surface of the base metals
and/or the solder prior to soldering. The ux covers the surface to
be soldered shielding it from oxygen and thereby preventing oxidation
during heating. Most uxes also have an acidic component that is
used to remove the oxide already present on the base metal.
1.3.9. Fluxless soldering
The soldering process needs to be adjusted as uxes can not be tol-
erated for many applications in the following new areas: In micro-
mechanics, uxes can inhibit the motion of delicate moveable struc-
tures or clog capacitors, nozzles and ventilation holes 12]. In photon-
ics uxes may contaminate sensible optical surfaces of the device and
thus de ect or attenuate the optical signal. Fluxes can moreover cause
corrosion, and even a mild ux leaves residues that continues to cor-
rode after the soldering process is complete, or weakens the adhesion
of under ll 113], with incresed possibility for future failure. Fluxless
FC soldering is essential for new microsystems applications. Fluxes
consume a small percentage of the solder during re ow, which makes
it very di cult to obtain vertical alignment with a reproducible high
accuracy (chapter 3).
Finally, uxes, and especially their cleaning agents, expose a serious
potential threat to the environment, even though the industry are in-
vesting e orts to make these chemicals comply with environmental
demands.
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1.4. Motivation and goals
This project has been motivated by the ongoing R&D for a micro-
phone module, carried out within the MSC and HISTACK projects as
mentioned in the preface. The microphone is intended to form part of
a Complete-in-the-Canal (CIC) hearing aid device which is separated
into several units witch each has a unique functionality. The silicon
microphone is based on a capacitive working principle with a compli-
ant single-backplate read-out principle 13,114].
The microphone concept has to ful ll the following packaging require-
ments:
Extreme small package size (few mm3)
Sealing for environmental protection
Acoustic access to the transducer
Low power consumption
Low parasitic capacitance and low resistance of wiring
The microphone should furthermore be protected against electromag-
netical radiation and environmental disturbances such as dust and
humidity. The microphone is assembled, and sealed, based on the
stacking principle with the individual components stacked on top of
each other ( g. 1.11). An intermediate silicon chip has been included
in the design to ensure the frontchamber is large enough for the micro-
phone to work satisfactory. The assembly of the microphone includes
three levels of bonding:
Level 1 : Anodic Si-Si wafer bonding of backchamber and micro-
phone.
Level 2 : FC solder bondingof interconnect chipwithvertical feedthroughs
and a seal ring to microphone/backchamber wafer-stack.
Level 3 : Gold stud bumping of IC chip to interconnect chip and
insulating under lling
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Figure 1.11.: The Si-microphone stack. The interconnection chip contains the
sound inlet with glued sealing membrane. Connection to theoutside
is obtained by bonded wires, shielding by conductive adhesives.
Cortesy of Microtronic A/S 4].
This Ph.D.-work has been focused on research and development for
the uxless FC soldering technology used for assembly of level 2 in the
Si-microphone module.
As mentioned in the previous section uxes, and their cleaning agents,
can clog the membrane and ventilation hole and can not be toler-
ated for this application. One of the major drawbacks in uxless FC-
bonding is that prealignment of the samples and the bonding could
not be separated due to the lack of the tackiness of the ux. The
intermediate chip (or wafer) has consequently to be bonded to the
microphone/backchamber wafer-stack by one of two possible bonding
roads as shown in g. 1.12.
Wafer to wafer bonding and re ow soldering in a reduced O2 partial
pressure, using infrared (IR) heating, would be a possible bonding
route resulting in a large number of simultaneously established bonds.
However, this approach involves inconvenient and cumbersome In Situ
wafer alignment. Wafer bending during heating is also likely to be a
possible obstacle.
Another possible route would be to create a physical bond and attach
single intermediate chips by cold welding on single microphone/back-
chamber chipstacks, or preferablyon KGD sitesof a microphone/back-
chamber wafer stack, followed by re ow soldering in inert ambient.
Such a scheme would increase the ease of chip handling and chip trans-
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portation considerably.
One goal in this Ph.D.-work has consequently been to establish a man-
ufacturable uxless prebonding FC technology.
Figure 1.12.: Microphone to intermediate chip/wafer bonding scheme.
E orts has been invested in exchanging experience with LETI on FC-
processing of Sn-based solder bumps. That is, to evaluate and com-
pare the self-alignment quality and accuracy of uxless Flip-Chip (FC)
re ow bonding in O2-purged atmosphere and when using ux respec-
tively.
Electroplating is generally being considered to be a more cost e ective
and a more suitable technique than vacuum evaporation techniques
for deposition of thick (10-50 m) layers of solder. Hence, e orts has
been invested to reveal di erence in the self-alignment quality between
these two deposition techniques.
Hermetic sealing is crucial for many microelectromechanical sys-
tems as explained in section 1.1.1. Another goal has been to simulate,
experimentally characterize a hermetic solder seal ring which serves as
an environmental protection against acoustical interference, humidity
or gases for the Si-microphone.
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During the research stay at LETI it became clear during dewetting ex-
periments that a more profound investigation concerning the surfaces
of solder and substrates could be of considerable importance.
Surface analytical investigations is consequently also included in this
thesis.
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2. A manufacturable uxless FC
bonding technology for
microsystems
A new approach to uxless ip-chip soldering is proposed in this chap-
ter. Using force and heat a prebonding scheme is established which
enables mechanically stable bonds between Sn solder bumps and a
wettable top-surface metallization with matching footprints.
A second part of this chapter compares two di erent FC bonding tech-
nologies: LETI's ux-assisted and MIC's uxless re ow bonding pro-
cesses are compared and evaluated in order to reveal any existing dif-
ferences in the self-alignment quality.
First trials to transfer MIC's FC process to re ow furnaces with N2
and N2/H2 purge, suitable for batch processing are nally presented.
2.1. Literature survey
Di erent approaches to obtain solder self-alignment without use of
uxes have been reported in the literature. These trials can be divided
into two major categories. The rst category include self-alignment
carried out in reducinggases like pureH2 92,115], forminggas (N2/H2-
gas-mixture) 116], formic acid vapor 92,117], acetic acid vapor 118],
halogen containing gases CF2Cl2, CF4 and SF6 (without plasma scti-
vation) 119], as well as self-alignment performed in an inert ambient
92] or high vacuum 115].The second category concerns di erent
types of dry chemical pretreatment of the solder prior to re ow sol-
dering.
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For studies concerning removal of oxide with reducing gases during
re ow, Kuhmann and Pech found that reproducible 1.4 +/- 0.8 m
lateral self-alignment accuracies was possible in a controlled pure H2-
atmosphere 53]. The authors also report that high vacuum was not
suitable to produce su cient accuracies required for single-mode ber-
chip coupling (section 1.3.6).
Lin and Lee conclude that formic acid appears to be one of the most
promising reaction gases for uxless soldering 117]. The process
implementation is relatively simple in contrast to H2-gas operation.
Formic acid vapor is moreover active at typical soldering tempera-
tures and decomposes to harmless reaction products (H2O and CO2)
in respect to optical facet contamination and reliability. Lin and Lee
found that an alignment accuracy of 2 m range could be obtained at
1.7 % formic acid vapor concentration.
Kallmayer et. al. con rm this observation in a study concerning the
self-aligning accuracy of eutectic Au/Sn solder bumps in a pure N2-
atmosphere (O2 content < 8 ppm), in pure H2-atmosphere (O2 content
< 3 ppm) and in an active atmosphere (O2 content < 8 ppm) respec-
tively 92]. Chips with Vernier patterns were used for quanti cation of
the horizontal alignment accuracy. A nal alignment accuracy better
than 3 m was achieved with 5 % of the samples which were re own in
N2, 95 % of the samples re own in H2 and 98 % of the samples which
were re own in an active atmosphere.
The other major trend in uxles self-alignment is to use dry chemical
pretreatment of the solder.
Pickering et. al. reported in 1989 that re ow bonding had been
achieved with tin-lead solder pretreated with H2-plasma 42].
Koopman et. al. have introduced Plasma Assisted Dry Soldering
(PADS) which is based on a CF4 or SF6 plasma pretreatment of the
solder prior to re ow soldering 120{124]. In the PADS process a mi-
crowave eld dissociates temporarily an inert, non- ammable, uorine
containing gas into its constituent elements. A roughing pump is used
to lead the gas stream down to the wafer ( g. 2.1). The solder is
thus not exposed to the high temperatures in the plasma or to sput-
tering. But the uorine atoms are long-lived enough to react with and
convert the oxide on the solder surface into oxy uorides according the
proposed reaction 124]:
SnOx + yF ! SnOxFy (2.1)
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2.1. Literature survey
Figure 2.1.: Schematic drawing of the PADS system. Pump time: 1 min. He
purge time: 1 min. Re ected power: 50 %. SF6 ow rate: 2 sccm.
Treatment time: 1.5 min. Temperature during treatment: < 120 C.
The enhanced re ow characteristics of the solder after PADS treat-
ment is explained as being a result of the oxy uorides which breaks
up more easily than solder oxide when the solder melts. An oxide free
solder surface is thus exposed, allowing re ow and joining to occur in
the absence of ux 124]. This statement will be discussed in chapter
4.
LETI has obtained self-alignment of PADS pretreated solder bumps
(after ux-assistedpre-re ow) witha reproduciblehorizontal self-align-
ment accuracy < 0.5 m 94]. An investigation of the oxide conversion
using surface science techniques will be presented in chapter 4.
However, the above mentioned processes obtained under laboratory
conditions are not easily transferred to re ow furnaces used for batch
processing under robust industrial conditions.
Another major drawback regarding uxless FC-bonding, which has to
be tackled in order to achieve commercial success, is the alleged lack of
prebonding capability. Fluxless FC-bonding can not make use of the
stickyness of the ux to keep the components in place after alignment.
Typical accuracies are +/- 20 m (see section 2.3) but very costly high
accuracy equipment o ers alignment accuracies better than 1 m. This
makes the stacked components sensitive to vibration during handling
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and transportation.
Industrial re ow soldering processes takes place in N2-streamed con-
veyer belt furnaces. The practicability, ease of chip-handling and chip-
transportation would consequently be improved considerably by sep-
arating the prealignment and the tacking of the components from the
subsequent re ow soldering into di erent work sequences.
Tsunetsugu et. al. have proposed a prebonding FC technique in which
SnPb(60/40 wt %) solder bumps are being transferred from a Si carrier
substrate to a chip, containing matching wettable metal footprint, us-
ing slight pressure and bondingtemperature below the melting point of
the solder 125]. To avoid a nonuniform applied pressure, which may
cause scattered bumps for large chip sizes, the authors used a spherical
bonding head. However, this approach imply the use of uxes after
transfer of the solder. Furthermore, in order to obtain su cient sol-
der bump height and vertical accuracy necessary for photonic devices
Tsunetsugu proposes multi-transferred bumps 1. This will inherently
increase fabrication di culty and result in a lower yield, and presum-
ably also increased variation in the solder height.
Tilmans et. al. have recently reported on the fabrication and hermetic
packaging of a electromagnetic microrelay using uxless FC bonding
67]. The authors use a prebonding scheme of PADS pretreated eutec-
tic SnPb(60/40 wt. %) solder to Au with subsequent re ow bonding
in vacuum or various gas mixtures.
A new approach to uxless ip-chip soldering is proposed in this chap-
ter. Using force and heat a prebonding scheme is established which
enables mechanically stable bonds between pure Sn solder and a wet-
table metallization without any special consideration to the surround-
ing ambient.
Re ow bonding is subsequently performed in a reduced O2 partial
pressure.
2.2. Sample preparation
Three di erent technologies have been utilized in order to produce
samples for the experiments described in this chapter (and throughout
1The as-evaporated solder height is not stated.
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2.2. Sample preparation
the thesis): two electroplating processes and one evaporation scheme.
The evaporated solder has been deposited by using structured thick
lm (22 m) photoresist with negative sidewalls. These processes fa-
cilitates lift-o and ensures solder bumps which are free from carbon
contamination, stemming from the photoresist. The corresponding
metallization schemes are discussed in the following subsections, and
the process sequences are explained in detail in appendix B.
2.2.1. Thin lm metallization
UBM scheme 1: UBM scheme 1 was used for electrodeposition of
solder in these experiments: prebonding and preliminary electrical
testing of prebonded solder bumps, and investigation of hermetic seal-
ing (chapter 3). Processing of UBM scheme 1 (appendix B.1) included
the layers as depicted in g. 2.2:
Figure 2.2.: Cross-section drawing of the Ti/Au/Cu/Ni UBM for an electroplated
solder bump with Cu as I/O metallization. (A): SiO2 passivation
layer. (B): Ti adhesion layer. (C): Au seed layer (D): Cu I/O pad
metallization (E): CuO2 solder dam. (F): Ni wettable metallization
and solder di usion barrier.
UBM scheme 2: UBM scheme 2 was used for electrodeposition of
solder in experiments regarding quanti cation/quali cation of self-
alignment using LETI's deposition technology and mask layout ( g.
2.8). Processing of UBM scheme 2 (appendix B.2) included the layers
as depicted in g. 2.3:
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Figure 2.3.: Cross-section drawing of the metallization scheme for an electro-
plated solder bump using LETI deposition technologies. (A): SiO2
passivation layer. (B): Ti adhesion layer. (C): Au seed layer. (D):
Ni wettable metallization solder di usion barrier. (E): Au oxidation
barrier.
Scheme 3: UBM scheme 3 was used for evaporation of solder in
experiments concerning quanti cation/quali cation of re ow and self-
alignment. Surface science investigations regarding substrate depen-
dency on solder dewetting characteristics is also based on this met-
allization scheme (chapter 4). The metallization scheme concerning
evaporated solder bumps is simple ( g. 2.4 and appendix B.3) be-
cause an I/O pad-metallization had no purpose in these experiments
and a seed layer is not necessary:
Figure 2.4.: the metallization scheme for an evaporated solder bump. (A): SiO2
(or Si3N4) passivation layer. (B): Cr adhesion layer. (C): Pt wettable
metallization solder di usion barrier.
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2.2. Sample preparation
Passivation layer
An inorganic layer such as 0.3-3 m thick thermal silica (SiO2) or
0.1-1 m nitride layer (Si3N4) is grown on the Si surface in IC pro-
cessing to passivate the wafer. Silica and nitride posses good low rel-
ative dielectric constants (4 and 6-9 respectively) which gives devices
a decreased capacitance resulting in increased speed for electronic ap-
plications 31,126].
For this work the insulation layer has ful lled two di erent require-
ments, namely:
1. to act as an electrical isolatingbarrierbetween the siliconchip/wafer
and the UBM ( g. 2.2).
2. to function as a non-wettable surface for the wafer. This ensures
reliable dewetting and proper self-alignment ( g. 2.3 and 2.4) or
to form large solder bump heights 94].
I/O pad metallization
Aluminum 2 is the metal of choice in the IC industry due to low cost,
low resistance, good reliability characteristics and its ability to be
wire-bonded.
In this project Cu has been chosen as I/O pad metallization due to
several advantages compared to Al. Copper oxidizes to a lesser extent
than Al due to a 10 times times larger enthalpy of formation 127].
Moreover, only a brief etching is required to remove the native oxide
prior to electrodeposition of the wettable metallization and of the sol-
der (appendix B.1). But most importantly, the Si microphone project
requires electroplating of the I/O metallization in order to realize ver-
tical feedthroughs 12,65]. In contrary to Cu which can be deposited
from water based electrolytes, Al can only be electrodeposited from
organic electrolytes which are expensive and di cult to use. Finally,
copper has a lower resistivity than Al (Cu: 2.22 and Al: 3.57 cm
at 100 C).
Adhesion layer and seed layer
Sputtered or evaporated Cr, Ti , or sputtered TiW (50-3000 A) are
commonly used adhesion materials in CMOS applications 31].
2Usually sputtered Al-1%Si.
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Al has two purposes when it serves as I/O metallization: to make a
strong bond between the I/O pads and the wettable metal upon which
the solder bump is deposited, and to function as barrier for interdif-
fusion between the wettable metal/solder and Al. This metal layer is
thus a key factor determining the reliability of the solder bump struc-
ture.
In this project, where electroplated Cu serves as I/O metallization, the
adhesion layer bonds the Au seed layer to the passivated wafer. The
seed layer functions as current feeding cathode during plating (section
1.3.3). Patterning of the I/O metal lines is achieved by standard pho-
tolithography techniques.
The plating base is later removed using the plated solder as etch mask.
Wettable metal
After plating of the I/O metallization, the geometry of wettable metal
is de ned by a new photolithography step. The most frequently used
thin lm metals are Cu and Ni. Typical thickness are 1-2 m.
In experiments in this work where evaporated solder was used, Cr (200
A) is evaporated as the adhesion layer and thin (2000 A) evaporated Pt
as wettable metal (because it is available in most processing facilities).
Pt has in addition previously shown good resistance against excessive
di usion into the solder (leaching) during thermal re ow 53,115,128].
The metals are structured using standard photolithography and lift-o
processes (appendix B.3).
Oxidation barrier layer
The oxidation barrier layer ( 0.1-0.01 m) is made of electroplated,
evaporated or sputtered Au. This protects the Ni from oxidation,
which otherwise would introduce a thin semiconducting layer between
the solder and the obstruct wetting. Au dissolves rapidly into the Sn
solder and forms brittle compounds. If the concentration becomes too
high it will a ect the solder fatigue life negatively 129]. This requires
that the thickness of the Au oxidation barrier is kept very thin in
order to ensure long term reliability of the solder joint. Typical Au
thicknesses are in the order of 1000 A which were used for the UBM
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2.2. Sample preparation
Scheme 2 ( g. 2.3). However, at MIC it is possible to transfer the
wafers directly from the Ni plating bath to the Sn plating bath (after
a short cleaning with water). Oxidation of Ni was thus avoided and an
Au oxidation layer was not necessary for these experiments ( g. 2.2).
Solder dam
The fact that there are metals in CMOS fabrication that do not react
with solder is important. These materials are used in the construction
of soldering machinery and can be used as temporary cover for com-
ponents that are not to be soldered.
Cr, silica or nitride are commonly used as a solder dam. However, as
this process step is one of the last in the IC fabrication, high temper-
ature processes (such as thermal oxidation used for passivation of the
bare Si wafer) can not be tolerated. Instead plasma enhanced chemi-
cal vapor deposition (PE-CVD) is used as deposition technique. It has
also been shown bu Shi et. al. that the native copper oxide (CuO) is
su cient to prevent a solder ball from wetting copper surfaces 130]
and act as a solder dam.
Top surface metallurgy
The topside (or top surface) metallurgy (TSM), de nes the terminal
metallurgy on the substrate to which the solder-bumped ip chips are
joined. The formation of TSM can be achieved by either thick- or
thin- lm technology similar to the UBM. Solder ow is restricted by
the use of solder dams where necessary.
In order to make reliable connections it is necessary to choose the
correct solder as well as the appropriate deposition, patterning and
joining techniques. During operation all parts of the package interact
as the temperatures changes and special testing methods are required
in order to make realistic lifetime projections. We used Cr/Pt as TSM
for all applications.
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2.3. Prebonding and re ow soldering
2.3.1. Test chips and substrates
Several di erent chip designs (photolithography mask layout) have
been used depending on the various experiments in this work.
It was one of the main goals to develop a prebonding scheme for a sol-
der seal ring and interconnection solder bumps in the Si microphone
stack (level 2 in g. 1.11). Consequently, in this chapter and in chapter
3 the prebonding technology is demonstrated using a solder seal ring.
A test vehicle ( g. 2.21) was in addition employed in order to perform
preliminary electrical and mechanical tests of the solder bonds.
2.3.2. Prebonding
The prebonding was performed, using a commercially available FC
bonder 131]. The prebonding principle in shown in g. 2.5 A. The
bumps were in their as-deposited state prior to prebonding.
During prebonding the bumped Si substrate was situated on a heating
plate and kept below the melting point of the solder. We used glass
chips in order to perform visual inspection during re ow. The glass
chip was attached to the heated chip-tool by a vacuum and aligned to
the solder bumps on the substrate using a split- eld microscope with
video-output ( g. 2.5 C-D).
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2.3. Prebonding and re ow soldering
Figure 2.5.: (A): The prebonding principle. (B): Dependency of deviation from
chip-parallelism. (C): Photograph of the FineTech FC-bonder. (D):
Close-up of the chip-tool and hotplate. at DELTA.
The hot-plate and the chip-tool were kept at the same constant tem-
perature during the bonding sequence. When a satisfactory alignment
was achieved, within the accuracy of the bonder (+/- 10 m), the
bumped chip was contacted to the substrate by applying force. Pla-
narity and parallelism of FC-equipment had also to be carefully con-
sidered. This was especially the case for large dies: A tolerance of +/-
5 m in bump height from one side of a 1 cm wide chip to the other
side requires a deviation less than 0.03 degree ( g. 2.5B).
These trials, using a wide range of parameters showed, that mechani-
cally stable prebonds, with shear force of > 3 +/-1 cN/mm2, could be
achieved.
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The bonding parameters were:
Bonding force: 0.5 cN/bump
Temperature: 180 C
Bonding time: 6 sec
Using these parameters intermediate chips were sucessfully prebonded
to a backchamber-microphone wafer stack ( g. 2.6).
Figure 2.6.: Intermediate chips prebonded to a microphone-backchamber wafer
stack. Design: cortesy of Microtronic A/S.
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2.3.3. Re ow bonding
Subsequent re ow bonding was performed both in HV and in N2 (20
ppm O2) using a rapid thermal anealing oven (RTA) at MIC ( g. 2.7).
Figure 2.7.: The rapid anealing oven at MIC. High vacuum is achieved with a
turbo pump in combination with a roughing pump. A Pirani gauge
and a Penning gauge monitor the pressure in the high and low pres-
sure range respectively. The chamber can be purged with high purity
N2.
Two 2 cm thick quartz plates, sealed with O-rings, constitute the bot-
tom and the top of the high vacuum (HV) chamber. The samples
were heated with a halogen lamp, emitting in the near infrared, sit-
uated underneath the chamber. The design of the oven allowed In
Situ observation and recording of the re ow bonding process using a
CCD-camera attached to a stereo microscope above the chamber. The
temperature was measured with a cromel-alumel thermocouple. The
re ow bonding process of the prebonded chip stacks was monitored at
an pressure of 10 6 torr.
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2.4. Comparison of ux-assisted and uxless FC
technologies
Figure 2.8.: A): Picture of a bumped wafer using the LETI OPTO layout as
photolithography mask. (B-C): Drawings of single dies samples used
for self-alingment measurement after dicing. (D): Picture of the chip
with structured thick resist, ready for evaporation. (E): SEM-picture
of the structured thick resist. (F) Part of the scale structure in the
corner of the chips used for quanti cation of self-alignment. Design
is courtesy of LETI.
To compare FC technologies developed at MIC and LETI it was de-
cidedto use a photolithographymask designedby LETI(named OPTO
mask) for all these processes. The mask design is depicted in g. 2.8.
The size of a single chip is 5x10 mm. Notice the di erencee in the
diameters of the UBM and the resist structure respectively. The di-
ameter of the as-deposited solder bumps is almost twice the diameter
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2.4. Comparison of ux-assisted and uxless FC technologies
of the underlying UBM ( g. 2.8 D). Due to an extraordinary large
dewetting during re ow, large re own solder bump heights can thus
be obtained with only a few m as-deposited solder.
The purpose of the design were to FC bond photonic devices, and to
measure vertical and horizontal alignment using a Michelson Interfer-
ometer 94].
The di erences in processing (appendix B) is re ected in the self-
alignment sequences performed at LETI and MIC.
The approach employed by MIC was explained in the previous sections
in this chapter. The approach used by LETI will be explained in
the following section. The two di erent self-alignment approaches are
illustrated in g. 2.9.
Figure 2.9.: The two bonding sequences as they are being approached at LETI
and MIC respectively.
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2.4.1. Fluxless self-alignment using evaporated solder
Figure 2.10.: Sequence of video-pictures during self-alignment of prebonded sol-
der bumps. (A): A section of the stacked chip before self-alignment
(viewed through the glass chip). (B): A section of the stacked chip
after self-alignment.
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Glass chips were prebonded, using the previous described parameters,
to as-evaporated Sn solder bumps on a Si substrates. After prebonding
the chip-stacks were re own in the RTA. The glass samples could thus
move freely and showed a large movement during re ow bonding. The
video still-pictures in g. 2.10 show that the TSM on the glass die
moves considerably ( 25 m) during re ow bonding, ending up as
centered to the underlying spherical solder balls.
The circular TSM (diameter 60 m) can be seen as small black circles
in the pictures. The solder occurs as grey circles (diameter 160 m).
The alignment occurred within less than 5 seconds after the melting
point of the solder was reached.
2.4.2. Flux-assisted self-alignment using electroplated
solder
The bumped wafers are initially re own on a hotplate in a controlled
N2 atmosphere using ux. After cleaning of ux residues the samples
are diced and transferred to a pick-and-place bonder. The bonder is
equipped with a microscope and an integrated video camera ( g. 2.11
A).
Figure 2.11.: The SC940, pick-and-place bonder. Purging time: 120 sec. Heat-
ing rate: 2 C/sec. Cooling rate: 5 C/sec (during purging
with N2 gas).
The chip and substrate is aligned with an accuracy of +/-20 m. No
force or heat is applied during the stacking sequence. When all chips
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have been placed onto the substrates, a dome is descended over the
stacks and purged with N2 or N2/H2 gas. Re ow bonding and self-
alignment is achieved by a heating chuck ( g. 2.11 B).
After re ow bonding, the self-alignment is measured using a Michelson
interferometer. The measurement principle is explained in g. 2.12:
Figure 2.12.: Principle in CSO-equipment focusing. Moving of the Si-chip-stack
vertically and horizontally results in intensity maxima of the re-
ected IR-radiation 4. Picture is courtesy of LETI.
The interferometer works by directing a focused IR-laser beam down
through a stacked Si-chip sample and measuring the re ected IR-
radiation when the sample is moved vertically and horizontally. When
the chip-stack is being moved vertically, using a micrometer handle,
a re ection will occur when the focal point of the IR-beam coincide
with the faces of the double sided polished Si-chips (marked with A,
B and C in g. 2.12 and g. 2.13). The positions of the faces can
then be identi ed from the intensity maximum in the back-scattered
IR-radiation ( g. 2.13). The horizontal (X-Y) self-alignment are mea-
sured using similar principles:
The IR-laser beam is placed at a corner on the chip stack, nearby
the 10 m wide metal scale lines on the TSM-chip ( g. 2.8F). The
vertically position of the stack is then adjusted in order to obtain a in-
tensity maximum in the backscattered IR radiation from face C in g.
2.12. The metal scale lines on the TSM-chip and on the substrate-chip
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2.4. Comparison of ux-assisted and uxless FC technologies
will be separated horozontally by exactly 35 m when the chips are
perfectly self-aligned. A series of maxima in the re ected IR-radiation
will then occur when the IR beam is scanned horizontally across the
surface of the stack ( g. 2.12). Deviation from the optimum 35 m in
the relative positions of the intensity peaks is a direct measure of the
self-alignment accuracy. It is possible to estimate the alignment with
an accuracy of +/- 0.01 m.
Figure 2.13.: Three intensity maximums in the re ected IR-radiation. The
largest peak corresponds to the upper surface of the chip-stack,
and the two smaller intensity peaks originate from the two inner
surfaces. The distance the sample has moved between these two
maximums corresponds to the height of the bumps in the stack.
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2.4.3. Evaporated solder bumps
Figure 2.14.: As evaporated Sn solder bumps. (A): Before lift-o . Notice the
straight resist sidewalls. (B-C): After lift-o . (D): The surface of
the evaporated in high resolution. A microscope picture of the same
surface is inserted in the upper right corner.
The as-evaporated solder is shown in g 2.14. Due to the thickness
of the AZ4562 resist (22 m) used at MIC, it is possible to evaporate
quite thick layers while still obtaining a good lift-o process. Neverthe-
less, although the solder is evaporated, the surface is somewhat rough.
The reproducibility is therefore +/- 1 m for 10 m as-deposited sol-
der height.
As a result of the pronounced dewetting, dictated by the design of the
mask, it became soon obvious during the experiments that optimiza-
tion of the thick resist processing was an extremely important factor.
It was very important to perform a thoroughly resist post baking (6
min at 90 C). The temperature of the resist during evaporation had
furthermore to be kept well below the glass transition temperature.
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This has avoided unwanted interaction of the solder into the photore-
sist (also referred to as "bleeding").
Figure 2.15.: Evaporated solder bumps re ow in N2 at MIC. Notice the circular
residues around the re ow solder bumps indicating the area from
which the solder has dewetted. (D): The rim of the as-evaporated
solder is still distinct after re ow.
During the work, It became evident that it was extremely di cult to
achieve satisfactory dewetting due to several (some very surprising)
failure modes:
Bleeding of the resist during evaporation ( g. 2.16 A), due to
an insu cient post-baking and/or to high temperatures during
evaporation.
Complete consumption of the UBM because of overheating dur-
ing re ow ( g. 2.16 B)
Excessive oxidation of the solder as a consequence of a too high
oxygen partial pressure during re ow, or during evaporation (see
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Prebonding and re ow soldering
section 4.4)
Sticking of the solder to the SiO2-substrate, which will be exam-
ined more closely in section 4.6.
Figure 2.16.: Di erent possible failure modes.
However, after extensive process and re ow optimization it was possi-
ble to obtain unimpeded and very convincing uxless dewetting of the
as-evaporated solder in high vacuum and in N2 at MIC ( g. 2.15).
The solder is re own in less than 10 seconds, in which the temperature
was raised to 250 C using a focused IR-heating lamp ( g. 2.7). Pre-
bonding of these samples in their as-deposited state, using glass TSM-
chips, resulted in self-alignment during the following re ow-soldering
step ( g. 2.10). However, the quantity of the self-alignment using
evaporated solder has not yet been investigated.
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2.4. Comparison of ux-assisted and uxless FC technologies
2.4.4. Electroplated Sn/Pb(60/40) solder bumps
Figure 2.17.: Electroplated Sn/Pb (60/40) solder re own in N2 using ux. (A):
As-electroplated bump. Notice the porous sponge-looking structure
of the solder and the mushroom-shaped bump. (B-D): Re own
electrodeposited solder bumps using ux. (D) The di erent metal
phases are clearly visible in the solder bump.
As-electroplated Sn/Pb(60/40)-solder ( g. 2.17) has a spongy porous
structure whenexaminedinhighresolution(SEM). Solderbath residues
may thus easily be trapped inside the solder. Consequently, residues
are removed by a 15 min. baking step in N2 at 150 C in order to
degas the solder prior to re ow. After prebaking, ux is applied to the
wafer/solder which then is dried. The rst re ow step ( g. 2.9) did
either take place in N2 streamed re ow bonder, or in an N2-purged (2
min.) bell jar before descending the wafer onto a 230 C hot plate for
10 seconds.
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Prebonding and re ow soldering
Figure 2.18.: Some failure modes occurring when using ux. (A): Flux residues
remains after cleaning. (B-C): Entrapments of ux and/or residues
from the electroplating bath makes some of the bumps expand dras-
tically during re ow. (D): X-ray microscopy showing the hollow
inside of some expanded bumps.
Due to entrapments of ux residues and/or solder bath residues, some
of the solder balls blow up like a balloon when the organic residues
expands inside the molten solder during re own ( g. 2.18). This is
obviously not desirable because of the huge di erence in the solder
bump height and due to reliability considerations. It was therefore
necessary to re ow the solder two times before dicing and stacking.
After dicing and stacking ux was applied to the soldered substrate
before self-alignment in the N2-streamed SC940 dome ( g. 2.11). The
self-alignment was measured with the Michelson inteferometer and 10
LETI SnPb(60/40) solder bumped chip-stacks showed very impressive
e self-alignment properties:
Height before re ow: 12 m
62
