Computer Architecture.

1. William Stallings
Computer Organization
and Architecture
8th Edition
Chapter 3
Top Level View of Computer
Function and Interconnection

2. What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed

3. Function of Control Unit
• For each operation a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals

4. Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• instructions need to get into the system
and results out
—Input/output
• Temporary storage of code and results is
needed
—Main memory

5. Computer Components:
Top Level View

6. Instruction Cycle
• Two steps:
—Fetch
—Execute

7. Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
• Instruction loaded into Instruction
Register (IR)
• Processor interprets instruction and
performs required actions

8. Execute Cycle
• Processor-memory
—data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations

9. Example of Program Execution

10. Instruction Cycle State Diagram

11. Interrupts
• In early years of computing, processor has to wait for
the signal for processing, so processor has to check each
and every hardware and software program in the system
if it has any signal to process.
• This method of checking the signal in the system for
processing is called polling method.
• In this method the processor has to waste number of
clock cycles just for checking the signal in the system, by
this processor will become busy unnecessarily. If any
signal came for the process, processor will take some
time to process the signal due to the polling process in
action. So system performance also will be degraded and
response time of the system will also decrease.

12. Interrupts
• So to over this problem engineers
introduced a new mechanism, in this
mechanism processor will not check for
any signal from hardware or software but
instead hardware/software will only send
the signal to the processor for processing.
• The signal from hardware or software
should have highest priority because
processor should leave the current
process and process the signal of
hardware or software. This mechanism of
processing the signal is called interrupt of
the system.

13. Interrupt
• “Interrupt is a signal which has highest
priority from hardware or software which
processor should process its signal
immediately”

14. Types of Interrupts:
• Although interrupts have highest priority
than other signals, there are many type of
interrupts but basic type of interrupts are
1. Hardware Interrupts:
If the
signal for the processor is from external
device or hardware is called hardware
interrupts.
Example: from keyboard we will press the
key to do some action this pressing of key
in keyboard will generate a signal which is
given to the processor to do action, such
interrupts are called hardware interrupts.

15. Hardware interrupts can be classified into
two types.
• Maskable Interrupt: The hardware
interrupts which can be delayed when a
much highest priority interrupt has
occurred to the processor.
• Non Maskable Interrupt: The hardware
which cannot be delayed and should
process by the processor immediately.

16. 2. Software Interrupts
Software interrupt can also divided in to two
types. They are
• Normal Interrupts: the interrupts which
are caused by the software instructions
are called normal interrupt
• Exception: unplanned interrupts while
executing a program is called Exception.
For example: while executing a program if
we got a value which should be divided by
zero is called a exception.

17. Program Generated Interrupts
• Most computers have an instruction that
generates an internal interrupt.
• Program generated interrupts are a
means for user programs to call a function
of the operating system

18. Transfer of Control via Interrupts

19. Interrupt Handling
• We know that instruction cycle consists of
fetch, decode, execute and read/write
functions.
• After every instruction cycle the processor
will check for interrupts to be processed
• if there is no interrupt is present in the
system it will go for the next instruction
cycle which is given by the instruction
register.

20. Interrupt Handling
• If there is an interrupt present then it will
trigger the interrupt handler
• the handler will stop the present
instruction which is processing and save
its configuration in a register and load the
program counter of the interrupt from a
location which is given by the interrupt
vector table.

21. Instruction Cycle with Interrupts

22. Interrupt Handling
• After processing the interrupt by the
processor interrupt handler will load the
instruction and its configuration from the
saved register, process will start its
processing where it’s left.
• This saving the old instruction processing
configuration and loading the new
interrupt configuration is also called as
context switching.
• The interrupt handler is also called as
Interrupt service routine (ISR).

23. Instruction Cycle (with Interrupts) -
State Diagram

24. Program Flow Control

25. Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted
program

26. • the processor and the operating system
are responsible for suspending the user
program and then resuming it at
the same point

27. Program Timing
Short I/O Wait

28. Program Timing
Long I/O Wait

29. Multiple Interrupts
• Disable interrupts
—Processor will ignore further interrupts while
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt

30. Multiple Interrupts - Sequential

31. Multiple Interrupts – Nested

32. Time Sequence of Multiple Interrupts

33. INTERCONNECTION STRUCTURES
• A computer consists of a set of
components or modules of three basic
types (processor, memory, I/O) that
communicate with each other. a
computer is a network of basic modules.
• There must be paths for connecting the
modules.
• The collection of paths connecting the
various modules is called the
interconnection structure.

34. Computer Modules

35. Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
—Read
—Write

36. Input/Output Connection(1)
• I/O is functionally similar to memory.
• There are two operations, read and write.
• An I/O module may control more than one
external device. We can refer to each
external device as a port and give each a
unique address (e.g., 0, 1,...,M– 1).
• an I/O module may be able to send
interrupt signals to the processor

37. CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts

38. The interconnection structure must
support the following types of transfers:
• Memory to processor: The processor
reads an instruction or a unit of data from
memory.
• Processor to memory:The processor
writes a unit of data to memory.
• I/O to processor:The processor reads data
from an I/O device.

39. • Processor to I/O: The processor sends
data to the I/O device.
• I/O to or from memory: For these two
cases, an I/O module is allowed to
exchange data directly with memory,
without going through the processor,
using direct memory access (DMA).

40. Buses
• A bus is a communication pathway
connecting two or more devices.
• it is a shared transmission medium.
• A signal transmitted by any one device is
available for reception by all other devices
attached to the bus
• There are a number of possible
interconnection systems
• Single and multiple BUS structures are
most common
• e.g. Control/Address/Data bus
• e.g. Unibus (DEC-PDP)

41. Buses
• A bus consists of multiple
communication pathways, or lines.
• Each line is capable of transmitting
signals representing binary 1 and binary
0.
• 8-bit unit of data can be transmitted
over eight bus lines.
• A bus that connects major computer
components (processor, memory, I/O)
is called a system bus.

42. Bus Structure
• A system bus consists about 50 to
hundreds of separate lines.
• Each line is assigned a particular meaning
or function.
• The lines can be classified into three
groups (data, address, and control lines).
• In addition, there may be power
distribution lines that supply power to the
attached modules.

43. Data Bus
• Data lines provide a path for moving data
among system modules.
• These lines, collectively, are called the
data bus
—Remember that there is no difference between “data”
and “instruction” at this level
• The data bus may consist of 32, 64, 128,
or even more separate lines, the number
of lines being referred to as the width of
the data bus.
• Because each line can carry only 1 bit at a
time, the number of lines determines how
many bits can be transferred at a time.

44. Address bus
• Identify the source or destination of data
• For example, if the processor wishes to
read a word (8, 16, or 32 bits) of data
from memory, it puts the address of the
desired word on the address lines.
• Width of the address bus determines the
maximum possible memory capacity of
the system.
• Address lines are also used to address I/O
ports.

45. Address Bus
• Higher-order bits are used to select a
particular module on the bus, and the
lower-order bits select a memory location
or I/O Port.
• For example, on an 8-bit address bus,
address (01111111) below might
reference location 128 in a memory
module (module 0),
• and address 10000000 refer to devices
attached to an I/O module (module 1).

46. Control Bus
• Data and address lines are shared by all
components, there must be a means of
controlling their use.
• Control signals transmit both command
and timing information among system
modules.
• Timing signals indicate the validity of data
and address information.
• Command signals specify operations to be
performed.

47. Control Lines Include
• Memory write: Causes data on the bus to
be written into the addressed location
• Memory read: Causes data from the
addressed location to be placed on the
bus
• I/O write: Causes data on the bus to be
output to the addressed I/O port
• I/O read: Causes data from the addressed
I/O port to be placed on the bus
• Transfer ACK: Indicates that data have
been accepted from or placed on the bus

48. • Bus request: Indicates that a module
needs to gain control of the bus
• Interrupt request: Indicates that an
interrupt is pending
• Interrupt ACK: Acknowledges that the
pending interrupt has been recognized
• Clock: Is used to synchronize operations
• Reset: Initializes all module

49. Bus Interconnection Scheme