1. Avinash Malik <avinash.malik@auckland.ac.nz>
+6421957581 https://unidirectory.auckland.ac.nz/profile/avinash-malik
Department of Electrical and Computer Engineering, University of Auckland Auckland, NZ
DATE OF BIRTH
22/10/1983
EDUCATION
University of Auckland, New Zealand 2006-2010
Doctor of Electrical and Computer Engineering (PhD)
• Thesis Topic: “Principia Lingua SystemJ”, designed a new system level language called SystemJ,
which follows the Globally Asynchronous Locally Synchronous (GALS) model of computation.
University of Auckland, New Zealand 2002-2006
Bachelor of Electrical and Electronic Engineering, First Class Honors
• Final year project topic: “A Discrete Time Recurrent Neural Network”, dealt with a more efficient
algorithm for learning and recall of time dependent activities such as robotic arm movement, and
motion tracking.
EMPLOYMENT
University of Auckland May 2013 – Current
Lecturer
Projects:
• Loan portfolio optimization for peer to peer lending: The aim of the project is to use statistical machine
learning techniques to build viable investment portfolio for investing in peer to peer loans. This project
is being carried out by a PhD student under my supervision.
• Time series analysis for feature extraction from electro-cardiograms (ECG): The aim of the project is
to build a real-time heart model for testing and verification of cyber-physical cardiac medical devices.
Time series analysis is used to extract the parameters for the heart model from patient ECG. This
project is being carried out in conjunction with a PhD student I am supervising.
• Model checking safety critical software systems: The aim of the project was to develop a new pro-
gramming language and associated tools for development of correct by construction safety critical
software systems. This project was completed in conjunction with my PhD student in 2014.
• Timing analysis and optimization of safety critical embedded systems: The aim of the project was to
perform worst case execution time analysis on new multi-core processor architectures for real-time
systems. This project was completed in conjunction with my PhD student in 2016.
• Compiler development for hybrid control systems: The aim of the project was to develop the compiler
and related tools for developing cyber-physical control software for competing with Matlab/Simulink
from Mathworks. I developed the tool-set as a domain specific language in Haskell.
IBM Research April 2012-May 2013
Research Staff Member
Projects:
• Graph based techniques for partitioning work loads onto Exascale architectures: In this project I
consider workloads such as traffic monitoring systems in Dublin city and partitioning/executing them
onto Exascale machines being developed in my team.
• Performance improvements in IBM products such as IBM Infosphere: In this project I am involved
with improving the performance of IBM’s streaming platform Infoshpere onto GPU architectures.
• Evaluating and promoting use of IBM’s X10 programming infrastructure for Exascale machines:
IBM’s new upcoming language X10 is targeted at programming next generation super-computers.
I am involved in evaluating the performance and suitability for target workloads and the underlying,
light based, reconfigurable system topology.
Dept of computer science TCD, Ireland April 2012-Current
Visiting Research Associate
Projects:

2. • Developing new multi-paradigm programming languages combining streaming and data-parallel com-
putations with effective dependent type systems.
• Developing auto vectorization techniques for non-affine loop accesses using llvm compiler infrastruc-
ture.
Trinity College Dublin, Ireland and IBM Research, Dublin, Ireland November 2010-April 2012
Post-doctoral fellow and Researcher
Projects:
• Compiler optimizations for increased throughput of streaming applications on future Exascale com-
puters.
• Working on compilation of non standard high performance application for the next generation Exas-
cale computer in design at IBM Research Ireland in collaboration with IBM T. J Watson Research
Center, NY, USA.
INRIA Grenoble-Rhône-Alpes, France December, 2009-October, 2010
Post-doctoral researcher
Projects:
• Compiling Parametrized reconfigurable DataFlow Graphs for distributed computing platforms in col-
laboration with STMicroElectronics, Ottawa, Canada.
• Code mobility and dynamic creation of processes in a Globally Asynchronous Locally Synchronous
(GALS) model of computation.
• Semantic and type analysis of mobile GALS programs.
• Efficient and distributed implementation of GALS programs.
• Formal verification of GALS programs.
University of Auckland March, 2006-August, 2009
Doctoral candidate
Projects:
• Proposing formal semantics of GALS language SystemJ.
• Implementing the compiler and runtime support for SystemJ.
• Designing and implementing a new processor supporting execution of GALS languages.
TEACHING, SUPERVISION AND WORK EXPERIENCE
University of Auckland May, 2013 - current
Lecturer
• Supervised 1 post-doctoral fellow, 5 PhD students, 4 masters of engineering student, and more than
10 bachelor of engineering students.
• Generating $196, 041 NZD in research income.
• Teaching C++ and Java programming – class of 250 plus students.
• Teaching real-time operating systems – class of 30 students.
• Teaching formal verification of software systems – class of 30 students.
• Teaching computer networking stack – class of 50 students.
• Teaching computer architecture – class of 100 plus students.
• Provided services as the research seminar enabler at the University of Auckland.
• Provided professional services by arranging the 18th
IEEE ISORC 2015 in Auckland, NZ.
• Awarded recognition by the vice-chancellor of the University of Auckland, for participating in the
mobile learning and teaching group at the university in 2014.
University of Auckland 2005- November, 2010
Graduate Teaching Assistant/Invited Lecturer
UniServices, Auckland September, 2009-July, 2010
Consultant
• Writing funding applications for a start up (SystemJ Technologies) in collaboration with UniServices,
based on my PhD.
• Exhibiting SystemJ technology at various entrepreneurial conventions.

3. • Taking part in Voice of Market forum organized by Uniservices and Paragon Development, San Fran-
cisco, California, USA.
• Training and providing expert advice to clients using SystemJ, especially, at ITRI (Industrial and
Technology Research Institute, Hsinchu, Taiwan), for their smart surveillance/tracking systems, April
2009.
International Marine Services, Auckland, NZ September, 2005-January, 2006
Consultant Engineer
• Developed analogue circuits for yacht stabilization.
• Developed and implemented software for propellers and bow-thrusters using AVR micro-controllers
and C.
Wellington Drive Technology Ltd, Auckland, NZ November, 2003-January, 2004
Test Engineer
• Assembled and tested small brush less DC-motors.
SKILLS
Programming Languages:
• Proficient in C/C++, Java, LATEX, VHDL, Verilog, Shell scripting, x86 assembler, Esterel, Matlab, and
Simulink, Integer Linear Programming (ILP), CPLEX solver, Uppaal Model checker, Ocaml, Haskell.
Operating Systems:
• Proficient in Linux and Windows.
Scholarships and Prizes:
• Awarded the Irish Government and Trinity College Fellowship for post-doctoral research at Trinity
College in conjunction with IBM.
• New Zealand smelters award for best performance in control systems engineering.
• University of Auckland doctoral scholarship for the full course of my PhD.
• Overall undergraduate class rank, 5/100, Dean’s list.
Miscellaneous:
• Proficient in TCP/IP networking, software configuration management systems (both central and dis-
tributed).
• Strong verbal and written communication skills, excellent troubleshooting and debugging skills.
PUBLICATIONS
Refereed (13 Journal and 19 Conference publications):
1. Zhenmin Li, HeeJong Park, Avinash Malik, Kevin I-Kai Wang, Zoran Salcic, Boris Kuzmin, Michael
Glas, Jurgen Teich, Using Design Space Exploration for Finding Schedules with Guaranteed Reac-
tion Times of Synchronous Programs on Multi-core Architecture, Journal of Systems Architecture,
Elsevier, 2017 (in print).
2. Sidharta Andalam, Avinash Malik, Partha Roop and Mark Trew, Benchmark: Hybrid automata model
of the heart for formal verification of pacemakers, Workshop on Applied Verification for Continuous
and Hybrid Systems (ARCH’ 2016).
3. Andrew Anderson, Avinash Malik, David Gregg: Automatic Vectorization of Interleaved Data Re-
visited. ACM Transactions on Architecture and Code Optimization, TACO 12(4): 50:1-50:25 (2016)
4. Long Cheng, Avinash Malik, Spyros Kotoulas, Tomas E. Ward, Georgios Theodoropoulos: Fast Com-
pression of Large Semantic Web Data Using X10. IEEE Transactions Parallel Distributed Systems,
TPDS 27(9): 2603-2617 (2016)
5. HeeJong Park, Zhenmin Li, Avinash Malik, Zoran A. Salcic: Times Square-Marriage of Real-Time
and Logical-Time in GALS and Synchronous Languages. Signal Processing Systems 84(1): 163-180,
Springer (2016)

4. 6. Nathan Allen, Sidharta Andalam, Partha S. Roop, Avinash Malik, Mark Trew, Nitish Patel: Mod-
ular code generation for emulating the electrical conduction system of the human heart. 19th
IEEE
International Design Automation and Test in Europe Conference, DATE 2016: 648-653, Dresden
Germany.
7. Sidharta Andalam, Harshavardhan Ramanna, Avinash Malik, Partha S. Roop, Nitish Patel, Mark L.
Trew: Hybrid automata models of cardiac ventricular electrophysiology for real-time computational
applications. 38th
IEEE Engineering in Medicine and Biology Society Conference, EMBC 2016:
5595-5598, Orlando, Florida.
8. HeeJong Park, Avinash Malik, Zoran A. Salcic: Compiling and verifying SC-SystemJ programs for
safety-critical reactive systems. Computer Languages, Systems & Structures 44: 251-282 (2015)
9. Avinash Malik, David Gregg: Heuristics on Reachability Trees for Bicriteria Scheduling of Stream
Graphs on Heterogeneous Multiprocessor Architectures. ACM Transactions Embedded Computing
Systems, TECS 14(2): 23:1-23:26 (2015)
10. HeeJong Park, Avinash Malik, Zoran A. Salcic: Scheduling Globally Asynchronous Locally Syn-
chronous Programs for Guaranteed Response Times. ACM Transactions Design Automation Elec-
tronic Systems, TODAES 20(3): 40:1-40:25 (2015)
11. Jin Woo Ro, Partha S. Roop, Avinash Malik: Schedule Synthesis for Time-Triggered Multi-hop Wire-
less Networks with Retransmissions. 18th
IEEE International Symposium on Real-time Computing,
ISORC 2015: 94-101, Auckland, NZ
12. Dez Packwood, Manu Sharma, Ding Ding, HeeJong Park, Zoran A. Salcic, Avinash Malik, Kevin I-
Kai Wang: FPGA-based Mixed-Criticality Execution Platform for SystemJ and the Internet of Indus-
trial Things. 18th
IEEE International Symposium on Real-time Computing, ISORC 2015: 174-181,
Auckland, NZ
13. Zhenmin Li, Avinash Malik, Zoran A. Salcic: Reducing Worst Case Reaction Time of Synchronous
Programs on Chip-multiprocessors with Application-Specific TDMA Scheduling. 13th
ACM Interna-
tional Workshop on Java Technologies for Real-time and Embedded Systems, JTRES 2015: 11:1-11:9,
Paris, France.
14. Wei-Tsun Sun, Zoran A. Salcic, Alain Girault, Avinash Malik: libDGALS: A library-based approach
to design dynamic GALS systems. 9th
IEEE International Symposium on Industrial Embedded Sys-
tems, SIES 2014: 104-111, Pisa, Italy.
15. HeeJong Park, Avinash Malik, Zoran A. Salcic: Times square - marriage of real-time and logical-
time in GALS and synchronous languages. 20th
IEEE International Conference on Embedded and
Real-time Computing Systems and Applications, RTCSA 2014: 1-10, Chongqing, China.
16. Zhenmin Li, Avinash Malik, Zoran A. Salcic: TACO: A scalable framework for timing analysis and
code optimization of synchronous programs. 20th
IEEE International Conference on Embedded and
Real-time Computing Systems and Applications, RTCSA 2014: 1-8, Chongqing, China.
17. HeeJong Park, Avinash Malik, Muhammad Nadeem, Zoran A. Salcic: The Cardiac Pacemaker: Sys-
temJ versus Safety Critical Java. 12th
ACM International Workshop on Java Technologies for Real-
time and Embedded Systems, JTRES 2014: 37, Niagara Falls, NY, USA.
18. Aravind Vasudevan, Avinash Malik, David Gregg: An improved simulated annealing heuristic for
static partitioning of task graphs onto heterogeneous architectures. 20th
IEEE International Confer-
ence on Parallel and Distributed Systems, ICPADS 2014: 95-102, Hsinchu, Taiwan.
19. H.J. Park, Avinash Malik, Zoran A. Salcic: WYPIWYE automation systems - An intelligent manu-
facturing system case study. 19th
IEEE Emerging Technology and Factory Automation Conference,
ETFA 2014: 1-8, Barcelona, Spain.

5. 20. H.J. Park, Z. Salcic, K-I. Wang, U. Atmojo, W-T. Sun, Avinash Malik, A New Design Paradigm
for Designing Reactive Pervasive Concurrent Systems with an Ambient Intelligence Example. IEEE
International Symposium on Distributed Processing with Applications (ISPA) 2013, Melbourne, Aus-
tralia.
21. S. Muralidharan, A. Vasudevan, Avinash Malik, D. Gregg, A framework for design space exploration
for HPC architectures. IEEE International Symposium on Distributed Processing with Applications
(ISPA) 2013, Melbourne, Australia.
22. Avinash Malik, D. Gregg, Orchestrating stream graphs using model-checking, ACM Transactions on
Architecture and Code Optimization (TACO), January, 2013.
23. Avinash Malik, Z. Salcic, S. Lee, A. Walker, GALS-HMP: A Heterogeneous Multiprocessor for
Embedded Applications. ACM Transactions on Embedded Computing Systems (TECS), 12(1s): 58:1-
58:26 (2013).
24. Avinash Malik, A. Girault, Z. Salcic, Formal semantics, compilation and execution of the GALS
programming language DSystemJ. IEEE Transactions on Parallel and Distributed Systems (TPDS),
July 2012.
25. Avinash Malik, Z. Salcic, C. Chong, S. Javed, System-level approach to design of a smart distributed
surveillance system using SystemJ. ACM Transactions on Embedded Computing Systems (TECS), in
publication, June, 2011.
26. Avinash Malik, A. Girault, Z. Salcic, A GALS Language for Dynamic Distributed and Reactive Pro-
grams. In 11th
International Conference on Application of Concurrency to System Design (ACSD),
Newcastle Upon Tyne, UK, June, 2011.
27. Avinash Malik, A. Girault, Z. Salcic, DSystemJ: A language for programming GALS dynamic sys-
tems. Poster presentation, In 8th
ACM/IEEE International Conference on Formal Methods and Mod-
els for Codesign (MEMOCODE), Grenoble, France, July 2010.
28. W. Sun, Z. Salcic, Avinash Malik, LibGALS: A Library for GALS Systems Design and Modeling, In
15th
Asia South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, January, 2010.
29. Avinash Malik, Z. Salcic, P. S. Roop, A. Girault, SystemJ: A GALS Language for System Level
Design. In Computer Languages, Systems and Structures, Elsevier (COMLAN), 36(4), pp 317–344,
2010.
30. Avinash Malik, Z. Salcic, A. Girault, A. Walker, S. C. Lee, A customizable multiprocessor for Glob-
ally Asynchronous Locally Synchronous execution. In ACM International Conference on Java Tech-
nologies for Real Time and Embedded Systems (JTRES), Madrid, Spain, pp. 120-129, 2009.
31. Avinash Malik, Z. Salcic, P. S., Roop, SystemJ compilation using the Tandem Virtual Machine Ap-
proach. ACM Transactions on Design Automation of Electronic Systems (TODAES), 14(3), pp 1–34,
2009.
32. Avinash Malik, Z. Salcic, P. S. Roop, Tandem virtual machine: An efficient execution platform for
GALS language SystemJ, Computer Systems Architecture Conference, 2008. In 13th
Asia-Pacific
Conference (ACSAC), pp.1-8, 4-6 August, 2008.
Non-refereed:
1. Eugene Yip, Sidharta Andalam, Partha S. Roop, Avinash Malik, Mark Trew, Weiwei Ai, Nitish
Patel: Towards the Emulation of the Cardiac Conduction System for Pacemaker Testing. CoRR
abs/1603.05315 (2016)
2. Avinash Malik, Partha S. Roop: A unified framework for modeling and implementation of hybrid
systems with synchronous controllers. CoRR abs/1501.05936 (2015)

6. 3. Avinash Malik, Partha S. Roop, Sidharta Andalam, Eugene Yip, Mark Trew: A synchronous render-
ing of hybrid systems for designing Plant-on-a-Chip (PoC). CoRR abs/1510.04336 (2015)
4. Long Cheng, Avinash Malik, Spyros Kotoulas, Tomas E. Ward, Georgios Theodoropoulos: Scalable
RDF Data Compression using X10. CoRR abs/1403.2404 (2014)
5. Avinash Malik, A. Girault, Z. Salcic, Design and Implementation of GALS languages, SYNCHRON’2011,
Melun, France.
6. Avinash Malik, Z. Salcic, P. S. Roop, SystemJ a GALS Language and its Operation Semantics, Tech-
nical Report-TR656, University of Auckland, 2006
7. Avinash Malik, Z. Salcic, P. S. Roop, Efficient Compilation of GALS language SystemJ, Technical
Report-TR655, University of Auckland, 2006
8. Avinash Malik, A. Girault, Z. Salcic, The DSystemJ programming language for dynamic GALS
systems: it’s semantics, compilation, implementation, and run-time system, INRIA Research Report,
RR – 7346, June, 2010.
Under review:
1. Avinash Malik, Cameron Walker, Michael O’Sullivan, Oliver Sinnen, SMT Formulation for Optimal
Scheduling of Task Graphs with Communication Delay, Elsevier Journal of Computers and Operations
Research.
2. Ke Ran, Avinash Malik, Optimization of loan investment portfolio for peer to peer lending systems,
Statistical Analysis and Data Mining, Wiley Journal.
3. Weiwei Ai, Nitish Patel, Partha Roop, Avinash Malik, MArk Trew, Sidhartha Andalam, Eugene Yip,
Nathan Allen, A parametric computational model of the action potential of pacemaker cells, IEEE
Transactions of Biomedical Engineering.
4. Avinash Malik, HeeJong Park, Muhammad Nadeem, Zoran Salcic, Compiler assisted memory man-
agement for safety-critical hard real-time applications, Springer Real-time Systems Journal.
5. Avinash Malik, Partha Roop, Theo Steger, Nathan Allen, Emulation of cyber-physical systems using
IEC-61499, IEEE Transactions on Industrial Informatics.
6. Eugene Yip, Sidhartha Andalam, Partha Roop, Avinash Malik, Mark Trew, Weiwei Ai, Nitish Patel,
Towards the Emulation of the Cardiac Conduction System for Pacemaker Validation, ACM Transac-
tions on Cyber-Physical Systems.
REFEREES
• Dr. Roopak Sinha, Senior Lecturer, AUT, Auckland, NZ
Email: rsinha@aut.ac.nz
• Dr. Partha Roop, Associate Professor, University of Auckland, Auckland, NZ
Email: p.roop@auckland.ac.nz
• Dr. David Gregg, Associate Professor, Trinity College Dublin, Ireland
Email: david.gregg@cs.tcd.ie
• Dr. Alain Girault, Senior Researcher, INRIA, France
Email: alain.girault@inria.fr