1. Curriculum Vitae
Adrian O'Shaughnessy
Personal Details
Bawnmore Cottage https://www.linkedin.com/in/adrianoshaughnessy
Ballinakill +353 87 7496482(m)
Co Laois
HYPERLINK "mailto:adrian.oshaughnessy@gmail.com"
adrian.oshaughnessy@gmail.com _________________________________________________________
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Profile
Widely considered to be an expert in nanometer and finFet layout. Extensive layout management and principal lead
experience at 10nmFF, 16nmFF, 20nm, 28nm, 32nm, 45nm, 65nm and 90nm full custom mask design with some
experience with place and route physical design. Eighteen years’ expert experience in RF/Baseband/Power products.
Extensive layout lead experience in putting complete mixed-signal IC’s together. Proven capability to interface with
analog design engineers in product definition phase to include: floor planning, power routing, ESD, block physical
design size estimations, layout effort estimations, and other tasks. Proven team leadership capabilities. Including
defining, directing and reviewing the other layout engineers work. Able to interface with digital P&R team in
implementing both digital-on-top and analog-on-top flows. Good understanding of packaging needs and constraints
including interface with packaging team. Superior layout skills including critical device and signal layout
techniques. Understanding of multiple voltage domains and techniques to ensure proper physical designs. Expert
knowledge of physical design techniques for volume manufacturing
Has a deep understanding of various silicon process effects that can kill silicon performance such as CD variation,
Dishing, Implant shadowing, Mask misalignment, Over/Under Etch, Lithography shadowing etc. Extensive
expertise on every conceivable verification suite out there; Calibre, Assura, Hercules, PVS etc. Experienced team
leader with a proven track record of meeting critical deadlines and design tapeouts. Has trained countless Design
and Layout Engineers across Germany, France, UK, Ireland and the States. Excellent communicator with an ability
to develop and maintain relationships at all levels. Highly experienced in all aspects of IC layout including laying
out of: LNA, Mixer, VGA/PGA, DAC, ADC, Bias, OP-Amp, Filters, VCO, PLL, Charge-pump, Divers, I/O ring etc
Experienced public speaker who has spoken and presented at various technical conferences.
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Key Competencies and Skills
Highly motivated team lead specializing in team/project/management of deep sub-micron and finFet layout.
Collaborative leader who develops positive working relationships
Excellent track record in leadership and innovation consulting
Proven ability to meet critical deadlines and design tapeouts
Significant knowledge in all aspects of expert layout techniques
Excellent creativity and problem-solving ability
Excellent media skills, including considerable experience in public speaking
Endura Technologies June 15 – to date
Game changing, patented technology for the next generation of application processors. Improving energy efficiency
for all operating modes including standby.
Principal Lead Layout
Successful management and tapeout of numerous 10nmFF and 28nm chips.
Participate in all critical aspects of product implementation including bump map definition and placement, ESD
implementation, chip level floor-planning, block level creation, debug and full verification, power routing concepts
Develop detailed layout guidelines for best practice strategy to reduce risk on silicon such as latch-up prevention and
parasitic reduction.

2. Guide layout team towards successful tape outs.
Estimations of layout timescales plus any subsequent re-estimations due to design changes.
Instigation of peer reviews for critical and major layout blocks.
Expert Layout IC Ltd Sept 11 – June 15
Expert Layout IC is my own consulting/contracting company
Key Achievements
Secured continuous contracts from leading technology companies including Intel, Xilinx and IC Mask Design.
Extensive critical layout design on 20nm node
Consulted on a range of critical layout challenges such as high speed matching, reduction in parasitics etc.
Developed and optimised a Hercules verification flow for a key customer. This role also included dynamic power
integrity analysis using Apache RedHawk
Spinning of various blocks using IC Compiler
Silansys Technologies May 11 – Sept 11
Silansys was founded in January 2002 to deliver turnkey ASIC product and IC Design Services for complex Mixed-
Signal intensive products.
Principal Layout Engineer
Supervision and management of various complex layout projects ranging across a variety of technology nodes
including 40 nanometer and 28 nanometer
Continually updated layout methodologies across various layout fields including Matching, Parasitics, Noise
Isolation, Supply Considerations etc
Preparation and updating of training material
Provide on-site training
Key advisor on all technical problems within the company and on-site
Several customers site visits to UK per year
IC Mask Design Aug 07 – May 11
Founded in 2002, IC Mask Design is Ireland's first independently owned Integrated Circuit Physical Design
Company.
Senior Layout Engineer
Introduced key strategies for optimal RF/Baseband layout
Successfully help train 600+ engineers worldwide
Developed and maintained key layout training material for the company
Trained all staff with respects to RF/Analog layout
Ensured all layouts reach and maintain a standard of excellence
Worked and engaged with customers across the world which also included working on customer sites for extended
periods of time
Day to day dealing with senior management, contractors, customers and suppliers
Frontier Silicon May 05 – Mar 07
Frontier Silicon is the world's leading supplier of innovative semiconductor, module and software solutions for
digital radio and connected audio systems.

3. Project Layout Engineer
Ported .18 micron layout designs down to .13 micron
Meet key layout challenges at the .13 micron process
Layout of a variety of baseband blocks including Bandgaps, Biasing circuitry, Voltage Regulators etc.
Key Achievements
Beng (HONS) Electronic Engineering which was completed on a three year part-time basis.
Parthus Ceva Mary 00 – May 05
Ceva is the leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores for the handset,
portable and consumer electronics markets.
Layout Engineer
Layout of varying structures on a .18 micron process
Spinning of digital blocks from RTL to GDSII
Qualifications
Leaving Certificate Salesian College, Laois 1991
Cert in Computers and Electronics Institute of Technology, Carlow
1999
Diploma in Computers and Electronics Institute of Technology, Carlow 2000
Bachelor Degree (Honours) in Electronic Engineering Institute of Technology, Tallaght 2006
Interests
Family time, Home music recording, Fitness, Electronics
Excellent references can be supplied on request
Adrian O'Shaughnessy