1. SfW Method: Delay Test Generation for Simple
Chain Wrapper Architecture
Marcel Baláž
Institute of Informatics
Slovak Academy of Sciences
845 07 Bratislava, Slovakia
E-mail: marcel.balaz@savba.sk
Abstract—The aim of the presented work is to improve the II. S CAN - BASED D ELAY T EST
quality of testing of SoC digital cores surrounded with test
wrappers. The paper presents a new effective delay fault test A test for delay faults, unlike tests for most of other
generation method for the transition faults based on the skewed- faults, consists of vector-pairs. The first vector of a vector-
load test. The generated delay fault test can be applied to
a SoC core through a test wrapper architecture with only a pair ensures the initial state of a core and the second one sets
simple boundary scan chain. This eliminates the necessity to the propagation state of the core. The transition between the
use an enhanced boundary scan chain for the application of two states can result in a delay fault in the functional operation
the delay fault test. The effectiveness of the developed method mode. Therefore, the transition has to be excited at the rated-
for a transition delay test generation was verified on the set of speed clock in the test mode as well. The main challenges
combinational and sequential circuits. The experiments show a
significant reduction of test vector application time. in the scan-based delay fault testing constitute transportation
or generation of an exciting vector and its application at full
I. I NTRODUCTION circuit speed.
Embedded digital blocks and their interconnections have to Three basic approaches should be considered for a vector-
be verified by an at-speed testing to satisfy the quality and the pair test application through core’s internal scan chains: a
reliability of nowadays SoCs. Once a chip is fabricated, it must skewed-load test [4], a broadside test [5] and an enhanced
be tested for a pre-specified clock frequency and therefore, the scan test. The skewed-load and the broadside tests use scan
testing has to cover also speed related faults. chain composed of simple scan cells (one memory element
Many delay fault models and related test generation tech- per one cell — Figure 1a). The first vector of a vector-pair
niques have been defined and used in digital circuits [1]. The is shifted in as a standard test vector. The difference between
common feature of most of the delay fault models is that these two test approaches lies in the way how to produce the
the test is composed of vector-pairs v1, v2 , where v1 is second vector. The broadside test uses circuit’s response and
the initialization vector and v2 is the excitation vector for the skewed-load test uses one additional shift to produce the
delay fault detection. The basic delay fault models are: the desired excitation vector. On the other hand, the enhanced scan
transition fault-, the gate delay fault-, and the path delay fault test uses enhanced scan cells (two memory elements per one
model. The transition and the path delay fault models are the cell — Figure 1b). The test architecture is much larger in
most frequently applied ones to combinational and scan-based comparison with simple scan chains but its advantage is in
sequential circuits. Several new models [2], [3] have been the capability of arbitrary vector-pairs application.
developed to use or combine some of the positive features The adaptation of existing scan methods to core-based SoCs
of the basic models. is an open issue, in particular in terms of test development for
The scan chain design is the most frequently used method core providers and test access mechanism (TAM) development
to increase testability of deeply embedded cores in SoC. for system integration. Although IEEE Std. 1500-2005 [6]
However, using the scan-based test architectures in vector-pair and recent research advances support structural scan tests,
testing is not a trivial problem. Test generation algorithms the most achievements are based on one-vector tests. Several
for combinational and scan-based synchronous circuits are approaches deal with vector-pair application for test wrapper
well known while test application techniques through test structures differently. The oscillation test method [7] requires
wrappers are still under development. This paper presents special address registers in each scan cell. Other test methods
a new developed method — called SfW (skewed-load for use principles of one of the three basic test approaches for
wrapper). The SfW method generates a test for the transition internal scan chains. The approach in [8] is based on the broad-
fault model applicable through a simple boundary scan chain. side test and requires only simple scan cells (with one memory
The paper is organized as follows. Delay test issues for scan- cell). The broadside effect is not achieved inside one core
based architectures are described in Section II. The proposed separately but it is obtained among several cores. The necessity
SfW method is described in Section III, and experimental of other cores assistance during a test restricts widespread
results are presented in Section IV. usage of this approach. The most common approach for
978-1-4244-8971-8/10$26.00 c 2010 IEEE

2. Strategy 2. The vector-pairs covering the transition faults
create one sequence of binary values in which each vector-pair
corresponds to Strategy 1 and also two consecutive vector-
pairs are generated by one or more bit shifts.
Example 1. Let delay fault test for a core with three in-
puts consist of following vector-pairs: 110, 100 , 001, 010 ,
101, 011 . Then the test sequence according to Strategy 1
and 2 is 11001011. The application of the test sequence is
illustrated in Figure 2. The simple boundary scan chain is
created with WC_SD1_CII scan cells (Figure 1a) which are
compliant with IEEE Std. 1500-2005 [6]. Every step of the test
application corresponds to one shift in scan chain. In the third
step the first initializing vector 110 is applied to the core.
In the fourth step the first excitation vector 100 is applied
Figure 1. a) An example of simple scan cell, and b) enhanced scan cell
and thus the first vector-pair as well. The eighth step is the
last step when the last excitation vector 011 is applied.
providing a delay test on embedded cores is the enhanced scan The transition fault test consists of vector-pairs where one
test (enhanced scan cells with two memory elements in each vector-pair covers one or more transition faults. The excitation
are used, e. g. [9]). No approach uses simple boundary scan vector of a vector-pair is actually a stuck-at test vector
chain without assistance of surrounding cores. The vector-pair according to basic principle of the delay fault test. For this
test approaches, which use simple scan chain are mostly based reason, the majority of existing automatic test generator for
on (pseudo)random vectors (the first presented skewed-load transition faults is based on test vectors for stuck-at-0 and
test used 100,000 random vector-pairs [10]). In comparison stuck-at-1 faults.
with the deterministic stuck-at test the application time of this The bit sequence formed by random or pseudo-random
type of delay test is multiple times longer. vectors corresponds to Strategy 1 and 2. This type of bit
The main idea was to develop a method to generate a sequence is very long (more than thousands of vector-pairs),
delay test which would, together with its ability to use test which leads to intolerable increase of test application time
wrapper with a simple boundary scan chain, have comparable for larger circuits. This solution also needs the use of a fault
application time with a deterministic stuck-at test. simulator to determine the fault coverage.
The proposed SfW method for generating a bit sequence
III. S F W M ETHOD is based on deterministic tests and thus it generates a de-
The new method was developed for a delay fault test terministic test sequence for transition faults. However, it is
generation aimed at embedded cores. The proposed method is not possible to use standard tests for stuck-at faults like it
designated for a transition faults test generation with primary is used in other test generators for delay faults [11], [12].
application through the simple boundary scan chain (one Existing stuck-at tests are optimized mostly for a minimal
memory element per one scan cell). The simple boundary scan number of test vectors. For that reason selection of appropriate
chain occupies smaller area than the enhanced boundary scan vectors for the transition fault test in accordance to Strategy 1
chain but for its simpler construction it is not suitable for and 2 is very limited due to shift dependency. Therefore, the
an ordinary delay fault test. Therefore, it was necessary to SfW method uses modified stuck-at test, which consists of
propose a method to generate tests for delay faults applicable sets of test vectors for every detectable stuck-at fault in the
through the simple boundary scan chain. The method is core. This approach increased the probability of delay fault
based on the skewed-load test (launch-on-shift test) for the test generation for test Strategy 1 and 2, and also the overall
internal scan chains and the basic principle is characterized coverage of delay faults.
by Strategy 1. Initialization and excitation vectors can be merged into a
one bit sequence if the corresponding bits are identical, or
Strategy 1. A vector-pair to detect transition faults is applied
at least one of them is undefined. This condition is known
through a simple boundary scan chain as a one bit sequence,
as vector consistency and the bit sequence is referred to as
where an excitation vector is created by one bit shift of an
m-vector.
initialization vector.
Definition 1. Let v1 denote the initialization vector and v2
The basic requirements of the proposed method for a
the excitation vector in the circuit with N inputs then m =
optimal test length of a generated test for transition faults
(m1 , m2 , . . . mN +1 ) with m1 = v11 , mN +1 = v2N is m-
were (1) a test application via a simple boundary scan chain
vector only if mi for i = 2, 3, . . . N is determined by one of
without the use of neighboring test cores (Strategy 1), and
the possibilities in Table I.
(2) the minimal test application time. The second strategy was
formulated to minimize the test application time. M-vector is the bit sequence N + 1 bits long, where

3. Figure 2. An example of the test application to test wrapper with the simple boundary scan chain
Table I
A LLOWED BIT COMBINATION FOR DEFINING M - VECTOR Each singular m-vector covers a transition fault as the only
v1i v2i−1 mi one; therefore it must certainly be included in the generated
0 0 0 test sequence. The application of a initialization vector and a
0 X 0
X 0 0
excitation vector consequently creates a partial sensitive path
1 1 1 in the core. The sensitive path is created between the primary
1 X 1
X 1 1
inputs and a wire where the transition fault is tested. M-vector
X X X may also cover other transition faults which occur on the
sensitive path.
Definition 3. Let ms ∈ S be the singular m-vector and mf ∈
excitation vector (v2) is generated by one shift operation of Mf be the m-vector covering the transition fault f , then mf
the initialization vector (v1). overlaps ms if (msi = 0 ∧ mf i = 1) ∨ (msi = 1 ∧ mf i = 0)
for i = 1, 2, . . . N , where N is number of bits of mf (and ms).
To find an appropriate initialization vector, the SfW method
uses a set of excitation vectors for the second type of transition If the set Mf contains only one m-vector, which can overlap
fault on the same wire. The set of excitation vectors does not one singular m-vector, this overlap is performed. If the set Mf
cover the whole set of initialization vectors for the second contains more vectors, which can overlap the same singular
transition fault on the same wire. Therefore, the proposed m-vector the selection of the best one is performed in several
method includes a simulator of initialization values. It per- steps. The number of replaced undefined bits in the singular m-
forms two basic operations: (1) In case no vector from the set vector is considered and also overlapping m-vectors for fault
is suitable for m-vector creation the simulator is used to find f are compared with overlapping m-vectors for other faults.
a suitable initialization vector. (2) If there is a vector from If the set Mf contains no m-vector, which overlaps any
the set, which is also an initialization vector for a opposite singular m-vector, it is necessary to choose the representing
transition fault, the simulator finds its minimal form (vector m-vector of the set Mf . The selection of the best m-vectors
bits, which initially provide test value propagation to outputs for transition faults without any overlap on singular m-vectors
are replaced by undefined values) and thus also provides a is made with the constraint to find the minimal number of
minimal form of m-vector. m-vectors, which would cover all remaining faults.
One of the method requirements is the shortest test applica- The SfW method generates a minimized set of m-vectors,
tion of the generated test sequence which is achieved only by which covers all diagnosable transition faults in the core
a short generated test sequence. The length of the sequence under test. The set can be formed into one of three test
is determined by two factors: (1) the number of m-vectors in types. Each type is applicable to various types of test wrapper
the sequence, and (2) the capability to cover more transition architectures.
faults by one m-vector.
IV. E XPERIMENTAL R ESULTS
The SfW method generates more m-vectors for each transi-
tion fault. Set of m-vectors for each transition fault is searched The SfW method for delay test generation was validated
to find the minimal number of m-vectors, which would cover with numerous experiments. The test pattern generator Ata-
all faults in the core. Searching the set of m-vectors starts with lanta [13] was used to generate excitation vectors. This stuck-
singular m-vectors. at fault generator provides generation of multiple test vectors
for every fault. This feature was mandatory, since the proposed
Definition 2. M-vector is known as singular m-vector only if method is based on it. Experiments were performed using
none of other m-vectors can cover the transition fault. combinational benchmark circuits ISCAS’85 and sequential

4. Table II
E XPERIMENTAL RESULTS OF S F W METHOD AND P RIORITY- BASED E XTENSION METHOD [11]
circuit number of number of test sequence test sequence test coverage test coverage
m-vectors [SfW] vector-pairs [11] length (bit) [SfW] length (bit) [11] [SfW] [11]
c880 203 257 7 523 30 840 85,0% 100,0%
c1355 545 461 17 565 37 802 59,8% 99,8%
c1908 739 440 16 596 29 040 82,1% 99,7%
c3540 801 755 12 905 75 500 73,6% 96,3%
c5315 1 690 421 96 327 149 876 87,3% 99,5%
s344 51 96 614 4 608 92,2% 100,0%
s382 46 120 473 5 760 86,1% 100,0%
s526 85 209 914 10 032 85,6% 99,9%
s832 119 450 854 20 700 71,3% 99,2%
s1196 238 532 2 443 34 048 80,3% 100,0%
s1423 220 382 13 462 69 524 90,2% 99,1%
s5378 430 1 069 40 871 457 532 82,0% 99,8%
benchmark circuits ISCAS’89 with internal scan chains. Two method based on the skewed-load test principle generates a
parameters were observed: the transition fault coverage and delay fault test which is suitable for test wrappers with the
the test application time. simple boundary scan chain; this eliminates the necessity to
The SfW method was developed with the goal to reduce use the extended boundary scan chain for the application of
the application time for delay test through a core wrapper. a delay fault test. The test generated by the SfW method is
The test application time depends on the length of the test multiple times shorter in comparison with the standard delay
sequence. As mentioned earlier, the application of the standard test application. The SfW method offers a good alternative
deterministic delay test in the embedded cores is provided to other approaches which use the enhanced scan cells or
through the core wrapper with extended scan cells. For this assistance of surrounding cores.
application type, the test sequence is given by equation 2×D×
ACKNOWLEDGMENT
N where D represents the number of vector-pairs and N is the
number of core inputs (the length of input scan chain). Table II This work has been supported by Slovak national project
reports the experimental results for the proposed SfW method VEGA 2/0135/08.
and Priority-based Extension method [11]. For the majority R EFERENCES
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