1. 2015 International Conference on Computer Communication and Informatics (ICCCI-2015), Jan.08-10, 2015, Coimbatore, INDIA
Study and Implementation of Multi-VDD
Power Reduction Technique
Mohammed Musab Siva Yellampalli
PG student Professor
VTU Ext. Centre, UTL technologies Ltd. VTU Ext. Centre, UTL technologies Ltd.
Bangalore, India Bangalore, India
musab1024@gmail.com siva.yellampalli@utltraining.com
Abstract—Advances in VLSI technology has led to
design of complex circuits, these complex circuits
consumes high power. Several traditional methods
such as power gating, clock gating, multi VT, variable
VT etc., exists to reduce power dissipation. This
paper studies Multi-VDD power reduction technique
and implements the same for ISCAS89 S38417
benchmark circuit. From the experimental results,
Multi VDD technique reduces the power by 85.83%
when compared with single VDD.
Index Terms— ASIC design flow, dynamic
power, static power, register transfer logic
(RTL), common power format (CPF), synopsis
design constraint file (SDC), library, level
shifters, power domains (PD), tool command
language (TCL), area, timing.
I. INTRODUCTION
T
he complexity of today’s integrated circuit had
reached billions of transistors[1] [2] which
increases the functionality but increases power
dissipation. The major sources of power dissipation
in CMOS circuits are Static and dynamic power [3]
[4] components, which are discussed in section I.A.
Several power reduction techniques [3] [5] are
available to reduce static and dynamic power. The
Multi-VDD technique is most widely used
technique in complex circuits because of its
effective power reduction.
A. Sources of Power Dissipation
The major sources of power dissipation [3] [4] are
1. Dynamic power, 2. Static power, 3. Glitch
power.
I. Dynamic power: Dynamic power is the
sum of two factors: switching power and
short-circuit power. Switching power is
dissipated when charging or discharging
node capacitances as shown in figure 1.
Short-circuit power is the power
dissipated because of the short circuit
connection between the supply voltage
and the ground as shown in figure 2 which
occurs when input is at voltage level
VDD/2. The dynamic power can be
lowered by reducing clock frequency
which affects performance, but the
dynamic power can be reduced by
reducing the switching activity by
eliminating unwanted transitions. The
switching power is given by the equation
1.1,
Figure 1.1 Dynamic Power
Pdyn = α C Vdd2
f …… 1.1
Where, α - switching activity
C - effective capacitance
f - switching frequency
Vdd- supply voltage
II. Static power: In deep submicron devices
the leakage current is increasing with
technology scaling and sub-threshold
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2. 2015 International Conference on Computer Communication and Informatics (ICCCI-2015), Jan.08-10, 2015, Coimbatore, INDIA
leakage is the major source of leakage
current which flows when the transistor is
off and it is given by the equation 1.2,
Pstat = Ileakage Vdd …….. 1.2
III. Glitch power: Glitches[6] are unwanted
transitions due to the delay unbalancing
and it is given by the equation 1.3,
Pglitch= α C Vdd Vmin …… 1.3
IV. Short circuit power
When input is at VDD/2 both PMOS and NMOS
are conducting for a short duration of time and
there is a current flowing between supply power
and ground as shown in the figure 1.2 and the
power dissipated due to short circuit current is
defined by equation 1.4.
Figure 1.2 Short circuit Power
Pavg = β/12 (Vdd-2Vt)3
/T +IƮ leakage Vdd …… 1.4
Where, Isc -short circuit current
Vdd- supply voltage
Ileakage- leakage current
fclk- clock frequency
- delayƮ
T- time
Pavg= Pswitching+ Pshort-circuit + Pleakage ……1.5
Total power is defined as the sum of both dynamic
power and the static power which is given in
equation 1.5, the total power is a function of
switching activity, effective capacitance, voltage,
slew, leakage power and the transistor structure.
This paper is organized as follows; section II
explains multi VDD power reduction technique.
Section III discusses about CPF based ASIC design
flow followed by experimental results in Section
IV, Section V concludes the paper.
II. Multi-VDD
Multi VDD technique [5][7] is widely used
technique for reducing both the dynamic and static
power. Here the given circuit is divided into
voltage islands, the block which operates at the
high frequency is supplied with high VDD and the
block operates at low frequency is supplied with
low VDD.
In Multi-VDD technique, the level shifters are
used for converting the voltage levels from high to
low and vice versa. The blocks under the different
VDDs are called as power domains which is
discussed in section IIA. The figure 2.1 shows the
use of multi-VDD architecture in a SoC where the
CPU, Cache works at high VDD and the interface
Figure 2.1 Multi-VDD architecture
Works at low VDD. As the signals are flowing
across different voltage domains level shifters must
be employed to shift the voltage levels.
A. Power domain
Power domain[5][7] represents a group of blocks
or gates with one common power supply or a group
of instance, pins and ports that can share the same
power distribution network. Isolation cells are
required when transferring data from one block to
another block if power to one of the blocks can
potentially be shut down. A power domain may be
shut down to save power. In such cases, isolation
cells are needed on signals that cross boundaries
between the potentially shut down domain and the
domain to ensure that there is no misinterpretation
of the signal level. The isolation cell ensures that a
valid signal is present at the input of the receiving
block.
B. Level Shifter
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3. 2015 International Conference on Computer Communication and Informatics (ICCCI-2015), Jan.08-10, 2015, Coimbatore, INDIA
Level shifters [5] [7] are logic elements which is
used to convert one voltage to the other. The level
shifters have to be placed properly to ensure proper
power domain crossing. The level shifters can be
placed physically in source or destination voltage
domain. The use of level shifter increase the area
but when the power reduction percentage is good
then the area overhead because of level shifters can
be justified.
The use of level shifters can be understood with
the figure 3 where low to high level shifters are
used which is used to convert the voltage from
0.81V to 0.9V. The level shifters are special type of
cell which may receive different different supply
voltage input signal and generates the other supply
voltage output signal.
Figure 3. Level shifters (LS) used when crossing
power domain
A level shifter can reside logically and physically
in either of the power domains. The use of the level
shifters increases the critical path delay between
the voltage domains because of the extra delay
incurred by the level shifter cell.
The level shifter is of two types
1. High to Low voltage level shifter (H->L)
2. Low to High voltage level shifter (L->H)
Figure 4. ASIC design flow
A high-to-low level shifter is used for a signal
going from a higher voltage domain to a lower
voltage domain. A low-to-high level shifter is used
when the source voltage domain is lower than the
target power domain. The power caused by the
level shifter can also be justified when good
percentage of power reduction is achieved.
III. CPF BASED ASIC DESIGN FLOW
CPF defines the power intent, constraints and
library details of the design; it can effectively
capture the power intent for the full chip. Figure 4
shows the ASIC design flow with the CPF. This
shows the ASIC design flow process which starts
from the customer requirements till tape-out.
Design entry is made through RTL coding; the
functional verification verifies the functionality of
the design. Gate level netlist is obtained by
synthesis with respect the technology library and
timing constraints (SDC) and CPF, Netlist defines
the hardware generation for an RTL. CPF explains
the power details of the different modules. The
same CPF can be used until the chip tape out.
IV. EXPERIMENTAL RESULTS
A. Experimental setup
To implement the Multi-VDD technique, a top
level module is created by replicating the
ISCAS’89 S38417 benchmark circuit twice as
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4. 2015 International Conference on Computer Communication and Informatics (ICCCI-2015), Jan.08-10, 2015, Coimbatore, INDIA
shown in figure 5. One instance of S38417 is
applied with High VDD and the other with Low
VDD. 17 connections are created between two
instances which require 17 low to high level
shifters and 30 high to low level shifters are
required, as the top level module belongs to low
power domain. The tool used for synthesis and
calculating power, area and timing is Cadence
RTL Compiler. The design is synthesized using
TSMC 40nm 0.81V and 0.99V library and the
clock is constrained to 1GHz.
Figure 5. Top module of the benchmark ‘S38417’
B. Analysis
The table 1 shows the analysis of multi VDD
technique for benchmark ‘S38417’ here the area
and power is reduced by 57.44%, 85.83% with
respect to only high VDD (1V). 47 level shifters
are inserted which increases the area overhead by
0.82% and power overhead by 4.98%, the tradeoff
is good because 85.83% overall power reduction is
achieved.
Table 1. Experimental results.
V. Conclusion
From the study and analysis, the Multi-Vdd
technique is very efficient in reducing both the
static and dynamic power. But the insertion of the
level shifters increases the critical path delay
between the power domains which may affect the
frequency. From the experiment conducted it is
found that both the dynamic power and the static
power has been reduced by 85.83%, area is reduced
by 57.74% after applying multi-VDD technique.
VI. References
[1]. “International Technology Road map for
Semiconductors, process integration,
devices and structures”, 2013 Edition.
[2]. Gordan E Moore, “cramming more
components onto integrated circuits”,
Electronics, Volume 38, number 8, April
19, 1965.
[3]. Kaushik Roy, Sharat Prasad, “Low power
CMOS-VLSI circuit design”, ISBN 0-
471-11488-X, John Wiley publishers
2000.
[4]. Gary K Yeap, “Practical Low Power
Digital VLSI Design”, ISBN 0792380096,
Springer US, 1997.
[5]. Michael Keating, David Flynn, Robert
Aitken, Alan Gibbons, Kaijian Shi, “Low
power methodology manual for SoC
design”, ISBN 978-0-387-71818-7,
Springer publishers, New York, USA,
2007.
[6]. Massoud Pedram,“Power minimization of
IC Design”, ACM transactions On Design
automation of electronic systems, vol
1.,pp 3-56, January 1996
[7]. J. Bhasker -Rakesh Chadha, “An ASIC
low power Primer”, ISBN 978-1-4614-
4270-7, Springer publishers, New York,
USA, 2013. `
VII. Author Biography
Mohammed Musab is currently
pursuing his M.Tech in VLSI
design and embedded systems
from VTU Extension Centre, UTL
technologies limited, Bengaluru, he
obtained his bachelor’s degree in
telecommunication engineering from Atria institute
of technology (AIT), Bengaluru. And also obtained
his diploma degree in electronics and
communication engineering from RNS polytechnic,
Murdeshwar. His interest includes System on Chip
and Low power VLSI design.
ACKNOWLEDGEMENT
The authors would like to thank Dr. V
Venkateswarlu, HOD and principal, VTU Ext.
Centre, UTL Technologies Limited. For their
inspirational guidance and support. And cannot
forget the constant encouragement and help
provided by internal guide Mr. G. Harish, Assistant
Professor, VTU Extension Centre, UTL
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5. 2015 International Conference on Computer Communication and Informatics (ICCCI-2015), Jan.08-10, 2015, Coimbatore, INDIA
Technologies Limited, who considered me like a
friend and made me feel at ease in times of
difficulty during my project work. I express my
sincere gratitude to him.
978-1-4799-6805-3/15/$31.00 ©2015 IEEE

6. 2015 International Conference on Computer Communication and Informatics (ICCCI-2015), Jan.08-10, 2015, Coimbatore, INDIA
Technologies Limited, who considered me like a
friend and made me feel at ease in times of
difficulty during my project work. I express my
sincere gratitude to him.
978-1-4799-6805-3/15/$31.00 ©2015 IEEE