The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed on Cadence Design Suit 6.1.5 using Virtuoso and ADE environment at GPDK 45nm technology with a unvaried width and length of PMOS and NMOS devices. The paper gives a compression of various design of 1 bit full adder with respect to number of transistors/ gate count, Delay, Power and Power Delay Product.

1. Design of Fast and Efficient 1-bit Full Adder and
its Performance Analysis
Kunjan D. Shinde1
M.Tech in Digital Electronics, Dept. of E&CE
S.D.M. College of Engineering & Technology
Dharwad, Karnataka, India,
Kunjan18m@gmail.com
Jayashree C. Nidagundi2
Assistant Professor, Dept. of E&CE
S.D.M. College of Engineering & Technology
Dharwad, Karnataka, India,
jayaprajwal@rediffmail.com
Abstract—The most fundamental computational process
encountered in digital system is binary addition, to accomplish
this process binary adders are used, half adder and full adders
are most often used to carry out binary addition. This paper
presents a comparative analysis of design of 1bit full adder using
conventional techniques and new techniques, the design and
simulation of 1-bit full adder is performed on Cadence Design
Suit 6.1.5 using Virtuoso and ADE environment at GPDK 45nm
technology with a unvaried width and length of PMOS and
NMOS devices. The paper gives a compression of various design
of 1 bit full adder with respect to number of transistors/ gate
count, Delay, Power and Power Delay Product.
Index Terms— Full Adder, CMOS, TG, GDI, GDI-PTL, No. of
Transistors/Gate count, Delay, Power and PDP.
I. INTRODUCTION
Adders are fundamental and most essential blocks in
every digital system. Design of fast, effective and reliable,
adder‟s plays an important role, as the technology is scaled
down the complexity in the design increases with some
reduction in the performance of the adders. In this paper a
different set of binary adders are designed using different
logics like Complementary Metal Oxide Semiconductor
(CMOS), Gate Diffusion Input (GDI), Transmission Gate (TG)
and few new optimized logics.
Adders can be implemented in different ways using
different technologies at different levels of architectures.
Design of high speed and reliable adders is the prime objective
and requirement for digital applications as the technology is
scaled down. Binary addition is a basic operation in most
digital circuits. There are a variety of adders used for this
purpose, but each of it has a certain criteria‟s like design style,
power, area, and speed. Adder is selected depending on where
the adder is to be used and criteria‟s selected for a given
application.
A simple adder performs the addition of given two
numbers and the result is sum of those two numbers. When
two numbers are added, in general, it is necessary to consider
at each bit position an augend bit A, an addent bit B, and a
carry-in Cin. The result of the addition at each bit position is a
sum bit SUM and a carry-out bit Cout. Table I summarizes the
addition process for each bit position, i.e. the value of SUM
and Cout for all the possible assignment of values to A, B and
Cin.[1]
Table I: Truth table for a binary full adder
Although table was constructed as an addition table, it
can also be regarded as the truth table for a logic network that
performs addition at a single bit position. Such a network is
referred to as a binary full adder.[1]
The rest of the sections in this paper are arranged as,
Section II gives the literature survey of various 1-bit full adder
designs styles. Section III gives the methodology and working
for the design of 1-bit full adders using different design styles
like CMOS, TG, GDI and GDI-PTL logic. Section VI gives
the simulation results and performance analysis of the various
design styles used for the design of 1-bit adder. In the last
Section gives conclusion and references.
II. LITERATURE REVIEW
The following are the few references that we have gone
through for the design of 1-bit full adder with unvaried width
and length of PMOS and NMOS devices. From [1] the design
and design equations of 1-bit full adder were used for the
design of full adder using CMOS, GDI and TG logics. In [2]
the design of 1 bit full adder using different techniques like
CMOS, TG, GDI, and optimized logics were used but the
width and length of MOS devices used were varied to obtain
proper results. In [3] the effective design of full adders is
A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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2. discussed, a hybrid design for high speed adder was the target
and comparative analysis is coated. In [4] design of full adders
for high performance full adder cell was coated and analysis
was performed. In [5] brief about the design and working of
adder is given.
III. DESIGN OF 1-BIT FULL ADDER
A full adder is used to performthe addition on two single
bit data and one carry in data producing the results as Sumand
Carryout signals, hence it has three inputs A, B, Cin and has
two outputs Sum, Carryout. The expression for the 1-bit full
adder is given as
Sum= A ^ B ^Cin (1)
Carry out = (A & B) + (B & Cin) + (Cin & A) (2)
( ^ - XOR operation, & - AND operation, + -OR operation )
Figure 1 and figure 2 gives the Block Diagram and
Schematic diagram of 1-bit full adder and the truth table of the
1-bit full adder is given in Table 1.
Fig 1: Block Diagram of 1-bit Full Adder
Figure 2: Schematic diagram of 1-bit Full Adder[1]
From the schematic of full adder shown in figure 2, it is
clear that the sum output is generated in two level gate delay of
XOR gate and carryout output is generated in three level gate
delays of AND-OR gate logic, the delay of each gate is
different with different logic used to design the given logic.
The following are the different design style used to design
1-bit full adder and simulation is performed on Cadence
Design Suite 6.1.5 using Virtuoso & ADE at 45 nanometer
technology. In the process of design and implementation of 1-
bit full adder, we are restricting our design to have an unvaried
width and length parameter of both NMOS & PMOS devices
and hence the obtained simulation results and their comparative
analysis are coated in this paper.
A.CMOS Design style
Figure 3 shows the schematic of 1-bit Full Adder
implemented using the equations (1) and (2), here the design
of each basic (gate) logic block is done using CMOS logic
with PMOS and NMOS logic networks, figure 5 shows the
simulation result of 1-bit full adder using CMOS logic, from
the figure 4 it is clear that the output level of both sum and
carryout is not degraded but this approach to design 1-bit full
adder using CMOS logic consumes more number of
transistors which is coated in the table 2.
Figure 3: Schematic of Full Adder using CMOS logic
Figure 4: Simulation of Full Adder using CMOS logic
B. GDI Design style
Figure 5 shows the schematic of 1-bit Full Adder
implemented using the equations (1) and (2), here the design
of each basic (gate) logic block is done using GDI logic, the
function of GDI block is shown in figure 14 and its behavior
in table 3, figure 6 shows the simulation result of full adder
using GDI logic, from the simulation result it is clear that the
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3. output level of both sumand carryout is degraded, considering
the sum and carryout output waveform we can see the output
voltage is same when the inputs are a=1,b=1,c=0 and
a=0,b=1,c=0 and a=0,b=1,c=1 , the degradation in output
signal is acceptable if signal level was not conflicting with the
output states i.e. the voltage level is same when output should
be logic 0 and logic 1, hence such conflict results to
undesirable results which is drawback of this approach with
the earlier assumptions, where this approach consumes less
number of transistors compared to CMOS logic but the results
are unsatisfactory.
Figure 5: Schematic of Full Adder using GDI Technique
Figure 6: Simulation result of Full Adder using GDI Technique
C. TG Design Style
Figure 7 shows the schematic 1-bit Full Adder
implemented using the equations (1) and (2), here the design
of each basic logic (gate design) block is done using TGlogic,
the behavior of TG logic is shown in figure 13 and its truth
table in table 2, figure 8 shows the simulation result of full
adder using TG logic, from the figure 8 it is clear that the
output level of both sumand carryout is not degraded, and the
design uses less number of transistors compared to CMOS
logic and more than GDI logic.
Figure 7: Schematic of Full Adder using TG Logic
Figure 8: Simulation Result of Full Adder using TG Logic
D. Full Adder using GDI-PTL 9TA logic [2]
Figure 9 shows the schematic 9T Full Adder using PTL
and GDI logic, figure 10 shows the simulation result for the
same, from the figure 10 it is clear that the output level of both
sum and carryout is degraded, considering the sum and
carryout output waveform we can see the output voltage is
same when the inputs are a=1,b=1,c=0 and a=1,b=0,c=1 and
a=0,b=1,c=0 and a=0,b=1,c=1 , the degradation in output
signal is acceptable if signal level was not conflicting with the
output states i.e. the voltage level is same when output should
be logic 0 and logic 1, hence such conflict results to
undesirable results which is drawback of this approach with
the earlier assumptions of using width parameter to be
constant, this approach consumes less number of transistors
Conflicting results
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4. compared to CMOS, TG logic but the results are
unsatisfactory.
Figure 9: Schematic of 9 Transistor full adder[2]
Figure 10: Simulation Results of 9 Transistor full adder
E. Full Adder using GDI-PTL logic[3]
Figure 11 shows the schematic 1-bit Full Adder design
using GDI-PTL logic, figure 12 shows the simulation result of
full adder using GDI-PTL logic, from the figure 12 it is clear
that the output level of both sumand carryout is degraded, but
gives the satisfactory results and no voltage levels conflicts in
any of the states for both Sum and Carryout outputs and In this
logic the Sum output is designed using Pass PTL logic and the
Carryout output is designed using GDI logic. Initially the
X= A^B function is been generated using two PMOS and two
NMOS transistors and then using Cin, Sum = Cin^ X is
obtained. The total number of transistor used is 8 to obtain the
Sum output. The Carryout output is designed using GDI logic
as shown.
Figure 11: Schematic of GDI-PTL full adder[3]
Figure12: Simulation Result of GDI-PTL full adder
IV RESULTS AND DISCUSSIONS.
The table II and table III gives comparative analysis of
all the above adder design techniques used with the
performance metrics as Delay, Power and Number of
transistors/ gate count and power delay product (PDP).
From the simulation results and the comparative analysis
coated below in the table II and table III, it is clear that the
Power Delay Product of the 1-bit pull adder design using 10T
GDI-PTL logic gives better results as well as consumes less
power overall and less area which suits well for low power,
area effective, high speed embedded applications.
Degraded and satisfactory resultConflicting results
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5. The measure of performance is done on Cadence Design
Suite 6.1.5 using Virtuoso and ADE environment at 45
nanometer technology with unvaried width and length of all the
PMOS and NMOS devices.
Table II: Comparativeanalysis of1-bit full adder withperformance measure as
Gate Count, Delay and Power.
Table III: Comparative analysis of 1-bit full adder with performance measure
as Power Delay Product
CONCLUSION
From the above simulation results and performance
analysis, it is clear that the CMOS and TG logic gives
undistorted output response with delay of 3 gate level
(maximum) and consumes a large amount of transistors in its
design, where as in GDI technique and 9TA design, the design
consumes less number of transistors but doesn‟t provide a
satisfactory results, and in the GDI-PTL optimized logics
provides a better results with output voltage levels degraded
and no conflicting with same output voltage for both logic „0‟
and logic „1‟ and consumes a less number of transistors,such a
design is well suited for the application with unvaried Width
and Length of transistors in its design.
ACKNOWLEDGMENT
The Authors would like to thank the management and the
Principal of SDMCET Dharwad all the support and we would
like to thank staff and lab in charge and the Dept. of
Electronics and Communication Engineering, SDMCET,
Dharwad for all the resources & support provided, a special
thanks Prof. Sunil S. Mathad, Mrs. Pavithra S. K. R. and Mr.
Sanjeev Wadiker for the support and help provided.
REFERENCES
[1] DonaldD. Givone, “Digital Principles andDesign”,Tata McGraw-Hill
Edition 2002, chapter 5 – pp 231- 233.
[2] Saradindu Panda, A.Banerjee,B.Maji, Dr.A.K. Mukhopadhyay “ Power
and Delay Comparison in between Different types of Full Adder
Circuits” International Journal of Advanced Research in Electrical,
Electronics andInstrumentationEngineering Vol. 1, Issue 3, September
2012, ISSN 2278 – 8875
[3] Rajkumar Sarma andVeerati Raju“Design And Performance Analysis
Of Hybrid Adders For High Speed Arithmetic Circuit” International
Journal of VLSI design & Communication Systems (VLSICS) Vol.3,
No.3, June 2012.
[4] Tripti Sharma,K.G.Sharma, Prof.B.P.Singh “High Performance Full
Adder Cell: A Comparative Analysis” Proceedings of the 2010 IEEE
student‟s technology symposium 3-4 April 2010 IIT Kharagpur.
[5] http://en.wikipedia.org/wiki/Adder_(electronics)
Performance
Measures/
Design Style
No. of
Transistor/
Gate Count
Delay
In S
Total
Power
In W
SUM CARRY
OUT
CMOS 58 25.67E-12 38.66E-12 11.08E-6
TG 46 10.13E-12 24.73E-12 14.66E-6
GDI 18 6.219E-09 503.8E-15 04.42E-6
9TA 10 3.618E-12 72.17E-12 06.16E-6
GDI-PTL 10 6.477E-12 7.573E-12 08.10E-6
Dynamic
Power
In W
Delay
In S
PDP
In Watt-sec
SUM CARRY
OUT
SUM CARRY
OUT
10.79E-06 25.67E-12 38.66E-12 2.769E-16 4.171E-16
14.50E-06 10.13E-12 24.73E-12 1.468E-16 35.90E-16
04.39E-06 6.219E-09 503.8E-15 273.2E-16 2.213E-18
06.14E-06 3.618E-12 72.17E-12 0.222E-16 4.433E-16
08.10E-06 6.477E-12 7.573E-12 0.524E-16 0.613E-16
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978-1-4799-4190-2/14/$31.00 ©2014 IEEE