May 1, 2013Methodology forMixed ModeDesign & Verification of Complex SoCsMay 1, 2013 Jan Pleskac, S3 Group
May 1, 2013AgendaIntroductionMixed Signal SoC examplesAnalog vs. digital design flowLessons from Mixed Mode Design & Verif...
May 1, 2013Founded in 1986250+ EmployeesOver 1000 IC tapeouts deliveredComplementary Services and ProductPortfolioAdvanced...
May 1, 2013Global Locations OFFICESSALES & SUPPORTSan Jose, US Kfar Saba, IsraelDublin / Cork, IrelandLisbon, PortugalWroc...
May 1, 2013Mixed Signal SoC examplesRF analog Front End with digital signal pre-processingTX – DAC, Filter, Mixer, VGA, PA...
May 1, 2013Mixed Mode Design & VerificationArchitectureDecide on TOP implementation flow – “analog on top” vs. “digital on...
May 1, 2013Analog vs. Digital CharacteristicsAnalogBottom-Up– focus on block level design (schematic,models, performance)–...
May 1, 2013Lesson #1Analog and Digital team communicationProblem: Two different worlds, different mindset.Solution:Clear a...
May 1, 2013Lesson #2Respect the difference in flow/domainProblem: Flows are disconnected and way different.Solution:Use ap...
May 1, 2013Lesson #3Implementation phasingProblem: It is not possible to finish digital controller until analog block is d...
May 1, 2013Lesson #4Reuse of digital verification environmentProblem: Digital standalone verification covers majority of a...
May 1, 2013ConclusionMixed mode design & verification is iterative processTop – Down approach is must for parallel executi...
May 1, 2013Thank You!jan.pleskac@s3group.com
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TRACK C: Methodology for Mixed Mode Design & Verification of Complex SoCs/ Jan Pleskac

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TRACK C: Methodology for Mixed Mode Design & Verification of Complex SoCs/ Jan Pleskac

  1. 1. May 1, 2013Methodology forMixed ModeDesign & Verification of Complex SoCsMay 1, 2013 Jan Pleskac, S3 Group
  2. 2. May 1, 2013AgendaIntroductionMixed Signal SoC examplesAnalog vs. digital design flowLessons from Mixed Mode Design & Verification projectsConclusion
  3. 3. May 1, 2013Founded in 1986250+ EmployeesOver 1000 IC tapeouts deliveredComplementary Services and ProductPortfolioAdvanced, independent MSIPcompanyHighlightsOver 100 Million mobile phonesshipped with ICs designed by S3GroupSatellite transceiver redesigndelivered an 85% BOM reductionComplete Turnkey service, deliveringspec to packaged-tested partsAbout S3 Group
  4. 4. May 1, 2013Global Locations OFFICESSALES & SUPPORTSan Jose, US Kfar Saba, IsraelDublin / Cork, IrelandLisbon, PortugalWroclaw, PolandPrague, Czech RepublicSingaporeNew Jersey, US Beijing, ChinaHong KongEindhoven, The NetherlandsShanghaiChicago, US
  5. 5. May 1, 2013Mixed Signal SoC examplesRF analog Front End with digital signal pre-processingTX – DAC, Filter, Mixer, VGA, PA DriverRX – LNA, Mixer, Programmable Filter, ADCPLL, LDOs, Auxiliary ADCs, DACs, Temp sensorRX/TX data interface, IC programming interface, GPIOsDigital filtering and DSP, Power managementAnalog blocks calibration, testingPower management ICPOR, Reset/Clock distribution, ADCs, Temperature monitors/alarms, Programming interfaceSmart SensorsUltra low power, Closed loop compensation/linearization control, Signal processing, uController
  6. 6. May 1, 2013Mixed Mode Design & VerificationArchitectureDecide on TOP implementation flow – “analog on top” vs. “digital on top”Early IC Floor Plan – package constrains (analog sensitive pads)Design partitioning– signal flow, operation modes, mission critical, power domains– leveraging existing design data (internally developed building blocks)– lP blocks selectionIdentify Analog/Digital critical parts– mixed mode co-simulation candidate – calibration, control loops, power sequencingTop-level Functional Verification – co-simulation– Integration checks on functionally verified analog and digital blocks– Functional Requirements sign-off
  7. 7. May 1, 2013Analog vs. Digital CharacteristicsAnalogBottom-Up– focus on block level design (schematic,models, performance)– GUI based tools, visual inspection– Sub-systems & TOP integration– Block/Sub-Systems Model creation for topverification (functional models)– Power Estimations accurate early– Hand LayoutDigitalTop-Down– block level design and early integration(reuse of verification environment)– Text based, regressions, self-checking– methodology and standards (strong reuse ofdesign patterns or blocks, coding style)– Active specification – (IP-XACT registersdescription)– Accurate power estimations requiressimulation (post layout + extractions)– Tool based automatic layout
  8. 8. May 1, 2013Lesson #1Analog and Digital team communicationProblem: Two different worlds, different mindset.Solution:Clear and consistent naming on IC architecture and interface signals from Day #1.High level functional/architecture specification.Focus on USE-CASEs – common language.Co-Working rather then forcing someone to work in unfriendly environment.
  9. 9. May 1, 2013Lesson #2Respect the difference in flow/domainProblem: Flows are disconnected and way different.Solution:Use appropriate tool or view for given task ( e.g. Modeling trade-off accuracy vs. speed).Implement small digital macros for non-critical analog routing (e.g. configuration bus, decoders).Uniform data formats for use in Analog/Digital standalone env., especially when 3rd party tool isinvolved (e.g. Matlab data generators, files).
  10. 10. May 1, 2013Lesson #3Implementation phasingProblem: It is not possible to finish digital controller until analog block is designed, but you haveto start someday… Late changes happen. Tight layout or performance issues may requirefunctional modifications (Power architecture, Filtering changes).Solution:Start to implement core functionality and structural parts (state machine, interval timers).Use simplified functional models of analog block, or create behavioral representation of digitalblock rather then creating RTL in early stages.Run several implementation iterations, each step needs consistent views. Final implementation“just configures soft core RTL”.This require multiple runs of full digital flow RTL2-GDS2, important for change impact analysis(area, power, routing).Keep working top-level schematic – co-simulation on netlist with “dummy” views.
  11. 11. May 1, 2013Lesson #4Reuse of digital verification environmentProblem: Digital standalone verification covers majority of analog scenarios, but with rubbishdata.Solution:Build digital standalone verification test environment aware of analog content (constrainmeaningful data for USE-CASEs, Min-Mid-Max VGA code, ADC start-up, etc.)Digital verification techniques like assertions, coverage are directly applicable to analog design.Interface monitors can be re-connected from digital boundary to analog blocks instances.Top-level mixed mode verification is just rerun of existing digital test.UVM based digital verification environment is easily reconfigurable for co-simulationenvironment.
  12. 12. May 1, 2013ConclusionMixed mode design & verification is iterative processTop – Down approach is must for parallel executionModeling at early design stages helps with implementation and verificationEffective reuse of digital verification environment require top-level verification planningMixed-Mode Functional Verification can be a DIGITAL task executed in ANALOG environmentMixed-Mode Design & Verification is team work – COMMUNICATION matter
  13. 13. May 1, 2013Thank You!jan.pleskac@s3group.com

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