The document discusses different approaches to implementing page tables in hardware. It describes: 1) Using dedicated high-speed registers to store small page tables. For example, the PDP-11 stored its 16-bit page table of 8 entries in registers. 2) Storing large page tables in main memory, using a page table base register and translation lookaside buffer (TLB) to cache recent translations and avoid multiple memory accesses. 3) TLBs store a cache of recent page table entries and allow fast translation of logical to physical addresses if the page is cached, falling back to memory if not present.

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1. Hardware Implementation Of Page Table
2. Types of page tables
Submitted by:
Sukhraj singh
449/12
1241916

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HARDWARE IMPLEMENTATION OF PAGE TABLE
When Page Table Is Reasonably Small
1. In this case page table is implemented by the use of dedicated registers.
2. As every memory access go through the paging map, these registers should be
built with very high speed logic to make the paging address translation efficient.
3. Brief working: the CPU dispatcher reloads these registers just as it reloads the
other register .instructions to load or modify the page table registers are only in the
hand of operating system that can change the memory map
4. Example: DEC PDP-11 is the example of such an architecture as its address
consists of 16 bits , and the page size is 8kb .the page table thus consist of eight
entries that are kept in fast register .
Thus the use of registers for the page table is satisfactory if page table is small
like 256 entries
When Page Table Is Very Large
1. Use of fast registers not feasible
2. Page table is kept in main memory and there is Page-table base register (PTBR)
that points to the page table. Page-table length register (PRLR) indicates size of
the page table.
Advantage: changing page tables requires changing only one register , as a result
the context switch time reduces.
Disadvantage: In this scheme every data/instruction access requires two memory
accesses. One for the page table and one for the data/instruction thus the memory
access is slowed by the factor of two. this delay would be intolerable under most
circumstances.

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3.The problem is solved using translation look –aside buffer (TLB)
4. The CPU's memory management unit (MMU) stores a cache of recently used
mappings from the operating system's page table. This is called the translation look
a side buffer (TLB).
5. The TLB is associative, high speed memory . each entry in TLB consists of two
parts : a key and a value. When associative memory is presented with an item is
compared with all keys simultaneously. If the item is found, the corresponding
value field is returned .
6. The seach is fast ,the hardware is expensive .
7.Working With Translation Look –Aside Buffer (TLB): the TLB contains only
a few of the page table entries . when a logical address is generated by the CPU ,
its page number is presented to the TLB . if the page number is found , its frame
number is immediately available and is used to access memory . if the page
number is not in TLB (known as TLB miss ), a memory reference to the page table
must be made . When the frame number is obtained , we can use it to access
memory . in addition , we add the page number and frame number to the tlb , so
they will be found quickly on next reference.

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EXAMPLE SHOWING WORKING OF TLB

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TYPES OF PAGE TABLE
Hierarchical Page Tables:
1.also Known as Multilevel Paging
2.The page table might be too big to fit in a contiguous space, so we may have a
hierarchy with several levels
3.Break up the logical address space into multiple page tables.
A simple technique is a two-level page table, three-level page table
Example :
Two-Level Paging Example
A logical address (on 32-bit machine with 4K page size) is divided into:
 a page number consisting of 20 bits.
 a page offset consisting of 12 bits.
Since the page table is paged, the page number is further divided into:
 a 10-bit page number.
 a 10-bit page offset.
Thus, a logical address is as follows:
where pi is an index into the outer page table, and p2 is the displacement within
the page of the outer page table.

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Fig: Address-translation scheme for a two-level 32-bit paging architecture
Hash page table
1.Common in address spaces > 32 bits.
2.The virtual page number is hashed into a page table. This page table contains a chain of
elements hashing to the same location.
3.Each element consists of three fields:
(1) the virtual page number,
(2) the value of the mapped page frame,
(3) a pointer to the next element in the linked list.
4.Virtual page numbers are compared in this chain searching for a match. If a match is found,
the corresponding physical frame is extracted.

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Inverted Page Table
1. The inverted page table (IPT) combines a page table and a frame table into one data
structure.
2. One entry for each virtual page number & real page of memory.
3. Entry consists of the virtual address of the page stored in that real memory location, with
information about the process that owns that page.
Advantage: Decreases memory needed to store each page table
Disadvantage :
1. Increases time needed to search the table when a page reference occurs.
2. There is only one virtual page entry for every physical page, one physical page cannot have
two (or more) shared virtual addresses.
Fig: Inverted Page Table Architecture