Device Modeling of Delay using PSpice

1. IC Modeling
Device Modeling of
Delay
Using PSpice
15OCT2014
Bee Technologies Inc
Tsuyoshi Horigome

2. Equivalent Circuit
R1
100MEG
R2
100MEG
Delay _OSC
Delay _IN
00
1
IN-
OUT+
OUT-
IN+
G1
if (V(Delay _IN)<1 & V(Delay _OSC)>3,1m,0)
GVALUE
IN-
OUT+
OUT-
IN+
G2
if (V(Delay _IN)>3 & V(Delay _OSC)>3,1m,0)
GVALUE
C1
1n
IC = 0
IN-
OUT+
OUT-
IN+
G3
if (V(CAL_01)>3.5,1m,0)
GVALUE
IN-
OUT+
OUT-
IN+
G4
if (V(CAL_01)<0.01,1m,0)
GVALUE
R3
100MEG
0 0
0
0
0
CAL_01 IN_Delay _P
IN+
IN-
OUT+
OUT-
E1
if (V(IN_Delay _P,IN_Delay _M)>0.01,5,0)
EVALUE
IN+
IN-
OUT+
OUT-
E2
if (V(Delay _OUT)>4,{LV},{HV})
EVALUE
R4
10
C2
10p
IC = 0
1
R5
100MEG
0
0
0
0
RL
100MEG
0
Delay _OUT
V
V
V
IN_Delay _M
PARAMETERS:
HV = 2.5
LV = 1.25
V1
5Vdc
V2
TD = 0
TF = 1n
PW = 1u
PER = 10u
V1 = 0
TR = 1n
V2 = 5
0
0
Delay

3. Simulation
Input
Output
OSC
Node of CAL_01
Delay Time