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Receiver Testing to Third GenerationStandardsJit Lim, 30th June 2011
Agenda1.Introduction2. Stressed Eye3. System Aspects4. Beyond Compliance5. ResourcesPCI Express is a trademark of PCI-Sig,...
Introduction                                                                       • Latest Generation                    ...
Introduction - Basics                                                       At the simplest level, receiver               ...
Introduction - Trends                                                    At the simplest level, receiver                  ...
Introduction - Trends                                                                 At the simplest level, receiver     ...
Introduction - Trends                                                                 At the simplest level, receiver     ...
Introduction - Trends                                                                 At the simplest level, receiver     ...
Introduction - Trends                                                                 At the simplest level, receiver     ...
Agenda1. Introduction2.Stressed Eye3. System Aspects4. Beyond Compliance5. Resources10   30th June 2011    Receiver Testin...
Agenda1. Introduction2.Stressed Eye                                    • Changing Test Signal Recipes                     ...
Receiver Testing (a.k.a “Jitter Tolerance”) Review    Test receiver for error free operation (0 BER) while     stressed w...
Receiver Testing (a.k.a “Jitter Tolerance”) Review    Test receiver for error free operation (0 BER) while     stressed w...
Traditional stressed eyeGeneric Stress Recipe                                                            typically compose...
Traditional stressed eye     Generic Stress Recipe                                                                      ty...
PCIe 3USB 3.0 Stress Recipe                                                                            USB 3             ...
PCIe Gen 3 Stress Recipe                                                                                           PCIe 3 ...
PCIe Gen 3 Stress Recipe                                                                                  PCIe 3   - Inte...
PCIe Gen 3 Stress Recipe                                                                                      PCIe 3   - ...
PCIe Gen 3 Stress Recipe                                                                                      PCIe 3   - ...
USB 3.0 Stress Recipe                                                                         PCIe 3- Calibration         ...
PCIe Gen 3: Example                                                           Gen 3 CBB Riser          PCIe 3          Ad...
Agenda1. Introduction2. Stressed Eye3.System Aspects4. Beyond Compliance5. Resources23   30th June 2011    Receiver Testin...
Agenda1. Introduction2. Stressed Eye3.System Aspects                                              • Closed Eye Return Sign...
PCIe Gen 3:                                                                                                            PCI...
PCIe Gen 3:                                                                                            PCIe 3   Test Setu...
Loopback1. Loopback usually specified in the standard with a   method to initiate it.   1. IC companies have control over ...
PCIe 3Loopback – USB3                                                                        USB 3    • USB3 specifies a ...
PCIe 3     Loopback – PCIe 3                                                                          USB 3• PCIe 3 loopb...
PCIe 3   Clocking – PCIe3                                                                         USB 3• Add-in cards tak...
PCIe 3   Clocking                                                                         USB 3• Practical setup used for...
Agenda1. Introduction2. Stressed Eye3. System Aspects4.Beyond Compliance5. Resources When a Device Fails… What Next?32   3...
Beyond ComplianceBERTScope = Debug/Characterization                      1. Click a control                               ...
Beyond ComplianceThe BERTScope Analysis Tools Besides being a BERT, the BERTScope’s “Scope” functionality brings benefits...
Agenda1. Introduction2. Stressed Eye3. System Aspects4. Beyond Compliance5.Resources35   30th June 2011    Receiver Testin...
ResourcesExtensive applicationinformation at:www.tek.comPCI Express : PCI-Sig, www.pcisig.comUSB: USB-IF, www.usb.org36   ...
Summary                                                                       High Speed Receiver Test                    ...
.Questions?38   30th June 2011   Receiver Testing to Third Generation Standards
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Receiver Testing To Third Generation Standerds

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PPT by EDN in association with Tektronix on Receiver testing (5Gbits/s). It discuss on USB 3.0 & PCI Express Gen 3

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Receiver Testing To Third Generation Standerds

  1. 1. Receiver Testing to Third GenerationStandardsJit Lim, 30th June 2011
  2. 2. Agenda1.Introduction2. Stressed Eye3. System Aspects4. Beyond Compliance5. ResourcesPCI Express is a trademark of PCI-Sig, www.pcisig.comUSB is a trademark of USB-IF, www.usb.org2 30th June 2011 Receiver Testing to Third Generation Standards
  3. 3. Introduction • Latest Generation Add-In Card Computer Standards have some common trends. • We’ll use PCI Express Gen 3 as our main example End Point • We’ll also use USB 3.0 PCI Express • Similar themes are Gen 3 Link emerging in other new standards such as IEEE 100GbE etc. Host or Root ComplexMotherboard • Conceptual example PCI Express link shown. 3 30th June 2011 Receiver Testing to Third Generation Standards
  4. 4. Introduction - Basics At the simplest level, receiver testing is composed of: 3. 1. Send impaired signal to the receiver under test 2. The receiver decides whether 2. the incoming bits are a one or a zero 1. 3. The chip loops back the bit • Pattern Generator stream to the transmitter • Stress 4. 4. The transmitter sends out exactly the bits it received • Error Counter 5. 5. An error counter compares the bits to the expected signal and looks for mistakes (errors)4 30th June 2011 Receiver Testing to Third Generation Standards
  5. 5. Introduction - Trends At the simplest level, receiver testing is composed of: 3. 1. Send impaired signal to theHigher receiver under testspeeds oncheap 2. The receiver decides whetherchannel 2. the incoming bits are a one ormaterials a zero 1.causingclosed 3. The chip loops back the bit • Pattern Generatoreyes from stream to the transmitter • StressISI and 4.crosstalk 4. The transmitter sends out exactly the bits it received • Error Counter 5. 5. An error counter compares the bits to the expected signal and looks for mistakes (errors)5 30th June 2011 Receiver Testing to Third Generation Standards
  6. 6. Introduction - Trends At the simplest level, receiver testing is composed of: Test signal is changing: 3. • Vertical eye closure 1. Send impaired signal to theHigher • Closed eye receiver under testspeeds on Calibration is difficultcheap 2. The receiver decides whetherchannel 2. the incoming bits are a one ormaterials a zero 1.causingclosed 3. The chip loops back the bit • Pattern Generatoreyes from stream to the transmitter • StressISI and 4.crosstalk 4. The transmitter sends out exactly the bits it received • Error Counter 5. 5. An error counter compares the bits to the expected signal and looks for mistakes (errors)6 30th June 2011 Receiver Testing to Third Generation Standards
  7. 7. Introduction - Trends At the simplest level, receiver testing is composed of: Test signal is changing: 3. • Vertical eye closure 1. Send impaired signal to theHigher • Closed eye receiver under testspeeds on Calibration is difficultcheap 2. The receiver decides whetherchannel 2. Increased use of equalization the incoming bits are a one ormaterials forcing changes in testing: speed a zero 1.causing negotiation & Tx controlclosed 3. The chip loops back the bit • Pattern Generatoreyes from stream to the transmitter • StressISI and 4.crosstalk 4. The transmitter sends out exactly the bits it received • Error Counter 5. 5. An error counter compares the bits to the expected signal and looks for mistakes (errors)7 30th June 2011 Receiver Testing to Third Generation Standards
  8. 8. Introduction - Trends At the simplest level, receiver testing is composed of: Test signal is changing: 3. • Vertical eye closure 1. Send impaired signal to theHigher • Closed eye receiver under testspeeds on Calibration is difficultcheap 2. The receiver decides whetherchannel 2. Increased use of equalization the incoming bits are a one ormaterials forcing changes in testing: speed a zero 1.causing negotiation & Tx controlclosed 3. The chip loops back the bit • Pattern Generatoreyes from stream to the transmitter • Stress Attaining Loopback is often 4.ISI and problematic.crosstalk 4. The transmitter sends out exactly the bits it received • Error Counter 5. 5. An error counter compares the bits to the expected signal and looks for mistakes (errors)8 30th June 2011 Receiver Testing to Third Generation Standards
  9. 9. Introduction - Trends At the simplest level, receiver testing is composed of: Test signal is changing: 3. • Vertical eye closure 1. Send impaired signal to theHigher • Closed eye receiver under testspeeds on Calibration is difficultcheap 2. The receiver decides whetherchannel 2. Increased use of equalization the incoming bits are a one ormaterials forcing changes in testing: speed a zero 1.causing negotiation & Tx controlclosed 3. The chip loops back the bit • Pattern Generatoreyes from stream to the transmitter • Stress Attaining Loopback is often 4.ISI and problematic.crosstalk 4. The transmitter sends out exactly the bits it received • Error Counter 5. Returned signal is often also a 5. An error counter compares closed eye, making error the bits to the expected signal counting difficult and looks for mistakes (errors)9 30th June 2011 Receiver Testing to Third Generation Standards
  10. 10. Agenda1. Introduction2.Stressed Eye3. System Aspects4. Beyond Compliance5. Resources10 30th June 2011 Receiver Testing to Third Generation Standards
  11. 11. Agenda1. Introduction2.Stressed Eye • Changing Test Signal Recipes • Channel Considerations3. System Aspects • Calibration Challenges4. Beyond Compliance5. Resources11 30th June 2011 Receiver Testing to Third Generation Standards
  12. 12. Receiver Testing (a.k.a “Jitter Tolerance”) Review Test receiver for error free operation (0 BER) while stressed with input jitter/impairments. Calibrated jitter/stress is added to Pattern Generator (PG), output is increased until receiver experiences bit errors, or test limit is reached. Test often repeated at another jitter frequency, results are plotted. Pattern Stress Generator Impairments Pattern High Speed Amplifiers etc.12 30th June 2011 Receiver Testing to Third Generation Standards
  13. 13. Receiver Testing (a.k.a “Jitter Tolerance”) Review Test receiver for error free operation (0 BER) while stressed with input jitter/impairments. Calibrated jitter/stress is added to Pattern Generator (PG), output is increased until receiver experiences bit errors, or test limit is reached. Test often repeated at another jitter frequency, results are plotted. Pattern Stress • Stress recipe varies by Generator Impairments standard. In theory it emulates the system impairments for the expected use. Pattern High Speed • Higher data rates mean closed Amplifiers eyes and crosstalk are bigger etc. issues.13 30th June 2011 Receiver Testing to Third Generation Standards
  14. 14. Traditional stressed eyeGeneric Stress Recipe typically composed of: • PRBS data signal • + Pre-emphasis • + Jitter such as Random (RJ) and Sinusoidal (SJ) Tx Eq • + Channel Inter-Symbol Interference (ISI) PRBS Test Channel Gen Equipment RJ SJ Source Source14 30th June 2011 Receiver Testing to Third Generation Standards
  15. 15. Traditional stressed eye Generic Stress Recipe typically composed of: Pre-Emphasis 2. • PRBS data signal • + Pre-emphasis • + Jitter such as Random (RJ) and Sinusoidal (SJ) Tx Eq • + Channel Inter-Symbol Interference (ISI)Clean PRBS TestSignal 1. Channel Gen Equipment RJ SJ Source Source 5. ISI Resulting Stressed Eye 6.RJ 3. SJ 4. 15 30th June 2011 Receiver Testing to Third Generation Standards
  16. 16. PCIe 3USB 3.0 Stress Recipe USB 3  USB 3.0 uses a representative channel – a long USB cable, which at 5Gb/s causes a Tx Eq closed eye to be formed. PRBS Test Channel Gen Equipment RJ SJ Source Source Resulting stressed eye is closed16 30th June 2011 Receiver Testing to Third Generation Standards
  17. 17. PCIe Gen 3 Stress Recipe PCIe 3 - Overview USB 3 PCI Express Gen 3 uses a long circuit board channel that closes the eye, and two forms of vertical Tx Eq eye closure (‘Interference’). 8G PRBS Cal. Replica Test Combiner Gen Channel Channel Equipment Post- RJ SJ processing Source Source Diff CM Interference Interference Eye Height Adjust(Taken from PCI Express Base Spec, Figure 4-71)17 30th June 2011 Receiver Testing to Third Generation Standards
  18. 18. PCIe Gen 3 Stress Recipe PCIe 3 - Interference USB 3Differential Mode interference is used to simulate uncorrelated Data +crosstalk. Operating PCIe3 systems have multiple (x16) lanes sitting Tx Eqright next to each other with high likelihood of coupling from adjacent Data -signals. 8G PRBS Cal. Replica Test CombinerCommon Mode interference is used to simulate modulated voltage Equipment Gen Channel Channel Data +and ground rails. It is difficult to completely filter out switchingsupplies in a PCIe3 system and other low frequency modulation effects Data - Post-beyond the loop bandwidth of the system. RJ processing SJ Source Source Diff CM Interference Interference EH Adjust18 30th June 2011 Receiver Testing to Third Generation Standards
  19. 19. PCIe Gen 3 Stress Recipe PCIe 3 - Channel USB 3• Depending upon Host or Add-in Card, different test Tx Eq fixtures/combinations are used.• ISI is large 8G PRBS to mean the enough Cal. Replica Test Combiner Eye is closed at the receiver. Gen Channel Channel Equipment Post- RJ SJ processing Source Source Diff CM Interference Interference EH Adjust19 30th June 2011 Receiver Testing to Third Generation Standards
  20. 20. PCIe Gen 3 Stress Recipe PCIe 3 - Calibration USB 3 Long waveform capture by Real Time Scope Tx Eq 8G PRBS Cal. Replica Test Combiner Gen Channel Channel Equipment Post- Post-processing bySJ RJ software. processing Several complex elements are accommodated in Source Source software including the IC package and elements Diff CM within the IC including the equalizer. Interference Interference EH Adjust This is still in flux – Correlation work ongoing between simulation and direct measurement and analysis techniques. Being refined at Plugfests20 30th June 2011 Receiver Testing to Third Generation Standards
  21. 21. USB 3.0 Stress Recipe PCIe 3- Calibration USB 3  Long waveform capture by Real Time Scope Tx Eq PRBS Test Channel Gen Equipment Post- RJ SJ processing Source Source Mature standardwith fully automated solutions for stresscalibration and good correlation21 30th June 2011 Receiver Testing to Third Generation Standards
  22. 22. PCIe Gen 3: Example Gen 3 CBB Riser PCIe 3 Add-In Card Stress Calibration USB 3 Gen 2 CLB SI Combiner Rx Lane 0 + + In Out - - Gen 3 CBB (Main) To RT Scope for Tx Lane 0 calibration (Rear) Last Cal. details being refined. This setup being successfully used at Plugfests22 30th June 2011 Receiver Testing to Third Generation Standards
  23. 23. Agenda1. Introduction2. Stressed Eye3.System Aspects4. Beyond Compliance5. Resources23 30th June 2011 Receiver Testing to Third Generation Standards
  24. 24. Agenda1. Introduction2. Stressed Eye3.System Aspects • Closed Eye Return Signal • Loopback4. Beyond Compliance • Clocking5. Resources24 30th June 2011 Receiver Testing to Third Generation Standards
  25. 25. PCIe Gen 3: PCIe 3 Test Setup with DUT USB 3 1. Stressed Eye is Tx (Out) intentionally closed SI Combiner + + In Out Rx (In) - - Interference DUT 2. DUT and Test Cards have enough ISI to mean returned signal is also closed.  3. Can’t count errors on closed eye25 30th June 2011 Receiver Testing to Third Generation Standards
  26. 26. PCIe Gen 3: PCIe 3 Test Setup with DUT & Eye Opener USB 3 + + In Out - - • Use external ‘eye opener’ equalizer to allow error counting • E.g. National Semiconductor Repeater DS100BR410EVK-4 www.national.com/26 30th June 2011 Receiver Testing to Third Generation Standards
  27. 27. Loopback1. Loopback usually specified in the standard with a method to initiate it. 1. IC companies have control over their chips and can usually force the chip into loopback 2. Often a pattern sent from a generator of a particular sequence is supposed to cause it • Generator also. 1. Obeying loopback rules is not part of compliance test, so rules frequently broken. 2. Attaining loopback at Plugfests can be • Error painful. Counter2. Devices often fall out of loopback during testing.3. Often hard to know device has attained loopback (waveform analyzer such as BERTScope ED often useful)27 30th June 2011 Receiver Testing to Third Generation Standards
  28. 28. PCIe 3Loopback – USB3 USB 3 • USB3 specifies a sequence of bits to initiate it that forms a low frequency square wave (“LFPS”).• Frequently test equipment will use a separate generator for loopback initiation which switches out once loopback is • Generator attained. Tek USB Switch with • Error LFPS Counter LFPS DUT Tek USB Software Loopback Control28 30th June 2011 Receiver Testing to Third Generation Standards
  29. 29. PCIe 3 Loopback – PCIe 3 USB 3• PCIe 3 loopback is more complicated. 1. Speed negotiation – natively 2.5GT/s, “Brute Force” needs to negotiate up to 8GT/s patterns for 2. Equalization negotiation – receiver BERTScope controls transmitter pre-emphasis and find optimum Tx & Rx settings – • Generator 500ns compliance response time limit 3. Setting of device into Loopback• Initially “brute force” with static Diagnostic • Error patterns state Counter• Now compliant state machine machine (500us)• Feedback from Plugfests is that Add-In Card manufacturers aren’t implementing equalization negotiation yet. Instead test with limited number of pre-emphasis presets (3)29 30th June 2011 Receiver Testing to Third Generation Standards
  30. 30. PCIe 3 Clocking – PCIe3 USB 3• Add-in cards take in a 100 MHz clock. • This is straight forward, test equipment 1. 100 MHz Clock usually provides sub-rate clock easily (1).• Motherboards are harder – DUT provides 2. 100 MHz Clock 100 MHz clock (2), but test equipment needs 8 GHz clock. • Could derive clock from 8 GT/s data signal using clock recovery (3). Device margins are small enough to mean worries about extra jitter added by the 3. 8 GT/s Data transmitter. • Ideally use well controlled clock multiplier from system 100 MHz clock.30 30th June 2011 Receiver Testing to Third Generation Standards
  31. 31. PCIe 3 Clocking USB 3• Practical setup used for Plugfests to multiply system clock (2)• Clock multiplied in two stages to preserve compliant loop bandwidth & peaking 2. 100 MHz Clock100 MHz Ref From CLB 8GHz to BERTScope 8GHz to BERTScope Detector Clock InGenerator Ext. Clock In31 30th June 2011 Receiver Testing to Third Generation Standards
  32. 32. Agenda1. Introduction2. Stressed Eye3. System Aspects4.Beyond Compliance5. Resources When a Device Fails… What Next?32 30th June 2011 Receiver Testing to Third Generation Standards
  33. 33. Beyond ComplianceBERTScope = Debug/Characterization 1. Click a control 3. Changes button in the UI 2. Adjust happen instantly Easy adjust with turn of the knob You may need to try lots of different signal conditions May want to monitor BER while changing stress conditions on the fly33 30th June 2011 Receiver Testing to Third Generation Standards
  34. 34. Beyond ComplianceThe BERTScope Analysis Tools Besides being a BERT, the BERTScope’s “Scope” functionality brings benefits that complement those of the Tektronix scopes Analysis tools are full featured and easy to use BER  Frees up the scope for other tasks PLUS…  Eye diagram for quick diagnosis of synchronization and BER failure issues  Debug challenging signal Jitter Tolerance integrity problems Jitter Jitter Decomposition Error Correlation34 30th June 2011 Receiver Testing to Third Generation Standards
  35. 35. Agenda1. Introduction2. Stressed Eye3. System Aspects4. Beyond Compliance5.Resources35 30th June 2011 Receiver Testing to Third Generation Standards
  36. 36. ResourcesExtensive applicationinformation at:www.tek.comPCI Express : PCI-Sig, www.pcisig.comUSB: USB-IF, www.usb.org36 30th June 2011 Receiver Testing to Third Generation Standards
  37. 37. Summary High Speed Receiver Test Solutions from Tektronix: Higher speeds on cheap channel BERTScope Family materials causing closed eyes from ISI and crosstalk Increased use of equalization forcing changes in testing: speed, equalization negotiation & Tx control Test signal is changing:  Vertical eye closure  Closed eye Arbitrary Waveform Calibration is evolving Generator (AWG) Family Attaining Loopback is often problematic. Returned signal is often also a closed eye, meaning eye needs opening before error counting37 30th June 2011 Receiver Testing to Third Generation Standards
  38. 38. .Questions?38 30th June 2011 Receiver Testing to Third Generation Standards

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