Novel pixel readout system-on-chip (SoC) has been designed to meet the ever increasing demands of the present and future generation of LHC pixel detectors. The FE-I4 architecture has higher luminosity and rate capability as well as a smaller single pixel area compared to its predecessors and is currently the most complex chip designed for particle physics applications. The IC has been designed in 130nm CMOS technology. The state of the art of the FE-I4 will be presented, including the architecture overview, simulation results, preliminary measurements and a global design flow.

1. The FE-I4 Pixel Readout System-on-Chip
for ATLAS Experiment Upgrades
Tomasz Hemperek on behalf of ATLAS Pixel Collaboration

2. ATLAS Detector
21/09/20102
Pixel Detector:
 3 barrels
 112 staves
 1744 modules
 80 million channels
IBL = New Insertable B-Layer at 33 mm
IBL
Beam pipe
Existing B-layer

3. Current Pixel Detector Module
21/09/20103
 16-front-end chip (FE-I3)
module with a module
controller chip (MCC)
 Planar n-on-n DOFZ silicon
sensors, 250 μm thick
 Designed for for 1 x 1015 1MeV
neq fluence and 50 MRad

4. Front End Chip
FE-I3 FE-I4
21/09/20104
Pixel Size [μm2] 50×400 50×250
Pixel Array 18×160 80×336
Chip Size [mm2] 7.6×10.8 20.2×19.0
Active Fraction 74 % 89 %
Output Data Rate [Mb/s] 40 160
Transistor Count [M] - ~80
2mm16.8mm
8mm2.8mm
7.6mm
20.2mm

5. Double Hit Column Waiting (FE-I3)
21/09/20105
Inefficiencies
ToT
Vth
Lost LE
Time over Threshold ~Q
Vth
LE
1. Record
2. Transfer
3. Trigger
4. Transmit

6. Motivation
21/09/20106
0%
20%
40%
60%
80%
100%
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.5 2 2.5 3 3.5 4 4.5 5
Hit probability per Double-Column
Inefficiency for FE-I3 at 3.7cm
Total Double Hit Wrong Bunch Crossing Busy Pixel
LHC
IBL
SLHC

7. New FE improvements
21/09/20107
 New technology
 Smaller pixel size
 Bigger chip size and active area
 New digital architecture
 New analog pixel
 Reduce number of external components
 New powering schemes
 Decrease cost (per area)
 Better radiation hardness

8. FE-I4 Functional Overview
21/09/20108
 Pads / RX /TX
 Double Column
 End Of Chip Logic
 Data Output Block
 Phase Lock Loop
 Command Decoder
 SEU-Hard Memory
 DACs & Reference
 Power
 4 Pixel Region
 Pixel Array

9. Analog Pixel
21/09/20109
150 µm
50µm
Cc
Cf2Cf1
Preamp Amp2
feedbox feedbox
Inj0
Inj1
injectIn
Cinj1
Cinj2
+
local
feedback
tune
FDAC
4 Bit
Vfb
+
local
threshold
tune
TDAC
5 Bit
Vfb2
+
-
HitOut
NotKill
Vth
 Two-stage architecture
optimized for low power, low
noise and fast rise time
 Additional gain Cc/Cf2~ 6
 More flexibility on choice of Cf1
 Charge collection less
dependent on detector
capacitor
 Decoupled from preamplifier
DC potential shift caused by
leakage
 Local DACs for tuning feedback
current and global threshold
 Charge injection circuitry
Preamp
Amp2
FDAC
TDAC
discri

10. FE-I4-P1 (Prototype)
21/09/201010
 61x14 pixel array
 Silicon proven
 RadHARD up to 200MRad
(loaded ~400 fF)
<ENC> = ~65 e
Noise Measurements
Noise Measurements (Irradiation)

11. 4 Pixel Region
21/09/201011
- Analog - Digital
0
5000
10000
15000
20000
25000
30000
1 2 3 4 5 6
central module - ϕ direction
Mean: 1.76
Cluster size projection
0
5000
10000
15000
20000
25000
30000
1 2 3 4 5 6
central module - Z direction
Mean: 1.87  4 analog pixels are connected to one
digital region
 Analog pixels can operate and be
tested independently from digital part
Pixel organization

12. Digital Region (simplified)
21/09/201012
- Hit Processing
- ToT Counter
- ToT Memory
- Latency Counter
- Triggering/Readout
 Receiving hit
 Start ToT counter
 Assign first free memory
and latency counter
 Generate trailing edge
 Store ToT value
 Check for trigger when
latency counter finished
 Indicate ready to read status
(release token)
 Release memory after read
 Read memory
 Generate leading edge

13. Regional Buffer Overflow FE-I4 Inefficiency (3.7cm)
21/09/201013
FE-I4 Inefficiency
Memories
Simulation
IBL 10xLHC
5 0.047% 2.19%
6 0.011% 0.65%
7 <0.01% 0.16%
0%
1%
2%
3%
4%
Hit probability per pixel
Total Double Hit Buffer Overflow
LHC
IBL
SLHC
Mean ToT = 4

14. Column Readout
21/09/201014
Token
Bus
End of Chip
Logic
 Two prioritized token scenario
(column and periphery level)
 One data bus
 End of column logic selects
column to read
 Chip control logic controls
trigger and read
 Data is always read in the
same order
 All buses including address
(thermal encoded) protected
with hamming encoding

15. Pixel Array Layout
21/09/201015
Digital
Region
Analog
Pixel
50x250µm

16. Framing / Transmission
21/09/201016
Re-Formatting
EventBuilder
Asynchronous
redundantFIFO
(8x32bit)
8b10bEncoding
Framing
Serializer
Readout Control
DataSwitch
Hamming
Encoded
Pixel
Data
Header
Service
TX
40MHz Clock Domain
160MHz Clock Domain
Re-formatting: Data reduction about 25% and 8-bit word format
HammingDecoder

17. DC/DC
Serial Power
21/09/201017
Powering
Shunt
LDO
FE-I4
1.2V1.5V
Shunt
LDO
Shunt
LDO
FE-I4
1.2V1.5V
Shunt
LDO
Iin
Iout
2x DC/DC LDO
FE-I4 1.2V1.5V
3.3V
2x DC/DC LDO
FE-I4 1.2V1.5V
 Saving cable
material budget
 Reduction of cable
power losses

18. New Module Concept
21/09/201018
 Sensor technology independent.
 Decision on sensors after prototyping with
FE-I4
 Minimum amount of external components
FE-I4
Sensor
Flex

19. Design Flow
21/09/201019
 Design in “big A small D” methodology
 Blocks designed and verified individually
 Full chip digital and mixed-signal verification
 Work synchronization with integrated Revision Control System
 Big chip = many difficulties with software and PDK!
Analog Block
Design & Verification
Digital Block
Design & Verification
Integration
Full Chip
Verification

20. Verification
21/09/201020
 Full chip verification based on Open Verification Methodology
(OVM) with multiple physics based and random test
ANALOG
ARRAY
(digital part)
DIGITAL
ARRAY
END OF COLUMN
END OF
CHIP
COMMAND
DECODER
REGISTER
MEMORY
PLL
PLL
DATA
OUTPUT
- verilog model
- Implementation (RTL/gate)
FE-I4
DETECTOR
(PIX)
OUTPUT
(RECEIVE)
MANUAL
SLOW
COMMAND
(CMD)
Modeling Interfaces

21. Conclusion
21/09/201021
 Project duration: ~3 years
 Design team: ~21 persons+
 FE-I4A last official shipping date: This Thursday (23rd September 2010)
 Test setup readiness ramping-up, on time for IC back
 Tests: Wafer, single-chip, bump-bonded (planar, 3D, diamond), irradiation
Design team
Bonn: D. Arutinov, M. Barbero, T. Hemperek, A. Kruth,
M. Karagounis
CPPM: D. Fougeron, F. Gensolen, M. Menouni
Genova: R. Beccherle, G. Darbo
LBNL: S. Dube, D. Elledge, J. Fleury (LAL),
M. Garcia-Sciveres, D. Gnani, F. Jensen, A. Mekkaoui
NIKHEF: V. Gromov, R. Kluit, J.D. Schipper, V. Zivkovic

22. Extra Slides
21/09/201022

23. Test Chips
21/09/201023
FE-I4-P1
LDO
Regulator
Charge
Pump
Current
Reference
DACs
Control
Block
Capacitance
Measurement
FE-I4-P1
61x14 Array
SEU test IC
4-LVDS Rx/Tx
ShuLDO+trist
LVDS/LDO/10b-
DAC
turboPLL:
PLL core + PRBS +
8b10b coder + LVDS
driv
low power
discri.

24. Clocking
21/09/201024
 Phase Lock Loop (PLL)
type 2
 Voltage Controlled
Oscillator (VCO) at 640
MHz (x16)
 Lost of Lock Detection
 2 Independent output
multiplexers
 Silicon Proven

25. LVDS TX LVDS RX
21/09/201025
Data Transmission
M3 M4
M5 M6
CMFBCMOS
driver
D
D
D
VofsVcm
Vbp
Vbn
5pF
5pF
100k 100k
TX
TX
M11
M12 M13 M14
M8
M9 M10
M4 M5 M6 M7
M1
M2 M3
RX RX
M14
M15 M16
M18
M17
OUT
M20
M19
M21 M22
 Transition speed up to 330 MHz
 RadHARD up to 200MRad
 Silicon Proven

26. Shunt-LDO
21/09/201026
+
-
+
-
+
-
Iin
Iout
Vref
Vout
A1
A2
A3
M1
M2
M3
M4
M5
R1
R2
Vin
Iload
R3
M6
Ishunt
 Combination of LDO and shunt transistor
 „Shunt-LDO“ regulators having completely different output voltages can
be placed in parallel without any problem regarding mismatch & shunt
current distribution
 „Shunt-LDO“ can cope with an increased supply current if one FE-I4
does not contribute to shunt current e.g. disconnected wirebond
 Can be used as an ordinary LDO when shunt is disabled
 Silicon Proven

27. RadHARD Memory
21/09/201027
 Silicon Proven
 RadHARD and SEU Tolerant